Re: [edk2-devel][edk2-platforms][PATCH v4] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
Looks good to me. Please get RB by atleast one of the Pkg maintainers.
With that:
Reviewed-by: Sai Chaganty
-Original Message-
From: Kuo, Ted
Sent: Tuesday, January 2, 2024 1:41 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel
; Desimone, Nathaniel L
; Dong, Eric ; S, Ashraf
Ali ; Duggapu, Chinni B ;
Gao, Liming
Subject: [edk2-devel][edk2-platforms][PATCH v4] MinPlatformPkg: Support
SecFspWrapperPlatformSecLib in X64
https://bugzilla.tianocore.org/show_bug.cgi?id=4623
1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
2.Made changes in common files to support both IA32 and X64.
3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP.
- PcdFspWrapperBfvforResetVectorInFsp
- PcdFsptUpdHeaderRevision
- PcdFsptArchUpdRevision
Cc: Sai Chaganty
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Eric Dong
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Liming Gao
Signed-off-by: Ted Kuo
---
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 ++-
.../Ia32/SecEntry.nasm| 4 +-
.../SecFspWrapperPlatformSecLib.inf | 9 +-
...pWrapperPlatformSecLibResetVectorInFsp.inf | 101 +
.../SecGetPerformance.c | 11 +-
.../SecPlatformInformation.c | 8 +-
.../SecRamInitData.c | 73 +--
.../X64/PeiCoreEntry.nasm | 202 ++
.../X64/SecEntry.nasm | 71 ++
.../X64/Stack.nasm| 72 +++
.../Ia32 => Include}/Fsp.h| 6 +-
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 17 +-
12 files changed, 565 insertions(+), 34 deletions(-) create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLibResetVectorInFsp.inf
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
rename
Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32
=> Include}/Fsp.h (79%)
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
index 7c0f605b92..24c18f25b8 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/FsptCoreUpd.h
@@ -1,6 +1,6 @@
/** @file -Copyright (c) 2017, Intel Corporation. All rights
reserved.+Copyright (c) 2017 - 2024, Intel Corporation. All rights
reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -10,6 +10,7
@@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1) +#if FixedPcdGet8 (PcdFsptArchUpdRevision) <= 1 /** Fsp T
Core UPD **/ typedef struct {@@ -34,6 +35,28 @@ typedef struct {
**/ UINT8 Reserved[16]; } FSPT_CORE_UPD;+#else+/** Fsp
T Core UPD+**/+typedef struct {++/** Offset 0x0040+**/+ EFI_PHYSICAL_ADDRESS
MicrocodeRegionBase;++/** Offset 0x0048+**/+ UINT64
MicrocodeRegionSize;++/** Offset 0x0050+**/+ EFI_PHYSICAL_ADDRESS
CodeRegionBase;++/** Offset 0x0058+**/+ UINT64
CodeRegionSize;+} FSPT_CORE_UPD;+#endif #pragma pack() diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 7f6d771e41..0b3f343991 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/Ia32/SecEntry.nasm
@@ -1,6 +1,6 @@
;--
;-; Copyright (c) 2019, Intel Corporation. All rights reserved.+; Copyright
(c) 2019 - 2024, Intel Corporation. All rights reserved. ;
SPDX-License-Identifier: BSD-2-Clause-Patent ; Module Name: ;@@ -13,7 +13,7 @@
;
;--
-#include "Fsp.h"+#include SECTION .text diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 2e0d67eae4..6806e000ce 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Librar
Re: [edk2-devel][edk2-platforms][PATCH v3] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
Hi Ted,
I see good improvements on V3. Thanks!
Few comments/feedback:
1. Minor feedback - The module name choice SecFspWrapperPlatformSecLibFspO.inf
is assuming FSP owning reset vector will be part of FSP-O. it's an
implementation choice. Perhaps consider the name to be
SecFspWrapperPlatformSecLibResetVectorInFsp or
SecFspWrapperPlatformSecLibFor64Bit (to be more relevant to the purpose of the
file).
2. I see TSC values are pushed into stack. However, I am not seeing a rdtsc
instruction to read the TSC value. Can you clarify how are we getting the TSC
values?
Thanks,
Sai
-Original Message-
From: Kuo, Ted
Sent: Friday, December 22, 2023 2:14 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel
; Desimone, Nathaniel L
; Dong, Eric ; S, Ashraf
Ali ; Duggapu, Chinni B ;
Gao, Liming
Subject: [edk2-devel][edk2-platforms][PATCH v3] MinPlatformPkg: Support
SecFspWrapperPlatformSecLib in X64
https://bugzilla.tianocore.org/show_bug.cgi?id=4623
1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
2.Made changes in common file to support both IA32 and X64.
3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP.
- PcdFspWrapperBfvforResetVectorInFsp
- PcdFsptUpdHeaderRevision
- PcdFsptArchUpdRevision
Cc: Sai Chaganty
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Eric Dong
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Liming Gao
Signed-off-by: Ted Kuo
---
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 +-
.../Ia32/SecEntry.nasm| 4 +-
.../SecFspWrapperPlatformSecLib.inf | 9 +-
.../SecFspWrapperPlatformSecLibFspO.inf | 101
.../SecGetPerformance.c | 11 +-
.../SecPlatformInformation.c | 8 +-
.../SecRamInitData.c | 73 --
.../X64/PeiCoreEntry.nasm | 218 ++
.../X64/SecEntry.nasm | 71 ++
.../X64/Stack.nasm| 72 ++
.../Ia32 => Include}/Fsp.h| 4 +-
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 15 ++
12 files changed, 579 insertions(+), 32 deletions(-) create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLibFspO.inf
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
rename
Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32
=> Include}/Fsp.h (86%)
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
index 7c0f605b92..cc36334227 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/FsptCoreUpd.h
@@ -1,6 +1,6 @@
/** @file -Copyright (c) 2017, Intel Corporation. All rights
reserved.+Copyright (c) 2017 - 2023, Intel Corporation. All rights
reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -10,6 +10,7
@@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1) +#if FixedPcdGet8 (PcdFsptArchUpdRevision) <= 1 /** Fsp T
Core UPD **/ typedef struct {@@ -34,6 +35,28 @@ typedef struct {
**/ UINT8 Reserved[16]; } FSPT_CORE_UPD;+#else+/** Fsp
T Core UPD+**/+typedef struct {++/** Offset 0x0040+**/+ EFI_PHYSICAL_ADDRESS
MicrocodeRegionBase;++/** Offset 0x0048+**/+ UINT64
MicrocodeRegionSize;++/** Offset 0x0050+**/+ EFI_PHYSICAL_ADDRESS
CodeRegionBase;++/** Offset 0x0058+**/+ UINT64
CodeRegionSize;+} FSPT_CORE_UPD;+#endif #pragma pack() diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 7f6d771e41..de44066a20 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/Ia32/SecEntry.nasm
@@ -1,6 +1,6 @@
;--
;-; Copyright (c) 2019, Intel Corporation. All rights reserved.+; Copyright
(c) 2019 - 2023, Intel Corporation. All rights reserved. ;
SPDX-License-Identifier: BSD-2-Clause-Patent ; Module Name: ;@@ -13,7 +13,7 @@
;
;--
-#include "Fsp.h"+#include SECTI
Re: [edk2-devel] [PATCH 1/1] Platform/Intel/Readme.md: Link to the OSS FSP repo
I do see the existing link gets redirected to the new link. Still a good change. Thanks! Reviewed-by: Sai Chaganty -Original Message- From: Pedro Falcato Sent: Wednesday, November 29, 2023 3:41 PM To: devel@edk2.groups.io Cc: Pedro Falcato ; Desimone, Nathaniel L ; Chaganty, Rangasai V Subject: [PATCH 1/1] Platform/Intel/Readme.md: Link to the OSS FSP repo Link to github.com/intel/FSP, which is the canonical OSS place for all your FSP needs. The old link is not accessible publicly. Signed-off-by: Pedro Falcato Cc: Nate DeSimone Cc: Sai Chaganty --- Platform/Intel/Readme.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index 112d0af1f6eb..d29a90729f1a 100644 --- a/Platform/Intel/Readme.md +++ b/Platform/Intel/Readme.md @@ -47,7 +47,7 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol || || | [EDK II](https://github.com/tianocore/edk2) | -| [Intel(r) FSP](https://github.com/IntelFsp/FSP) | +| [Intel(r) FSP](https://github.com/intel/FSP) | | [Minimum Platform (`MinPlatformPkg`)](https://github.com/tianocore/edk2-platforms/tree/master/Platform/Intel/MinPlatformPkg) | | [Board Support (\OpenBoardPkg)](https://github.com/tianocore/edk2-platforms/tree/master/Platform/Intel) | -- 2.43.0 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#111869): https://edk2.groups.io/g/devel/message/111869 Mute This Topic: https://groups.io/mt/102883723/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH v1] IpmiFeaturePkg: Fix Build
Reviewed-by: Sai Chaganty -Original Message- From: Desimone, Nathaniel L Sent: Wednesday, November 29, 2023 4:40 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Gao, Liming Subject: [edk2-platforms][PATCH v1] IpmiFeaturePkg: Fix Build Add missing MemoryAllocationLib dependency Cc: Sai Chaganty Cc: Liming Gao Signed-off-by: Nate DeSimone --- .../IpmiFeaturePkg/GenericElog/Smm/GenericElog.inf | 1 + 1 file changed, 1 insertion(+) diff --git a/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/GenericElog/Smm/GenericElog.inf b/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/GenericElog/Smm/GenericElog.inf index 00f4154cdd..ea1cf9d61b 100644 --- a/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/GenericElog/Smm/GenericElog.inf +++ b/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/GenericElog/Smm/GenericElog.inf @@ -28,6 +28,7 @@ UefiDriverEntryPoint DebugLib SmmServicesTableLib + MemoryAllocationLib [Protocols] gSmmGenericElogProtocolGuid # PROTOCOL ALWAYS_PRODUCED -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#111868): https://edk2.groups.io/g/devel/message/111868 Mute This Topic: https://groups.io/mt/102884732/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms PATCH] Maintainers.txt: remove Isaac Oram's email address
Reviewed-by: Sai Chaganty
-Original Message-
From: Laszlo Ersek
Sent: Wednesday, October 25, 2023 1:36 AM
To: edk2-devel-groups-io
Cc: Abdul Lateef Attar ; Abner Chang
; S, Ashraf Ali ; Chiu, Chasel
; Dong, Eric ; Gao, Liming
; Desimone, Nathaniel L
; Nickle Wang ; Pedro
Falcato ; Chaganty, Rangasai V
; Ni, Ray ; Theo Jehl
Subject: [edk2-platforms PATCH] Maintainers.txt: remove Isaac Oram's email
address
Email to Isaac's address bounces ("5.1.0 Address
rejected"); remove that address.
Cc: Abdul Lateef Attar
Cc: Abner Chang
Cc: Ashraf Ali S
Cc: Chasel Chiu
Cc: Eric Dong
Cc: Liming Gao
Cc: Nate DeSimone
Cc: Nickle Wang
Cc: Pedro Falcato
Cc: Rangasai V Chaganty
Cc: Ray Ni
Cc: Sai Chaganty
Cc: Theo Jehl
Signed-off-by: Laszlo Ersek
---
Maintainers.txt | 11 ---
1 file changed, 11 deletions(-)
diff --git a/Maintainers.txt b/Maintainers.txt index 3e72f53afa0d..affb2632e0db
100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -148,7 +148,6 @@ R: Marvin Häuser Features/Intel
F: Features/Intel/
M: Sai Chaganty
-M: Isaac Oram
M: Nate DeSimone
R: Liming Gao
@@ -159,7 +158,6 @@ R: Liming Gao
Features/Intel/OutOfBandManagement/IpmiFeaturePkg
F: Features/Intel/OutOfBandManagement/IpmiFeaturePkg
-M: Isaac Oram
M: Nate DeSimone
R: Liming Gao
@@ -171,14 +169,12 @@ R: Liming Gao
Features/ManageabilityPkg
F: Features/ManageabilityPkg/
M: Abner Chang
-M: Isaac Oram
R: Abdul Lateef Attar
R: Nickle Wang
Platform/Intel
F: Platform/Intel/
M: Sai Chaganty
-M: Isaac Oram
M: Nate DeSimone
Platform/Intel/QuarkPlatformPkg
@@ -196,7 +192,6 @@ R: Nate DeSimone
Platform/Intel/BoardModulePkg
F: Platform/Intel/BoardModulePkg/
M: Eric Dong
-M: Isaac Oram
R: Liming Gao
Platform/Intel/KabylakeOpenBoardPkg
@@ -216,7 +211,6 @@ Platform/Intel/MinPlatformPkg
F: Platform/Intel/MinPlatformPkg/
M: Chasel Chiu
M: Nate DeSimone
-M: Isaac Oram
R: Liming Gao
R: Eric Dong
@@ -253,7 +247,6 @@ R: Saloni Kasbekar
Platform/Intel/WhitleyOpenBoardPkg
F: Platform/Intel/WhitleyOpenBoardPkg/
-M: Isaac Oram
M: Nate DeSimone
M: Chasel Chiu
@@ -279,14 +272,12 @@ M: Daniel Schaefer Silicon/Intel
F: Silicon/Intel/
M: Rangasai V Chaganty
-M: Isaac Oram
M: Nate DeSimone
Silicon/Intel/IntelSiliconPkg
F: Silicon/Intel/IntelSiliconPkg/
M: Ray Ni
M: Rangasai V Chaganty
-M: Isaac Oram
R: Ashraf Ali S
Silicon/Intel/QuarkSocPkg
@@ -331,7 +322,6 @@ R: Saloni Kasbekar
Silicon/Intel/WhitleySiliconPkg
F: Silicon/Intel/WhitleySiliconPkg/
-M: Isaac Oram
M: Nate DeSimone
M: Chasel Chiu
@@ -377,7 +367,6 @@ R: Meenakshi Aggarwal
QEMU EDK II Minimum Platform Specification implementation
F: Platform/Qemu/QemuOpenBoardPkg/
-M: Isaac Oram
M: Pedro Falcato
R: Theo Jehl
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Re: [edk2-devel] [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Chuang, Rosen
Subject: [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and
SiPkg.dec
Adds the following modules:
- Product/Alderlake/Include
- Product/Alderlake/Library
- Product/Alderlake DSCs
- SiPkg.dec
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../Product/Alderlake/Include/Ppi/SiPolicy.h | 55 ++
.../Library/PeiSiPolicyLib/PeiSiPolicyLib.c | 47 ++
.../Library/PeiSiPolicyLib/PeiSiPolicyLib.inf | 47 ++
.../PeiSiPolicyLib/PeiSiPolicyLibPreMem.c | 47 ++
.../PeiSiPolicyLib/PeiSiPolicyLibrary.h | 21 +
.../Product/Alderlake/SiPkgBuildOption.dsc| 122
.../Product/Alderlake/SiPkgCommonLib.dsc | 36 +
.../Product/Alderlake/SiPkgDxe.dsc| 32 +
.../Product/Alderlake/SiPkgDxeLib.dsc | 23 +
.../Product/Alderlake/SiPkgPeiLib.dsc | 19 +
Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec | 625 ++
11 files changed, 1074 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
new file mode 100644
index 00..703f0221bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/Si
+++ Policy.h
@@ -0,0 +1,55 @@
+/** @file
+ Silicon Policy PPI is used for specifying platform
+ related Intel silicon information and policy setting.
+ This PPI is consumed by the silicon PEI modules and carried
+ over to silicon DXE modules.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _SI_POLICY_PPI_H_
+#define _SI_POLICY_PPI_H_
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#ifndef DISABLED
+#define DISABLED 0
+#endif
+#ifndef ENABLED
+#define ENABLED 1
+#endif
+
+extern EFI_GUID gSiPreMemPolicyPpiGuid; extern EFI_GUID
+gSiPolicyPpiGuid;
+
+
+#include
+
+
+#include
+#include
+extern EFI_GUID gCpuPciePeiPreMemConfigGuid; extern EFI_GUID
+gCpuPcieRpConfigGuid;
+
+#include
+extern EFI_GUID gMemoryConfigGuid;
+extern EFI_GUID gMemoryConfigNoCrcGuid;
+
+#include
+extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
+
+#include
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid; extern EFI_GUID
+gHostBridgePeiConfigGuid;
+
+typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI; typedef
+struct _SI_POLICY_STRUCT SI_POLICY_PPI;
+
+#endif // _SI_POLICY_PPI_H_
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
new file mode 100644
index 00..886415bdaa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLib.c
@@ -0,0 +1,47 @@
+/** @file
+ This file is PeiSiPolicyLib library creates default settings of RC
+ Policy and installs RC Policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+"PeiSiPolicyLibrary.h"
+#include
+#include
+
+
+/**
+ SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So
+please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESSThe policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPpiDesc;
+
+ SiPolicyRe
Re: [edk2-devel] [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules
Reviewed-by: Sai Chaganty -Original Message- From: Kasbekar, Saloni Sent: Thursday, September 14, 2023 9:46 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules Adds the following modules: - AdlPch/Include - AdlPch/IncludePrivate - AdlPch/Library - AdlPch DSCs - IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Fru/AdlPch/CommonLib.dsc | 29 ++ .../AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc| 10 + .../AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc | 7 + .../Fru/AdlPch/Include/PchBdfAssignment.h | 81 + .../Fru/AdlPch/Include/PchLimits.h| 47 +++ .../Fru/AdlPch/Include/PchPcieRpInfo.h| 17 ++ .../Fru/AdlPch/Include/PchReservedResources.h | 13 + .../AdlPch/Include/PchReservedResourcesAdpP.h | 36 +++ .../IncludePrivate/Register/PchPcrRegs.h | 59 .../IncludePrivate/Register/PchRegsLpcAdl.h | 30 ++ .../PeiDxeSmmPchInfoLib/PchInfoLibAdl.c | 223 ++ .../PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h | 44 +++ .../PeiDxeSmmPchInfoLibAdl.inf| 37 +++ .../AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc| 7 + .../AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc | 12 + .../IncludePrivate/RegisterAccess.h | 288 ++ 16 files changed, 940 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc new file mode 100644 index 00..3f508f83a1 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc @@ -0,0 +1,29 @@ +## @file +# Component description file for the AlderLake PCH Common FRU libraries. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + + PchPcrLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL + ib/PeiDxeSmmPchPcrLib.inf + PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/Pei + DxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf + + P2SbSidebandAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPriva + te/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf + + + EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/P + eiDxeSmmEspiLib.inf + + + + PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiD + xeSmmPmcLib.inf + PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxe + SmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf + + SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpi + CommonLib/BaseSpiCommonLib.inf + GpioLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/P + eiDxeSmmGpioLib.inf + PchDmiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeS + mmPchDmiLib/PeiDxeSmmPchDmiLib.inf + + + GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiD + xeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf + + PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/PeiDxeSmmPc + hPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf + + + # + # Common FRU Libraries + # + + PchInfoLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Library/PeiDxeSmmPchInfoL + ib/PeiDxeSmmPchInfoLibAdl.inf + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc b/Silicon/Intel
Re: [edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Chuang, Rosen
Subject: [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register,
Other Includes
Adds the following Includes:
- Include/
- Include/Protocol
- Include/Register
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../AlderlakeSiliconPkg/Include/ConfigBlock.h | 53 +++
.../AlderlakeSiliconPkg/Include/CpuPcieHob.h | 48 +++
.../Include/Protocol/IgdOpRegion.h| 22 ++
.../Include/Protocol/Spi.h| 346 ++
.../Include/Protocol/Wdt.h| 111 ++
.../Include/Register/FlashRegs.h | 73
.../Include/Register/GpioRegs.h | 103 ++
.../Include/Register/GpioRegsVer2.h | 211 +++
.../Include/Register/PchDmi14Regs.h | 49 +++
.../Include/Register/PchDmiRegs.h | 51 +++
.../Include/Register/PchPcieRpRegs.h | 45 +++
.../Include/Register/PchRegsLpc.h | 77
.../Include/Register/PmcRegs.h| 134 +++
.../Include/Register/RtcRegs.h| 44 +++
.../Include/Register/TcoRegs.h| 71
.../Include/SerialIoDevices.h | 226
.../AlderlakeSiliconPkg/Include/SiConfigHob.h | 17 +
.../Include/SiPolicyStruct.h | 64
18 files changed, 1745 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 00..2e609bc8d9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include
+#include
+#include
+#include
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+ EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID
extension HOB header
+ UINT8 Revision; ///< Offset 24Revision
of this config block
+ UINT8 Attributes; ///< Offset 25The main
revision for config block
+ UINT8 Reserved[2]; ///< Offset 26-27 Reserved
for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+///
+typedef struct _CONFIG_BLOCK {
+ CONFIG_BLOCK_HEADERHeader; ///< Offset 0-27 Header of
config block
+ //
+ // Config Block Data
+ //
+} CONFIG_BLOCK;
+
+///
+/// Config Block Table Header
+///
+typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
+ CONFIG_BLOCK_HEADERHeader; ///< Offset 0-27 GUID
number for main entry of config block
+ UINT8 Rsvd0[2];///< Offset 28-29 Reserved
for future use
+ UINT16 NumberOfBlocks; ///< Offset 30-31 Number of
config blocks (N)
+ UINT32 AvailableSize; ///< Offset 32-35 Current
config block table size
+///
+/// Individual Config Block Structures are added here in memory as part of
AddConfigBlock()
+///
+
Re: [edk2-devel] [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Chuang, Rosen
Subject: [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru
Adds the following modules:
- AdlCpu/CpuPcieRp
- AdlCpu/Include
- AdlCpu/IncludePrivate
- AdlCpu/LibraryPrivate
- AdlCpu/PeiReportCpuHob
- AdlCpu DSCs
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../Fru/AdlCpu/CommonLib.dsc | 9 +
.../CpuPcieInfoFruLib.c | 87 ++
.../PeiDxeSmmCpuPcieInfoFruLib.inf| 39 +
.../AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc | 8 +
.../Fru/AdlCpu/Include/CpuGenInfo.h | 42 +
.../Include/Library/CpuPcieInfoFruLib.h | 45 +
.../Include/Register/SaRegsHostBridge.h | 64 +++
.../AdlCpu/IncludePrivate/CpuGenInfoFruLib.h | 44 +
.../AdlCpu/IncludePrivate/Register/IgdRegs.h | 34
.../BaseCpuInfoFruLib/BaseCpuInfoFruLib.c | 164 ++
.../BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf | 29
.../PeiReportCpuHobLib/PeiReportCpuHobLib.c | 22 +++
.../PeiReportCpuHobLib/PeiReportCpuHobLib.inf | 26 +++
13 files changed, 613 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
new file mode 100644
index 00..35a3cce916
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
@@ -0,0 +1,9 @@
+## @file
+# Component description file for the AlderLake CPU Common FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+CpuPcieInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/CpuPcieRp/Library/P
+CpuPcieInfoFruLib|eiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.
+CpuPcieInfoFruLib|inf
+CpuInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/LibraryPrivate/BaseCpuI
+CpuInfoFruLib|nfoFruLib/BaseCpuInfoFruLib.inf
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
new file mode 100644
index 00..277b73fe67
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/Pei
+++ DxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
@@ -0,0 +1,87 @@
+/** @file
+ CPU PCIe information library.
+
+ All function in this library is available for PEI, DXE, and SMM, But
+ do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+ #include #include
+ #include #include
+ #include
+#include #include
+
+/**
+ Get Maximum CPU Pcie Root Port Number
+
+ @retval Maximum CPU Pcie Root Port Number **/
+UINT8
+GetMaxCpuPciePortNum (
+ VOID
+ )
+{
+ switch (GetCpuSku ()) {
+case EnumCpuUlt:
+ return CPU_PCIE_ULT_MAX_ROOT_PORT;
+case EnumCpuUlx:
+ return CPU_PCIE_ULX_MAX_ROOT_PORT;
+default:
+ return CPU_PCIE_ULT_MAX_ROOT_PORT;
+ }
+}
+
+/**
+ Get CPU Pcie Root Port Device and Function Number by Root Port
+physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device
number
Re: [edk2-devel] [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes
Reviewed-by: Sai Chaganty -Original Message- From: Kasbekar, Saloni Sent: Thursday, September 14, 2023 9:46 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes Adds the following Includes: - Include/Library - Include/Pins - Include/Ppi Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Include/Library/ConfigBlockLib.h | 64 +++ .../Include/Library/EspiLib.h | 34 ++ .../Include/Library/GpioConfig.h | 372 ++ .../Include/Library/GpioLib.h | 174 .../Include/Library/GpioNativeLib.h | 135 +++ .../Include/Library/GraphicsInfoLib.h | 46 +++ .../Include/Library/MmPciLib.h| 27 ++ .../Include/Library/PchPcieRpLib.h| 41 ++ .../Include/Library/PchPcrLib.h | 221 +++ .../Library/PeiDxeSmmReserveMmio64SizeLib.h | 21 + .../Include/Library/PeiSiPolicyUpdateLib.h| 154 .../Include/Library/PmcLib.h | 40 ++ .../Include/Library/ResetSystemLib.h | 68 .../Include/Library/SecPlatformLib.h | 81 .../Include/Library/SiConfigBlockLib.h| 56 +++ .../Include/Library/SiPolicyLib.h | 39 ++ .../Include/Library/SpiLib.h | 21 + .../Include/Pins/GpioPinsVer2Lp.h | 36 ++ .../Include/Ppi/FspmArchConfigPpi.h | 32 ++ .../Include/Ppi/PeiPreMemSiDefaultPolicy.h| 33 ++ .../Include/Ppi/PeiSiDefaultPolicy.h | 33 ++ .../AlderlakeSiliconPkg/Include/Ppi/Spi.h | 29 ++ .../AlderlakeSiliconPkg/Include/Ppi/Wdt.h | 22 ++ 23 files changed, 1779 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h new file mode 100644 index 00..d9966c76e9 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h @@ -0,0 +1,64 @@ +/** @file + Header file for Config Block Lib implementation + + Copyright (c) 2022, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CONFIG_BLOCK_LIB_H_ +#define _CONFIG_BLOCK_LIB_H_ + +/** + Create config block table + + @param[in] TotalSize- Max size to be allocated for the Config Block Table + @param[out]ConfigBlockTableAddress - On return, points to a pointer to the beginning of Config Block Table Address + + @retval EFI_INVALID_PARAMETER - Invalid Parameter + @retval EFI_OUT_OF_RESOURCES - Out of resources + @retval EFI_SUCCESS - Successfully created Config Block Table at ConfigBlockTableAddress +**/ +EFI_STATUS +EFIAPI +CreateConfigBlockTable ( + IN UINT16TotalSize, + OUTVOID **ConfigBlockTableAddress
Re: [edk2-devel] [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Chuang, Rosen
Subject: [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components
Adds the following modules:
- IpBlock/Pmc/IncludePrivate
- IpBlock/Pmc/Library
- IpBlock/Pmc/LibraryPrivate
- IpBlock/Spi/IncludePrivate
- IpBlock/Spi/Library
- IpBlock/Spi/LibraryPrivate
- IpBlock/Spi/Smm
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../IncludePrivate/Library/PmcPrivateLib.h| 47 +
.../IpBlock/Pmc/IncludePrivate/PmcSocConfig.h | 67 +
.../PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 38 +
.../Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c | 50 +
.../PeiDxeSmmPmcPrivateLib.inf| 43 +
.../PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c| 86 ++
.../Spi/IncludePrivate/Library/SpiCommonLib.h | 376 ++
.../Spi/IncludePrivate/Register/SpiRegs.h | 116 ++
.../IpBlock/Spi/Library/PeiSpiLib/PchSpi.c| 209 +++
.../Spi/Library/PeiSpiLib/PeiSpiLib.inf | 41 +
.../BaseSpiCommonLib/BaseSpiCommonLib.inf | 29 +
.../BaseSpiCommonLib/SpiCommon.c | 1127 +
.../AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c | 387 ++
.../IpBlock/Spi/Smm/SpiSmm.inf| 46 +
14 files changed, 2662 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
new file mode 100644
index 00..6ec244b127
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
@@ -0,0 +1,47 @@
+/** @file
+ Header file for private PmcLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_PRIVATE_LIB_H_
+#define _PMC_PRIVATE_LIB_H_
+
+#include
+#include "Register/PmcRegs.h"
+
+typedef enum {
+ PmcSwSmiRate1p5ms = 0,
+ PmcSwSmiRate16ms,
+ PmcSwSmiRate32ms,
+ PmcSwSmiRate64ms
+} PMC_SWSMI_RATE;
+
+/**
+ This function sets SW SMI Rate.
+
+ @param[in] SwSmiRateRefer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+ IN PMC_SWSMI_RATE SwSmiRate
+ );
+
+typedef enum {
+ PmcPeriodicSmiRate8s = 0,
+ PmcPeriodicSmiRate16s,
+ PmcPeriodicSmiRate32s,
+ PmcPeriodicSmiRate64s
+} PMC_PERIODIC_SMI_RATE;
+
+/**
+ This function sets Periodic SMI Rate.
+
+ @param[in] PeriodicSmiRateRefer to PMC_PERIODIC_SMI_RATE for
possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+ IN PMC_PERIODIC_SMI_RATEPeriodicSmiRate
+ );
+
+#endif // _PMC_PRIVATE_LIB_H_
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
new file mode 100644
index 00..523a84a180
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
@@ -0,0 +1,67 @@
+/** @file
+ PMC SoC configuration
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PMC_SOC_CONFIGURATION_H_
+#define _PMC_SOC_CONFIGURATION_H_
+
+typedef enum {
+ AdrSinglePhase = 0,
+ AdrDualPhase
+} ADR_PHASE_TYPE;
+
+typedef enum {
+ AdrGpioB = 0,
+ AdrGpioC
+
Re: [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components
Reviewed-by: Sai Chaganty -Original Message- From: Kasbekar, Saloni Sent: Thursday, September 14, 2023 9:46 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Adds the following modules: - IpBlock/CpuPcieRp/Include - IpBlock/Espi/Library - IpBlock/Gpio/IncludePrivate - IpBlock/Gpio/Library - IpBlock/Gpio/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../IpBlock/CpuPcieRp/Include/CpuPcieInfo.h | 25 + .../Espi/Library/PeiDxeSmmEspiLib/EspiLib.c | 58 ++ .../PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf | 38 ++ .../IncludePrivate/Library/GpioHelpersLib.h | 50 ++ .../IncludePrivate/Library/GpioNativePads.h | 245 .../IncludePrivate/Library/GpioPrivateLib.h | 350 +++ .../Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c | 546 ++ .../Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c | 522 + .../Library/PeiDxeSmmGpioLib/GpioLibrary.h| 29 + .../Library/PeiDxeSmmGpioLib/GpioNativeLib.c | 177 ++ .../PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf | 44 ++ .../BaseGpioHelpersLibNull.c | 51 ++ .../BaseGpioHelpersLibNull.inf| 25 + .../GpioNativePrivateLibInternal.h| 48 ++ .../PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c | 267 + .../GpioPrivateLibPch.c | 172 ++ .../GpioPrivateLibVer2.c | 81 +++ .../PeiDxeSmmGpioPrivateLibVer2.inf | 40 ++ .../PeiGpioHelpersLib/PeiGpioHelpersLib.c | 218 +++ .../PeiGpioHelpersLib/PeiGpioHelpersLib.inf | 46 ++ 20 files changed, 3032 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h new file mode 100644 index 00..a6f8b16d10 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h @@ -0,0 +1,25 @@ +/** @file + This file contains definitions of PCIe controller information + + Copyright (c) 2022, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CPU_PCIE_INFO_H_ +#define _CPU_PCIE_INFO_H_ + +#define PCIE_HWEQ_COEFFS_MAX5 + + +// +// SA PCI Express* Port configuration +// + +#define CPU_PCIE_MAX_ROOT_PORTS4 +#define CPU_PCIE_MAX_CONTROLLERS 3 + +#define SA_PEG_MAX_FUN 0x04 +#define SA_PEG_MAX_LANE 0x14
Re: [edk2-devel] [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Chuang, Rosen
Subject: [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi
components
Adds the following modules:
- IpBlock/P2sb/IncludePrivate
- IpBlock/P2sb/Library
- IpBlock/P2sb/LibraryPrivate
- IpBlock/PchDmi/IncludePrivate
- IpBlock/PchDmi/LibraryPrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../Library/P2SbSidebandAccessLib.h | 105 +++
.../IncludePrivate/Library/PchSbiAccessLib.h | 58
.../P2sb/IncludePrivate/P2SbController.h | 32 +++
.../P2sb/IncludePrivate/Register/P2sbRegs.h | 53
.../Library/PeiDxeSmmPchPcrLib/PchPcrLib.c| 266 ++
.../PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf | 35 +++
.../PeiDxeSmmP2SbSidebandAccessLib.c | 208 ++
.../PeiDxeSmmP2SbSidebandAccessLib.inf| 30 ++
.../PchSbiAccessLib.c | 72 +
.../PeiDxeSmmPchSbiAccessLib.inf | 35 +++
.../PchDmi/IncludePrivate/Library/PchDmiLib.h | 60
.../PeiDxeSmmPchDmiLib/PchDmi14.c | 34 +++
.../PeiDxeSmmPchDmiLib/PchDmi14.h | 22 ++
.../PeiDxeSmmPchDmiLib/PchDmiLib.c| 110
.../PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf | 43 +++
15 files changed, 1163 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
new file mode 100644
index 00..e364508eb4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Libr
+++ ary/P2SbSidebandAccessLib.h
@@ -0,0 +1,105 @@
+/** @file
+ Header for P2SbSidebandAccessLib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_
+#define _P2SB_SIDEBAND_ACCESS_LIB_H_
+
+#include
+#include
+#include // For PCH_SBI_PID definition
+
+typedef PCH_SBI_PID P2SB_PID;
+
+typedef enum {
+ P2SbMemory = 0,
+ P2SbPciConfig,
+ P2SbPrivateConfig
+} P2SB_REGISTER_SPACE;
+
+typedef enum {
+ MemoryRead = 0x0,
+ MemoryWrite= 0x1,
+ PciConfigRead = 0x4,
+ PciConfigWrite = 0x5,
+ PrivateControlRead = 0x6,
+ PrivateControlWrite= 0x7,
+ GpioLockUnlock = 0x13
+} P2SB_SBI_OPCODE;
+
+typedef enum {
+ SBI_SUCCESSFUL = 0,
+ SBI_UNSUCCESSFUL= 1,
+ SBI_POWERDOWN = 2,
+ SBI_MIXED = 3,
+ SBI_INVALID_RESPONSE
+} P2SB_SBI_RESPONSE;
+
+typedef enum {
+ P2SbMmioAccess = 0,
+ P2SbMsgAccess
+} P2SB_SIDEBAND_ACCESS_METHOD;
+
+/**
+ REGISTER_ACCESS for P2SB device to support access to sideband registers.
+ Be sure to keep first member of this structure as REGISTER_ACCESS to
+allow
+ for correct casting between caller who sees this structure as
+REGISTER_ACCESS
+ and calle who will cast
Re: [edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Chuang, Rosen
Subject: [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics,
HostBridge, PcieRp components
Adds the following modules:
- IpBlock/Graphics/Include
- IpBlock/Graphics/IncludePrivate
- IpBlock/Graphics/Library
- IpBlock/Graphics/LibraryPrivate
- IpBlock/HostBridge/IncludePrivate
- IpBlock/PcieRp/Library
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../Include/Ppi/GraphicsPlatformPolicyPpi.h | 76 +++
.../Library/DxeGraphicsPolicyLib.h| 71 +++
.../Library/DxeIgdOpRegionInitLib.h | 115 +
.../GraphicsInfoLibVer1.c | 52
.../GraphicsInfoLibVer1.inf | 33 +
.../DxeGraphicsPolicyLib.c| 116 +
.../DxeGraphicsPolicyLib.inf | 36 ++
.../DxeIgdOpRegionInit.c | 119 ++
.../DxeIgdOpRegionInitLib.inf | 47 +++
.../IncludePrivate/HostBridgeDataHob.h| 25
.../PchPcieRpLibInternal.h| 20 +++
.../PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c | 71 +++
.../PeiDxeSmmPchPcieRpLibVer2.inf | 37 ++
13 files changed, 818 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
new file mode 100644
index 00..a8f67061a5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/Gra
+++ phicsPlatformPolicyPpi.h
@@ -0,0 +1,76 @@
+/** @file
+ The PEI_GRAPHICS_PLATFORM_POLICY_PPI provides platform information to PEI
Graphics PEIM.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+#define _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+
+/**
+ Globally unique identifier for PEI platform policy PPI.
+**/
+#define PEI_GRAPHICS_PLATFORM_POLICY_PPI_GUID \ { \
+ 0x4eabcd09, 0x43d3, 0x4b4d, { 0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89,
+0x99, 0x5 } \ }
+
+#define PEI_GRAPHICS_PLATFORM_POLICY_REVISION 1
+
+/**
+Pre-declaration of PEI graphics platform policy PPI.
+**/
+typedef struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI
+PEI_GRAPHICS_PLATFORM_POLICY_PPI;
+
+/**
+ Enum defining the different lid status values **/ typedef enum {
+ LidClosed,
+ LidOpen,
+ LidStatusMax
+} LID_STATUS;
+
+/**
+ This function gets the platform lid status for LFP displays.
+
+ @param[out] CurrentLidStatus Output variable to store the lid status.
+
+ @retval EFI_SUCCESS Correct lid status is returned.
+ @retval EFI_UNSUPPORTED Platform does not support lid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+ OUT LID_STATUS *CurrentLidStatus
+ );
+
+/**
+ This function gets the base address of loaded VBT.
+
+ @param[out] VbtAddressStarting address of the VBT is returned in this
parameter.
+ @param[out] VbtSize Size of the VBT is returned in this parameter
Re: [edk2-devel] [PATCH 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Chuang, Rosen
Subject: [PATCH 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec
Adds the following modules:
- Product/Alderlake/Include
- Product/Alderlake/Library
- Product/Alderlake DSCs
- SiPkg.dec
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../Product/Alderlake/Include/Ppi/SiPolicy.h | 55 ++
.../Library/PeiSiPolicyLib/PeiSiPolicyLib.c | 47 ++
.../Library/PeiSiPolicyLib/PeiSiPolicyLib.inf | 47 ++
.../PeiSiPolicyLib/PeiSiPolicyLibPreMem.c | 47 ++
.../PeiSiPolicyLib/PeiSiPolicyLibrary.h | 21 +
.../Product/Alderlake/SiPkgBuildOption.dsc| 122
.../Product/Alderlake/SiPkgCommonLib.dsc | 36 +
.../Product/Alderlake/SiPkgDxe.dsc| 32 +
.../Product/Alderlake/SiPkgDxeLib.dsc | 23 +
.../Product/Alderlake/SiPkgPeiLib.dsc | 19 +
Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec | 625 ++
11 files changed, 1074 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
new file mode 100644
index 00..703f0221bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/Si
+++ Policy.h
@@ -0,0 +1,55 @@
+/** @file
+ Silicon Policy PPI is used for specifying platform
+ related Intel silicon information and policy setting.
+ This PPI is consumed by the silicon PEI modules and carried
+ over to silicon DXE modules.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _SI_POLICY_PPI_H_
+#define _SI_POLICY_PPI_H_
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#ifndef DISABLED
+#define DISABLED 0
+#endif
+#ifndef ENABLED
+#define ENABLED 1
+#endif
+
+extern EFI_GUID gSiPreMemPolicyPpiGuid; extern EFI_GUID
+gSiPolicyPpiGuid;
+
+
+#include
+
+
+#include
+#include
+extern EFI_GUID gCpuPciePeiPreMemConfigGuid; extern EFI_GUID
+gCpuPcieRpConfigGuid;
+
+#include
+extern EFI_GUID gMemoryConfigGuid;
+extern EFI_GUID gMemoryConfigNoCrcGuid;
+
+#include
+extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
+
+#include
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid; extern EFI_GUID
+gHostBridgePeiConfigGuid;
+
+typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI; typedef
+struct _SI_POLICY_STRUCT SI_POLICY_PPI;
+
+#endif // _SI_POLICY_PPI_H_
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
new file mode 100644
index 00..886415bdaa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLib.c
@@ -0,0 +1,47 @@
+/** @file
+ This file is PeiSiPolicyLib library creates default settings of RC
+ Policy and installs RC Policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+"PeiSiPolicyLibrary.h"
+#include
+#include
+
+
+/**
+ SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So
+please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESSThe policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPpiDesc;
+
+ SiPolicyRe
Re: [edk2-devel] [PATCH 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules
Reviewed-by: Sai Chaganty -Original Message- From: Kasbekar, Saloni Sent: Wednesday, September 13, 2023 3:14 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules Adds the following modules: - AdlPch/Include - AdlPch/IncludePrivate - AdlPch/Library - AdlPch DSCs - IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Fru/AdlPch/CommonLib.dsc | 29 ++ .../AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc| 10 + .../AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc | 7 + .../Fru/AdlPch/Include/PchBdfAssignment.h | 81 + .../Fru/AdlPch/Include/PchLimits.h| 47 +++ .../Fru/AdlPch/Include/PchPcieRpInfo.h| 17 ++ .../Fru/AdlPch/Include/PchReservedResources.h | 13 + .../AdlPch/Include/PchReservedResourcesAdpP.h | 36 +++ .../IncludePrivate/Register/PchPcrRegs.h | 59 .../IncludePrivate/Register/PchRegsLpcAdl.h | 30 ++ .../PeiDxeSmmPchInfoLib/PchInfoLibAdl.c | 223 ++ .../PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h | 44 +++ .../PeiDxeSmmPchInfoLibAdl.inf| 37 +++ .../AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc| 7 + .../AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc | 12 + .../IncludePrivate/RegisterAccess.h | 288 ++ 16 files changed, 940 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc new file mode 100644 index 00..3f508f83a1 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc @@ -0,0 +1,29 @@ +## @file +# Component description file for the AlderLake PCH Common FRU libraries. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + + PchPcrLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL + ib/PeiDxeSmmPchPcrLib.inf + PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/Pei + DxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf + + P2SbSidebandAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPriva + te/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf + + + EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/P + eiDxeSmmEspiLib.inf + + + + PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiD + xeSmmPmcLib.inf + PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxe + SmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf + + SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpi + CommonLib/BaseSpiCommonLib.inf + GpioLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/P + eiDxeSmmGpioLib.inf + PchDmiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeS + mmPchDmiLib/PeiDxeSmmPchDmiLib.inf + + + GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiD + xeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf + + PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/PeiDxeSmmPc + hPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf + + + # + # Common FRU Libraries + # + + PchInfoLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Library/PeiDxeSmmPchInfoL + ib/PeiDxeSmmPchInfoLibAdl.inf + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc b/Silicon/Intel
Re: [edk2-devel] [PATCH 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Chuang, Rosen
Subject: [PATCH 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register,
Other Includes
Adds the following Includes:
- Include/
- Include/Protocol
- Include/Register
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../AlderlakeSiliconPkg/Include/ConfigBlock.h | 53 +++
.../AlderlakeSiliconPkg/Include/CpuPcieHob.h | 48 +++
.../Include/Protocol/IgdOpRegion.h| 22 ++
.../Include/Protocol/Spi.h| 346 ++
.../Include/Protocol/Wdt.h| 111 ++
.../Include/Register/FlashRegs.h | 73
.../Include/Register/GpioRegs.h | 103 ++
.../Include/Register/GpioRegsVer2.h | 211 +++
.../Include/Register/PchDmi14Regs.h | 49 +++
.../Include/Register/PchDmiRegs.h | 51 +++
.../Include/Register/PchPcieRpRegs.h | 45 +++
.../Include/Register/PchRegsLpc.h | 77
.../Include/Register/PmcRegs.h| 134 +++
.../Include/Register/RtcRegs.h| 44 +++
.../Include/Register/TcoRegs.h| 71
.../Include/SerialIoDevices.h | 226
.../AlderlakeSiliconPkg/Include/SiConfigHob.h | 17 +
.../Include/SiPolicyStruct.h | 64
18 files changed, 1745 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 00..2e609bc8d9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include
+#include
+#include
+#include
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+ EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID
extension HOB header
+ UINT8 Revision; ///< Offset 24Revision
of this config block
+ UINT8 Attributes; ///< Offset 25The main
revision for config block
+ UINT8 Reserved[2]; ///< Offset 26-27 Reserved
for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+///
+typedef struct _CONFIG_BLOCK {
+ CONFIG_BLOCK_HEADERHeader; ///< Offset 0-27 Header of
config block
+ //
+ // Config Block Data
+ //
+} CONFIG_BLOCK;
+
+///
+/// Config Block Table Header
+///
+typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
+ CONFIG_BLOCK_HEADERHeader; ///< Offset 0-27 GUID
number for main entry of config block
+ UINT8 Rsvd0[2];///< Offset 28-29 Reserved
for future use
+ UINT16 NumberOfBlocks; ///< Offset 30-31 Number of
config blocks (N)
+ UINT32 AvailableSize; ///< Offset 32-35 Current
config block table size
+///
+/// Individual Config Block Structures are added here in memory as part of
AddConfigBlock()
+///
+
Re: [edk2-devel] [PATCH 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes
Reviewed-by: Sai Chaganty -Original Message- From: Kasbekar, Saloni Sent: Wednesday, September 13, 2023 3:14 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes Adds the following Includes: - Include/Library - Include/Pins - Include/Ppi Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Include/Library/ConfigBlockLib.h | 64 +++ .../Include/Library/EspiLib.h | 34 ++ .../Include/Library/GpioConfig.h | 372 ++ .../Include/Library/GpioLib.h | 174 .../Include/Library/GpioNativeLib.h | 135 +++ .../Include/Library/GraphicsInfoLib.h | 46 +++ .../Include/Library/MmPciLib.h| 27 ++ .../Include/Library/PchPcieRpLib.h| 41 ++ .../Include/Library/PchPcrLib.h | 221 +++ .../Library/PeiDxeSmmReserveMmio64SizeLib.h | 21 + .../Include/Library/PeiSiPolicyUpdateLib.h| 154 .../Include/Library/PmcLib.h | 40 ++ .../Include/Library/ResetSystemLib.h | 68 .../Include/Library/SecPlatformLib.h | 81 .../Include/Library/SiConfigBlockLib.h| 56 +++ .../Include/Library/SiPolicyLib.h | 39 ++ .../Include/Library/SpiLib.h | 21 + .../Include/Pins/GpioPinsVer2Lp.h | 36 ++ .../Include/Ppi/FspmArchConfigPpi.h | 32 ++ .../Include/Ppi/PeiPreMemSiDefaultPolicy.h| 33 ++ .../Include/Ppi/PeiSiDefaultPolicy.h | 33 ++ .../AlderlakeSiliconPkg/Include/Ppi/Spi.h | 29 ++ .../AlderlakeSiliconPkg/Include/Ppi/Wdt.h | 22 ++ 23 files changed, 1779 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h new file mode 100644 index 00..d9966c76e9 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h @@ -0,0 +1,64 @@ +/** @file + Header file for Config Block Lib implementation + + Copyright (c) 2022, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CONFIG_BLOCK_LIB_H_ +#define _CONFIG_BLOCK_LIB_H_ + +/** + Create config block table + + @param[in] TotalSize- Max size to be allocated for the Config Block Table + @param[out]ConfigBlockTableAddress - On return, points to a pointer to the beginning of Config Block Table Address + + @retval EFI_INVALID_PARAMETER - Invalid Parameter + @retval EFI_OUT_OF_RESOURCES - Out of resources + @retval EFI_SUCCESS - Successfully created Config Block Table at ConfigBlockTableAddress +**/ +EFI_STATUS +EFIAPI +CreateConfigBlockTable ( + IN UINT16TotalSize, + OUTVOID **ConfigBlockTableAddress
Re: [edk2-devel] [PATCH 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Chuang, Rosen
Subject: [PATCH 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components
Adds the following modules:
- IpBlock/Pmc/IncludePrivate
- IpBlock/Pmc/Library
- IpBlock/Pmc/LibraryPrivate
- IpBlock/Spi/IncludePrivate
- IpBlock/Spi/Library
- IpBlock/Spi/LibraryPrivate
- IpBlock/Spi/Smm
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../IncludePrivate/Library/PmcPrivateLib.h| 47 +
.../IpBlock/Pmc/IncludePrivate/PmcSocConfig.h | 67 +
.../PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 38 +
.../Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c | 50 +
.../PeiDxeSmmPmcPrivateLib.inf| 43 +
.../PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c| 86 ++
.../Spi/IncludePrivate/Library/SpiCommonLib.h | 376 ++
.../Spi/IncludePrivate/Register/SpiRegs.h | 116 ++
.../IpBlock/Spi/Library/PeiSpiLib/PchSpi.c| 209 +++
.../Spi/Library/PeiSpiLib/PeiSpiLib.inf | 41 +
.../BaseSpiCommonLib/BaseSpiCommonLib.inf | 29 +
.../BaseSpiCommonLib/SpiCommon.c | 1127 +
.../AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c | 387 ++
.../IpBlock/Spi/Smm/SpiSmm.inf| 46 +
14 files changed, 2662 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
new file mode 100644
index 00..6ec244b127
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
@@ -0,0 +1,47 @@
+/** @file
+ Header file for private PmcLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_PRIVATE_LIB_H_
+#define _PMC_PRIVATE_LIB_H_
+
+#include
+#include "Register/PmcRegs.h"
+
+typedef enum {
+ PmcSwSmiRate1p5ms = 0,
+ PmcSwSmiRate16ms,
+ PmcSwSmiRate32ms,
+ PmcSwSmiRate64ms
+} PMC_SWSMI_RATE;
+
+/**
+ This function sets SW SMI Rate.
+
+ @param[in] SwSmiRateRefer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+ IN PMC_SWSMI_RATE SwSmiRate
+ );
+
+typedef enum {
+ PmcPeriodicSmiRate8s = 0,
+ PmcPeriodicSmiRate16s,
+ PmcPeriodicSmiRate32s,
+ PmcPeriodicSmiRate64s
+} PMC_PERIODIC_SMI_RATE;
+
+/**
+ This function sets Periodic SMI Rate.
+
+ @param[in] PeriodicSmiRateRefer to PMC_PERIODIC_SMI_RATE for
possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+ IN PMC_PERIODIC_SMI_RATEPeriodicSmiRate
+ );
+
+#endif // _PMC_PRIVATE_LIB_H_
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
new file mode 100644
index 00..523a84a180
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
@@ -0,0 +1,67 @@
+/** @file
+ PMC SoC configuration
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PMC_SOC_CONFIGURATION_H_
+#define _PMC_SOC_CONFIGURATION_H_
+
+typedef enum {
+ AdrSinglePhase = 0,
+ AdrDualPhase
+} ADR_PHASE_TYPE;
+
+typedef enum {
+ AdrGpioB = 0,
+ AdrGpioC
+
Re: [edk2-devel] [PATCH 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Chuang, Rosen
Subject: [PATCH 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components
Adds the following modules:
- IpBlock/P2sb/IncludePrivate
- IpBlock/P2sb/Library
- IpBlock/P2sb/LibraryPrivate
- IpBlock/PchDmi/IncludePrivate
- IpBlock/PchDmi/LibraryPrivate
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../Library/P2SbSidebandAccessLib.h | 105 +++
.../IncludePrivate/Library/PchSbiAccessLib.h | 58
.../P2sb/IncludePrivate/P2SbController.h | 32 +++
.../P2sb/IncludePrivate/Register/P2sbRegs.h | 53
.../Library/PeiDxeSmmPchPcrLib/PchPcrLib.c| 266 ++
.../PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf | 35 +++
.../PeiDxeSmmP2SbSidebandAccessLib.c | 208 ++
.../PeiDxeSmmP2SbSidebandAccessLib.inf| 30 ++
.../PchSbiAccessLib.c | 72 +
.../PeiDxeSmmPchSbiAccessLib.inf | 35 +++
.../PchDmi/IncludePrivate/Library/PchDmiLib.h | 60
.../PeiDxeSmmPchDmiLib/PchDmi14.c | 34 +++
.../PeiDxeSmmPchDmiLib/PchDmi14.h | 22 ++
.../PeiDxeSmmPchDmiLib/PchDmiLib.c| 110
.../PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf | 43 +++
15 files changed, 1163 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
new file mode 100644
index 00..e364508eb4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Libr
+++ ary/P2SbSidebandAccessLib.h
@@ -0,0 +1,105 @@
+/** @file
+ Header for P2SbSidebandAccessLib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_
+#define _P2SB_SIDEBAND_ACCESS_LIB_H_
+
+#include
+#include
+#include // For PCH_SBI_PID definition
+
+typedef PCH_SBI_PID P2SB_PID;
+
+typedef enum {
+ P2SbMemory = 0,
+ P2SbPciConfig,
+ P2SbPrivateConfig
+} P2SB_REGISTER_SPACE;
+
+typedef enum {
+ MemoryRead = 0x0,
+ MemoryWrite= 0x1,
+ PciConfigRead = 0x4,
+ PciConfigWrite = 0x5,
+ PrivateControlRead = 0x6,
+ PrivateControlWrite= 0x7,
+ GpioLockUnlock = 0x13
+} P2SB_SBI_OPCODE;
+
+typedef enum {
+ SBI_SUCCESSFUL = 0,
+ SBI_UNSUCCESSFUL= 1,
+ SBI_POWERDOWN = 2,
+ SBI_MIXED = 3,
+ SBI_INVALID_RESPONSE
+} P2SB_SBI_RESPONSE;
+
+typedef enum {
+ P2SbMmioAccess = 0,
+ P2SbMsgAccess
+} P2SB_SIDEBAND_ACCESS_METHOD;
+
+/**
+ REGISTER_ACCESS for P2SB device to support access to sideband registers.
+ Be sure to keep first member of this structure as REGISTER_ACCESS to
+allow
+ for correct casting between caller who sees this structure as
+REGISTER_ACCESS
+ and calle who will cast
Re: [edk2-devel] [PATCH 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Chuang, Rosen
Subject: [PATCH 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge,
PcieRp components
Adds the following modules:
- IpBlock/Graphics/Include
- IpBlock/Graphics/IncludePrivate
- IpBlock/Graphics/Library
- IpBlock/Graphics/LibraryPrivate
- IpBlock/HostBridge/IncludePrivate
- IpBlock/PcieRp/Library
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../Include/Ppi/GraphicsPlatformPolicyPpi.h | 76 +++
.../Library/DxeGraphicsPolicyLib.h| 71 +++
.../Library/DxeIgdOpRegionInitLib.h | 115 +
.../GraphicsInfoLibVer1.c | 52
.../GraphicsInfoLibVer1.inf | 33 +
.../DxeGraphicsPolicyLib.c| 116 +
.../DxeGraphicsPolicyLib.inf | 36 ++
.../DxeIgdOpRegionInit.c | 119 ++
.../DxeIgdOpRegionInitLib.inf | 47 +++
.../IncludePrivate/HostBridgeDataHob.h| 25
.../PchPcieRpLibInternal.h| 20 +++
.../PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c | 71 +++
.../PeiDxeSmmPchPcieRpLibVer2.inf | 37 ++
13 files changed, 818 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
new file mode 100644
index 00..a8f67061a5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/Gra
+++ phicsPlatformPolicyPpi.h
@@ -0,0 +1,76 @@
+/** @file
+ The PEI_GRAPHICS_PLATFORM_POLICY_PPI provides platform information to PEI
Graphics PEIM.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+#define _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+
+/**
+ Globally unique identifier for PEI platform policy PPI.
+**/
+#define PEI_GRAPHICS_PLATFORM_POLICY_PPI_GUID \ { \
+ 0x4eabcd09, 0x43d3, 0x4b4d, { 0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89,
+0x99, 0x5 } \ }
+
+#define PEI_GRAPHICS_PLATFORM_POLICY_REVISION 1
+
+/**
+Pre-declaration of PEI graphics platform policy PPI.
+**/
+typedef struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI
+PEI_GRAPHICS_PLATFORM_POLICY_PPI;
+
+/**
+ Enum defining the different lid status values **/ typedef enum {
+ LidClosed,
+ LidOpen,
+ LidStatusMax
+} LID_STATUS;
+
+/**
+ This function gets the platform lid status for LFP displays.
+
+ @param[out] CurrentLidStatus Output variable to store the lid status.
+
+ @retval EFI_SUCCESS Correct lid status is returned.
+ @retval EFI_UNSUPPORTED Platform does not support lid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+ OUT LID_STATUS *CurrentLidStatus
+ );
+
+/**
+ This function gets the base address of loaded VBT.
+
+ @param[out] VbtAddressStarting address of the VBT is returned in this
parameter.
+ @param[out] VbtSize Size of the VBT is returned in this parameter
Re: [edk2-devel] [PATCH 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components
Reviewed-by: Sai Chaganty -Original Message- From: Kasbekar, Saloni Sent: Wednesday, September 13, 2023 3:14 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Adds the following modules: - IpBlock/CpuPcieRp/Include - IpBlock/Espi/Library - IpBlock/Gpio/IncludePrivate - IpBlock/Gpio/Library - IpBlock/Gpio/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../IpBlock/CpuPcieRp/Include/CpuPcieInfo.h | 25 + .../Espi/Library/PeiDxeSmmEspiLib/EspiLib.c | 58 ++ .../PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf | 38 ++ .../IncludePrivate/Library/GpioHelpersLib.h | 50 ++ .../IncludePrivate/Library/GpioNativePads.h | 245 .../IncludePrivate/Library/GpioPrivateLib.h | 350 +++ .../Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c | 546 ++ .../Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c | 522 + .../Library/PeiDxeSmmGpioLib/GpioLibrary.h| 29 + .../Library/PeiDxeSmmGpioLib/GpioNativeLib.c | 177 ++ .../PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf | 44 ++ .../BaseGpioHelpersLibNull.c | 51 ++ .../BaseGpioHelpersLibNull.inf| 25 + .../GpioNativePrivateLibInternal.h| 48 ++ .../PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c | 267 + .../GpioPrivateLibPch.c | 172 ++ .../GpioPrivateLibVer2.c | 81 +++ .../PeiDxeSmmGpioPrivateLibVer2.inf | 40 ++ .../PeiGpioHelpersLib/PeiGpioHelpersLib.c | 218 +++ .../PeiGpioHelpersLib/PeiGpioHelpersLib.inf | 46 ++ 20 files changed, 3032 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h new file mode 100644 index 00..a6f8b16d10 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h @@ -0,0 +1,25 @@ +/** @file + This file contains definitions of PCIe controller information + + Copyright (c) 2022, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CPU_PCIE_INFO_H_ +#define _CPU_PCIE_INFO_H_ + +#define PCIE_HWEQ_COEFFS_MAX5 + + +// +// SA PCI Express* Port configuration +// + +#define CPU_PCIE_MAX_ROOT_PORTS4 +#define CPU_PCIE_MAX_CONTROLLERS 3 + +#define SA_PEG_MAX_FUN 0x04 +#define SA_PEG_MAX_LANE 0x14
Re: [edk2-devel] [PATCH 3/4] Readme.md: Add AlderlakeOpenBoardPkg
Reviewed-by: Sai Chaganty -Original Message- From: Kasbekar, Saloni Sent: Wednesday, September 13, 2023 3:06 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH 3/4] Readme.md: Add AlderlakeOpenBoardPkg Add AlderlakeOpenBoardPkg in the Readme Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- Readme.md | 1 + 1 file changed, 1 insertion(+) diff --git a/Readme.md b/Readme.md index 624f9a6da6..8de9eaa7cf 100644 --- a/Readme.md +++ b/Readme.md @@ -254,6 +254,7 @@ they will be documented with the platform. * [Comet Lake](Platform/Intel/CometlakeOpenBoardPkg) * [Tiger Lake](Platform/Intel/TigerlakeOpenBoardPkg) * [Whitley/Cedar Island](Platform/Intel/WhitleyOpenBoardPkg) +* [Alder Lake](Platform/Intel/AlderlakeOpenBoardPkg) For more information, see the [EDK II Minimum Platform Specification](https://edk2-docs.gitbooks.io/edk-ii-minimum-platform-specification). -- 2.36.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108629): https://edk2.groups.io/g/devel/message/108629 Mute This Topic: https://groups.io/mt/101347620/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 2/4] Enable build for AlderlakeOpenBoardPkg
Reviewed-by: Sai Chaganty -Original Message- From: Kasbekar, Saloni Sent: Wednesday, September 13, 2023 3:06 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH 2/4] Enable build for AlderlakeOpenBoardPkg This change adds the configuration to enable build for AlderlakePRvp. Also it updates Alderlake P Rvp details to the Readme.md. Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- Platform/Intel/Readme.md | 11 +++ Platform/Intel/build.cfg | 1 + 2 files changed, 12 insertions(+) diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index 953260852d..112d0af1f6 100644 --- a/Platform/Intel/Readme.md +++ b/Platform/Intel/Readme.md @@ -59,6 +59,7 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol * The `WhiskeylakeOpenBoardPkg` contains board implementations for WhiskeyLake systems. * The `CometlakeOpenBoardPkg` contains board implementations for CometLake systems. * The `TigerlakeOpenBoardPkg` contains board implementations for TigerLake systems. +* The `AlderlakeOpenBoardPkg` contains board implementations for AlderLake systems. * The `WhitleyOpenBoardPkg` contains board implementations for Ice Lake-SP and Cooper Lake systems. ### **Supported Hardware** @@ -87,6 +88,7 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol | WHL-U DDR4 RVP| WhiskeyLake | WhiskeylakeOpenBoardPkg | WhiskeylakeURvp| | CML-U LPDDR3 RVP | CometLake V1 | CometlakeOpenBoardPkg| CometlakeURvp | | TGL-U DDR4 RVP| TigerLake | TigerlakeOpenBoardPkg| TigerlakeURvp | +| ADL-P DDR5 RVP| AlderLake | AlderlakeOpenBoardPkg| AlderlakePRvp | | Wilson City RVP | IceLake-SP (Xeon Scalable) | WhitleyOpenBoardPkg | WilsonCityRvp | | Cooper City RVP | Copper Lake | WhitleyOpenBoardPkg | CooperCityRvp | @@ -316,6 +318,11 @@ return back to the minimum platform caller. | || |---build_config.cfg: TigerlakeURvp specific build | || settings environment variables. | || + | ||--AlderlakeOpenBoardPkg + | || |--AlderlakePRvp + | || |---build_config.cfg: AlderlakePRvp specific build + | || settings environment variables. + | || |--FSP @@ -401,6 +408,10 @@ For PurleyOpenBoardPkg (TiogaPass) 1. This firmware project has been tested booting to Microsoft Windows 10 x64 with AHCI mode and Integrated Graphic Device. 2. This firmware project has been also tested booting to Puppy Linux BionicPup64 8.0 with AHCI mode and Integrated Graphic Device. +**AlderlakeOpenBoardPkg** +1. This firmware project has been tested booting to Microsoft Windows 11 x64 with M2 SSD Disk and Integrated Graphic Device. +2. AlderlakeOpenBoardPkg/Acpi/MinDsdt has been modified from MinPlatformPkg/Acpi/MinDsdt to avoid hang on boot to Microsoft Windows 11 x64. + **WhitleyOpenBoardPkg** 1. This firmware project has been tested booting to UEFI shell with headless serial console diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg index fe0ddb7a1e..2ff536bb3e 100644 --- a/Platform/Intel/build.cfg +++ b/Platform/Intel/build.cfg @@ -70,3 +70,4 @@ WilsonCityRvp = WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg BoardTiogaPass = PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg JunctionCity = WhitleyOpenBoardPkg/JunctionCity/build_config.cfg Aowanda = WhitleyOpenBoardPkg/Aowanda/build_config.cfg +AlderLakePRvp = AlderLakeOpenBoardPkg/AlderLakePRvp/build_config.cfg -- 2.36.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108628): https://edk2.groups.io/g/devel/message/108628 Mute This Topic: https://groups.io/mt/101347618/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 1/4] AlderlakeOpenBoardPkg/AlderlakePRvp: Add DSC and build files
Reviewed-by: Sai Chaganty -Original Message- From: Kasbekar, Saloni Sent: Wednesday, September 13, 2023 3:05 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH 1/4] AlderlakeOpenBoardPkg/AlderlakePRvp: Add DSC and build files Adds the DSC and build files necessary to build the AlderlakePRvp board instance. Key files: * build_config.cfg - Board-specific build configuration file. * OpenBoardPkg.dsc - The AlderlakePRvp board description file. * OpenBoardPkgPcd.dsc - Used for other PCD customization. * OpenBoardPkg.fdf - The AlderlakePRvp board flash file. * OpenBoardPkgBuildOption.dsc - Sets build options Based on PCD values. * FlashMapInclude.fdf - AlderlakePRvp flash map file. Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Include/Fdf/FlashMapInclude.fdf | 52 ++ .../AlderlakePRvp/OpenBoardPkg.dsc| 481 .../AlderlakePRvp/OpenBoardPkg.fdf| 724 ++ .../AlderlakePRvp/OpenBoardPkgBuildOption.dsc | 161 .../AlderlakePRvp/OpenBoardPkgPcd.dsc | 371 + .../AlderlakePRvp/build_config.cfg| 34 + 6 files changed, 1823 insertions(+) create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/FlashMapInclude.fdf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgBuildOption.dsc create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.dsc create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/build_config.cfg diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/FlashMapInclude.fdf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/FlashMapInclude.fdf new file mode 100644 index 00..03c198c06a --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/FlashMapInclude.fdf @@ -0,0 +1,52 @@ +## @file +# FDF file of Platform. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +#=# +# 16 MB BIOS - for FSP wrapper +#=# +DEFINE FLASH_BASE = 0xFF00 # +DEFINE FLASH_SIZE = 0x0100 # +DEFINE FLASH_BLOCK_SIZE = 0x0001 # +DEFINE FLASH_NUM_BLOCKS = 0x0100 # +#=# + +#=# +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x # Flash addr (0xFF00) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x0006 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x # Flash addr (0xFF00) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0002E000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0002E000 # Flash addr (0xFF02E000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize= 0x2000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x0003 # Flash addr (0xFF03) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = 0x0003 # + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset= 0x000E # Flash addr (0xFF0E) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x0031 # +SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset = 0x003F # Flash addr (0xFF40) +SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize = 0x0036 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset= 0x0075 # Flash addr (0xFF76) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x0009 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x007E # Flash addr (0xFF7F) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize= 0x000A # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset= 0x0088 # Flash addr (0xFF86) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x0018 # + +SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset = 0x00A0 # Flash addr
Re: [edk2-devel] [PATCH 4/4] Maintainers.txt: Add maintainers
Reviewed-by: Sai Chaganty -Original Message- From: Kasbekar, Saloni Sent: Wednesday, September 13, 2023 3:06 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH 4/4] Maintainers.txt: Add maintainers Add AlderlakeSiliconPkg and AlderlakeOpenBoardPkg maintainers Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- Maintainers.txt | 14 ++ 1 file changed, 14 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index d1d7613ef4..936304d608 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -245,6 +245,13 @@ M: Sai Chaganty M: Nate DeSimone R: Heng Luo +Platform/Intel/AlderlakeOpenBoardPkg +F: Platform/Intel/AlderlakeOpenBoardPkg/ +M: Sai Chaganty +M: Nate DeSimone +R: Rosen Chuang +R: Saloni Kasbekar + Platform/Intel/WhitleyOpenBoardPkg F: Platform/Intel/WhitleyOpenBoardPkg/ M: Isaac Oram @@ -316,6 +323,13 @@ M: Sai Chaganty M: Nate DeSimone R: Heng Luo +Platform/Intel/AlderlakeSiliconPkg +F: Platform/Intel/AlderlakeSiliconPkg/ +M: Sai Chaganty +M: Nate DeSimone +R: Rosen Chuang +R: Saloni Kasbekar + Silicon/Intel/WhitleySiliconPkg F: Silicon/Intel/WhitleySiliconPkg/ M: Isaac Oram -- 2.36.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108626): https://edk2.groups.io/g/devel/message/108626 Mute This Topic: https://groups.io/mt/101347621/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2 6/6] AlderlakeOpenBoardPkg: Add Library Instances
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Tuesday, August 01, 2023 3:18 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Oram, Isaac W ;
Chuang, Rosen
Subject: [PATCH v2 6/6] AlderlakeOpenBoardPkg: Add Library Instances
Adds the following libraries
- BasePlatformHookLib
- PeiBoardConfigLib
- PeiGetFvInfoLib
- SmmSpiFlashCommonLib
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Isaac Oram
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../BasePlatformHookLib/BasePlatformHookLib.c | 38
.../BasePlatformHookLib.inf | 44
.../PeiBoardConfigLib/PeiBoardConfigLib.c | 136 +++
.../PeiBoardConfigLib/PeiBoardConfigLib.inf | 56 +
.../Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c | 89
.../PeiGetFvInfoLib/PeiGetFvInfoLib.inf | 34 +++
.../SmmSpiFlashCommonLib.inf | 49
.../SmmSpiFlashCommonLib/SpiFlashCommon.c | 215 ++
.../SpiFlashCommonSmmLib.c| 60 +
9 files changed, 721 insertions(+)
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
new file mode 100644
index 00..cccb1e18cc
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/B
+++ asePlatformHookLib.c
@@ -0,0 +1,38 @@
+/** @file
+ Platform Hook Library instances
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+
+
+/**
+ Performs platform specific initialization required for the CPU to
+access
+ the hardware associated with a SerialPortLib instance. This function
+does
+ not initialize the serial port hardware itself. Instead, it
+initializes
+ hardware devices that are required for the CPU to access the serial
+port
+ hardware. This function may be called more than once.
+
+ @retval RETURN_SUCCESS The platform specific initialization succeeded.
+ @retval RETURN_DEVICE_ERROR The platform specific initialization could not
be completed.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+ VOID
+ )
+{
+
+ //
+ // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port
2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.
+ //
+ PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
+ PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
+
+ return RETURN_SUCCESS;
+}
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
new file mode 100644
index 00..b77724d5ab
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/B
+++ asePlatformHookLib.inf
@@ -0,0 +1,44 @@
+### @file
+# Platform Hook Library instance for Alderlake Mobile/Desktop CRB.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION= 0x00010017
+ BASE_NAME = BasePlatformHookLib
+ FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
+ VERSION_STRING = 1.0
+ MODULE_TYPE= BASE
+ LIBRARY_CLASS = PlatformHookLib
+#
+# The following information is for reference only and not required by the
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC #
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciSegmentLib
+ PciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress## CONSUMES
+
+[FixedPcd
Re: [edk2-devel] [PATCH v2 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Tuesday, August 01, 2023 3:18 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Oram, Isaac W ;
Chuang, Rosen
Subject: [PATCH v2 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module
Adds the following libraries within the Policy module
- DxeSiliconPolicyUpdateLib
- PeiPolicyUpdateLib
- PeiSiliconPolicyUpdateLib
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Isaac Oram
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../DxeSaPolicyInit.c | 64 +++
.../DxeSiliconPolicyUpdateLate.c | 78
.../DxeSiliconPolicyUpdateLib.inf | 53 +++
.../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c | 114 +
.../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h | 31 ++
.../PeiCpuPolicyUpdatePreMem.c| 93 +
.../PeiPolicyUpdateLib/PeiPchPolicyUpdate.c | 210 ++
.../PeiPolicyUpdateLib/PeiPchPolicyUpdate.h | 24 ++
.../PeiPchPolicyUpdatePreMem.c| 124 ++
.../PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf | 208 ++
.../PeiPolicyUpdateLib/PeiSaPolicyUpdate.c| 214 ++
.../PeiPolicyUpdateLib/PeiSaPolicyUpdate.h| 27 ++
.../PeiSaPolicyUpdatePreMem.c | 389 ++
.../PeiSiliconPolicyUpdateLib.inf | 65 +++
.../PeiSiliconPolicyUpdatePostMem.c | 39 ++
.../PeiSiliconPolicyUpdatePreMem.c| 37 ++
16 files changed, 1770 insertions(+)
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
new file mode 100644
index 00..da2f568e07
--- /dev/null
+++
b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
@@ -0,0 +1,64 @@
+/** @file
+ This file initialises and Installs GopPolicy Protocol.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+
+EFI_STATUS
+EFIAPI
+CreateSaDxeConfigBlocks (
+ IN OUT VOID **SaPolicy
+ );
+
+EFI_STATUS
+EFIAPI
+SaInstallPolicyProtocol (
+ IN EFI_HANDLE ImageHandle,
+ IN VOID*SaPolicy
+ );
+
+/**
+ Initialize SA DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCESDo not have enough resources to initialize
the driver.
+ @retval EFI_DEVICE_ERRORDevice error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+ SA_POLICY_PROTOCOL *SaPolicy;
+
+ //
+ // Call CreateSaDxeConfigBlocks to create & initialize platform po
Re: [edk2-devel] [PATCH v2 4/6] AlderlakeOpenBoardPkg: Add ACPI module
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Tuesday, August 01, 2023 3:18 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Oram, Isaac W ;
Chuang, Rosen
Subject: [PATCH v2 4/6] AlderlakeOpenBoardPkg: Add ACPI module
Adds the MinDsdt driver
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Isaac Oram
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../Acpi/MinDsdt/MinDsdt.asl | 68 +
.../Acpi/MinDsdt/MinDsdt.c| 232 ++
.../Acpi/MinDsdt/MinDsdt.inf | 48
3 files changed, 348 insertions(+)
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl
b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl
new file mode 100644
index 00..be110145bc
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl
@@ -0,0 +1,68 @@
+/** @file
+ ACPI minimum DSDT table
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+DefinitionBlock (
+ "DSDT.aml",
+ "DSDT",
+ 0x01, // DSDT revision.
+// A Revision field value greater than or equal to 2 signifies that
integers
+// declared within the Definition Block are to be evaluated as 64-bit
values
+ "INTEL ", // OEM ID (6 byte string)
+ "MIN ",// OEM table ID (8 byte string)
+ 0x00 // OEM version of DSDT table (4 byte Integer)
+)
+
+// BEGIN OF ASL SCOPE
+{
+ Scope(\_SB) {
+
+//-
+--
+ // Begin PCI tree object scope
+ //---
+Device(PCI0) { // PCI Bridge "Host Bridge"
+ Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host
hierarchy
+ Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't
understand the new HID
+ Name(_SEG, 0)
+ Method(^BN00, 0){ return(0x) } // Returns default Bus number for
Peer PCI busses. Name can be overriden with control method placed directly
under Device scope
+ Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root
PCI Bus
+ Name(_UID, 0x) // Unique Bus ID, optional
+ Name(BUF0,ResourceTemplate()
+ {
+//
+// PCI Configuration Registers ( 0x0CF8 - 0x0CFF )
+//
+Io(Decode16,0x0CF8,0x0CF8,1,0x08)
+//
+// PCI MMIO space
+//
+DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0x00,0x00,0x00,0x00,,,PM01)
+ })
+ Method(_CRS,0,Serialized)
+ {
+//
+// Create pointers to Memory Sizing values.
+//
+CreateDwordField(BUF0, ^PM01._MIN,M1MN)
+CreateDwordField(BUF0, ^PM01._MAX,M1MX)
+CreateDwordField(BUF0, ^PM01._LEN,M1LN)
+
+//
+// Set Memory Size Values. TLUD represents bits 31:20 of phyical
+// TOM, so shift these bits into the correct position and fix up
+// the Memory Region available to PCI.
+//
+Subtract
(FixedPcdGet32(PcdPciReservedMemLimit),FixedPcdGet32(PcdPciReservedMemBase),M1LN)
+Store (FixedPcdGet32(PcdPciReservedMemBase), M1MN)
+Subtract (FixedPcdGet32(PcdPciReservedMemLimit), 1, M1MX)
+
+Return(BUF0)
+ }
+}
+ }
+}// End of ASL File
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c
b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c
new file mode 100644
index 00..08709a43cd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c
@@ -0,0 +1,232 @@
+/** @file
+ Min DSDT Driver
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+//
+// Function implementations
+//
+
+/**
+ Locate the first instance of a protocol. If the protocol requested
+is an
+ FV protocol, then it will return the first FV that contains the ACPI
+table
+ storage file.
+
+ @param[in] Protocol The protocol to find.
+ @param[in] FfsGuidThe FFS that contains the ACPI table.
+ @param[out] Instance Return pointer to the first instance of the
protocol.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND The protocol could not be located.
+ @retval EFI_
Re: [edk2-devel] [PATCH v2 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add libraries
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Tuesday, August 01, 2023 3:18 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Oram, Isaac W ;
Chuang, Rosen
Subject: [PATCH v2 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add libraries
Adds the following library instances:
- BoardAcpiLib
- BoardInitLib
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Isaac Oram
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../SmmAlderlakePRvpAcpiEnableLib.c | 50 +
.../SmmMultiBoardAcpiSupportLib.c | 88
.../SmmMultiBoardAcpiSupportLib.inf | 41
.../BoardAcpiLib/SmmSiliconAcpiEnableLib.c| 134
.../BoardInitLib/Pei/BoardPchInitPreMemLib.c | 104 +
.../BoardInitLib/Pei/BoardSaConfigPreMem.h| 73 +++
.../BoardInitLib/Pei/BoardSaInitPreMemLib.c | 160 ++
.../Library/BoardInitLib/Pei/PeiDetect.c | 62 ++
.../BoardInitLib/Pei/PeiInitPostMemLib.c | 100 +
.../BoardInitLib/Pei/PeiInitPreMemLib.c | 202 ++
.../Pei/PeiMultiBoardInitPostMemLib.c | 45
.../Pei/PeiMultiBoardInitPostMemLib.inf | 53 +
.../Pei/PeiMultiBoardInitPreMemLib.c | 89
.../Pei/PeiMultiBoardInitPreMemLib.inf| 149 +
14 files changed, 1350 insertions(+)
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c
new file mode 100644
index 00..8dfc04c5f5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAc
+++ piLib/SmmAlderlakePRvpAcpiEnableLib.c
@@ -0,0 +1,50 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ Enable Board Acpi
+
+ @param[in] EnableSci Enable SCI if EnableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable Board Acpi
+
+ @param[in] DisableSciDisable SCI if DisableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
new file mode 100644
index 00..ea0f7c966b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAc
+++ piLib/SmmMultiBoardAcpiSupportLib.c
@@ -0,0 +1,88 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
Re: [edk2-devel] [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Tuesday, August 01, 2023 3:18 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Oram, Isaac W ;
Chuang, Rosen
Subject: [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules
Adds the following modules:
-BiosInfo
-OpenBoardPlatformInit
-SBCVpdStructurePcd
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Isaac Oram
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c | 196 +++
.../BiosInfo/BiosInfo.inf | 84 +++
.../OpenBoardPlatformInitPostMem.c| 233 ++
.../OpenBoardPlatformInitPostMem.inf | 75 ++
.../SBCVpdStructurePcd/AllStructPCD.dsc | 19 ++
.../GpioTableAdlPPostMem.dsc | 40 +++
.../GpioTableAdlPPreMem.dsc | 29 +++
.../MrcDqDqsSPD/AdlPSpdMap.dsc| 138 +++
.../PcieClocks/AdlPPcieClocks.dsc | 31 +++
9 files changed, 845 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
create mode 100644
Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
new file mode 100644
index 00..64462900de
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
@@ -0,0 +1,196 @@
+/** @file
+ PEIM to provide BiosInfo structure listing up all firmware volume's
+base addresses, sizes,
+ attributes, and information associated to the firmware volume.
+ Primarily the structure is used on FIT table creation and Bpm.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define BASE_FV_SIZE 10
+
+#define FSP_WRAPPER_FV_SIZE 3
+
+#define TSN_MAC_ADDRESS_FV_SIZE 0
+
+#define BIOS_INFO_STRUCT_SIZE (BASE_FV_SIZE + FSP_WRAPPER_FV_SIZE +
+TSN_MAC_ADDRESS_FV_SIZE)
+
+
+/*
+ BIOS_INFO structure is the base of the firmware volume layout for
+Intel platform BIOS implementation
+ so security checker module can run based on the structure and throw
+warnings, error or deadloop
+ when any unexpected firmware volumes are detected.
+
+ BIOS_INFO is recommended to support full entries of firmware volumes
+present in a flash
+ with right type, attribute, version, flash map base address and size,
+ all associated information which is defined by BIOS_INFO_STRUCT structure.
+ - IBB firmware volumes, which are expected to be measured or/and verified
+by hardware base security solution to meet SecureBoot chain of trust
+(Intel BootGuard for example), have attribute 0x0.
+ - Post IBB firmware volumes, which are expected to be measured or/and
verified
+by BIOS (TCG code for measurement, RSA2048SHA256Sign algorithm for
verification for example),
+have attribute BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB.
+ - Else, follows Firmware Interface Table specification.
+*/
+#pragma pack (1)
+typedef struct {
+ BIOS_INFO_HEADER Header;
+ BIOS_INFO_STRUCT Entry[BIOS_INFO_STRUCT_SIZE]; } BIOS_INFO; #pragma
+pack ()
+
+GLOBAL_REMOVE_IF_UNREFERENCED BIOS_INFO mBiosInfo = {
+ {
+BIOS_INFO_SIGNATURE,
+BIOS_INFO_STRUCT_SIZE,
+0,
+ },
+ {
+{
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize) + FixedPcdGet32
(PcdFlashNvStorageFtwWorkingSize) + FixedPcdGet32
(PcdFlashNvStorageFtwSpareSize),
+ FixedPcdGet32 (PcdFlashNvStorageVariableBase)
+},
+{
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvAdvancedSize),
+ FixedPcdGet32 (PcdFlashFvAdvancedBase)
+},
+{
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOptionalSize
Re: [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers
Reviewed-by: Sai Chaganty -Original Message- From: Kasbekar, Saloni Sent: Tuesday, August 01, 2023 3:18 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Oram, Isaac W ; Chuang, Rosen Subject: [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers Create the AlderlakeOpenBoardPkg to provide board support code. The package supports Alderlake Mobile board with LPDDR4. The package serves as a support package in the EDK II Minimum Platform design. Cc: Sai Chaganty Cc: Nate DeSimone Cc: Isaac Oram Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Include/Library/BoardConfigLib.h | 59 .../Include/Library/PeiGetFvInfoLib.h | 29 ++ .../Include/Library/SpiFlashCommon.h | 99 ++ .../Include/PlatformBoardConfig.h | 93 ++ .../Include/PlatformBoardId.h | 21 ++ .../Include/PlatformGpioConfig.h | 18 + .../Include/PlatformPostCode.h| 39 +++ .../Include/PolicyUpdateMacro.h | 48 +++ .../AlderlakeOpenBoardPkg/OpenBoardPkg.dec| 307 ++ 9 files changed, 713 insertions(+) create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h new file mode 100644 index 00..3a07563c5d --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLi +++ b.h @@ -0,0 +1,59 @@ +/** @file + Function prototype of BoardConfigLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _BOARD_CONFIG_LIB_H_ +#define _BOARD_CONFIG_LIB_H_ + +#include +#include + +#define SIZE_OF_FIELD(TYPE, Field) (sizeof (((TYPE *)0)->Field)) + +#define SIZE_OF_TABLE(TABLE, TYPE) (sizeof (TABLE) / sizeof (TYPE)) + +#define BOARD_CONFIG PLATFORM_INFO + +#define PRE_MEM0 +#define POST_MEM 1 +#define EARLY_PRE_MEM 2 + +/** + Procedure to detect current board HW configuration. + +**/ +VOID +EFIAPI +GetBoardConfig ( + VOID + ); + + +/** + Count the number of GPIO settings in the Table. + + @param[in] GpioTable The pointer of GPIO config table + @param[out] GpioCount The number of GPIO config entries +**/ +VOID +GetGpioTableSize ( + GPIO_INIT_CONFIG *GpioTable, + OUT UINT16 *GpioCount + ); + + +/** + Configure GPIO pads in PEI phase. + + @param[in] GpioTable Pointer to Gpio table **/ VOID GpioInit ( + IN GPIO_INIT_CONFIG *GpioTable + ); + +#endif // _BOARD_CONFIG_LIB_H_ diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h new file mode 100644 index 00..f2e5a77787 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoL +++ ib.h @@ -0,0 +1,29 @@ +/** @file + Header file for PeiGetFvInfoLib.. + + Copyright (c) 2022, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_GET_FV_INFO_LIB_H_ +#define _PEI_GET_FV_INFO_LIB_H_ + +/** + PeiGetSectionFromFv finds the file in FV and gets file Address and +Size + + @param[in] NameGuid - File GUID + @param[out] Address - Pointer to the File Address + @param[out] Size - Pointer to File Size + + @retval EFI_SUCCESSSuccessfull in reading the section from FV +**/ +EFI_STATUS +EFIAPI +PeiGetSectionFromFv ( + IN CONST EFI_GUIDNameGuid, + OUT VOID **Address, + OUT UINT32*Size + ); + +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h new file mode 100644 index 00..76ba3a8094 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommo +++ n.h @@ -0,0 +1,99 @@ +/** @file + The header file includes the common header files, defines + internal structure and functions used by SpiFlashCommonLib. + + Copyright (c) 2022, Intel Corporation. All rig
Re: [edk2-devel] [PATCH 8/8] AlderlakeSiliconPkg/SystemAgent: Add library and driver modules
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Thursday, June 15, 2023 10:53 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Oram, Isaac W ;
Chuang, Rosen
Subject: [PATCH 8/8] AlderlakeSiliconPkg/SystemAgent: Add library and driver
modules
Adds the following modules:
- Library/DxeSaPolicyLib
- SaInit
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Isaac Oram
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../Library/DxeSaPolicyLib/DxeSaPolicyLib.c | 225 ++
.../Library/DxeSaPolicyLib/DxeSaPolicyLib.inf | 46
.../DxeSaPolicyLib/DxeSaPolicyLibrary.h | 30 +++
.../SystemAgent/SaInit/Dxe/SaAcpi.c | 193 +++
.../SystemAgent/SaInit/Dxe/SaInit.c | 97
.../SystemAgent/SaInit/Dxe/SaInit.h | 42
.../SystemAgent/SaInit/Dxe/SaInitDxe.c| 90 +++
.../SystemAgent/SaInit/Dxe/SaInitDxe.h| 119 +
.../SystemAgent/SaInit/Dxe/SaInitDxe.inf | 98
9 files changed, 940 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLibrary.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
new file mode 100644
index 00..d812f300c1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyL
+++ ib/DxeSaPolicyLib.c
@@ -0,0 +1,225 @@
+/** @file
+ This file provide services for DXE phase policy default
+initialization
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include "DxeSaPolicyLibrary.h"
+#include #include
+ #include "MemoryConfig.h"
+
+extern EFI_GUID gMemoryDxeConfigGuid;
+
+/**
+ This function prints the SA DXE phase policy.
+
+ @param[in] SaPolicy - SA DXE Policy protocol **/ VOID
+SaPrintPolicyProtocol (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ UINT8 ControllerIndex;
+ UINT8 ChannelIndex;
+ EFI_STATUS Status;
+ MEMORY_DXE_CONFIG *MemoryDxeConfig;
+
+ Status = GetConfigBlock ((VOID *) SaPolicy, ,
+ (VOID *)); ASSERT_EFI_ERROR (Status);
+
+
+ DEBUG_CODE_BEGIN ();
+ INTN i;
+
+ DEBUG ((DEBUG_INFO, "\n SA Policy (DXE) print
+ BEGIN -\n")); DEBUG ((DEBUG_INFO, "Revision : %x\n",
+ SaPolicy->TableHeader.Header.Revision));
+ ASSERT (SaPolicy->TableHeader.Header.Revision ==
+ SA_POLICY_PROTOCOL_REVISION);
+
+ DEBUG ((DEBUG_INFO, " SA_MEMORY_CONFIGURATION
+ -\n"));
+
+ DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", 4)); for (i = 0; i <
+ 4; i++) {
+DEBUG ((DEBUG_INFO, " %x", MemoryDxeConfig->SpdAddressTable[i]));
+ }
+ DEBUG ((DEBUG_INFO, "\n"));
+
+ for (ControllerIndex = 0; ControllerIndex < MEM_CFG_MAX_CONTROLLERS;
ControllerIndex++) {
+for (ChannelIndex = 0; ChannelIndex < MEM_CFG_MAX_CHANNELS;
ChannelIndex++) {
+ DEBUG ((DEBUG_INFO, " SlotMap[%d][%d] : 0x%x\n", ControllerIndex,
ChannelIndex, MemoryDxeConfig->SlotMap[ControllerIndex][ChannelIndex]));
+}
+ }
+ DEBUG ((DEBUG_INFO, " MrcTimeMeasure : %x\n",
MemoryDxeConfig->MrcTimeMeasure));
+ DEBUG ((DEBUG_INFO, " MrcFastBoot : %x\n",
MemoryDxeConfig->MrcFastBoot));
+
+ DEBUG ((DEBUG_INFO, " CPU_PCIE_CONFIGURATION
+ -\n")); DEBUG ((DEBUG_INFO, " PegAspm[%d] :",
+ SA_PEG_MAX_FUN)); DEBUG ((DEBUG_INFO, " PegRootPortHPE[%d] :",
+ SA_PEG_MAX_FUN)); DEBUG ((DEBUG_INFO, "\n"));
+
+
+ DEBUG ((DEBUG_INFO, "\n SA Policy (DXE) print
+ END -\n")); DEBUG_CODE_END ();
+
+ return;
+}
+
+/**
+ Load DXE Config block default
+
+ @param[in] ConfigBlockPointer Pointer to config block
+**/
+VOID
+LoadMemoryDxeDefault (
+ IN VO
Re: [edk2-devel] [PATCH 7/8] AlderlakeSiliconPkg/SystemAgent: Add include headers
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Thursday, June 15, 2023 10:53 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Oram, Isaac W ;
Chuang, Rosen
Subject: [PATCH 7/8] AlderlakeSiliconPkg/SystemAgent: Add include headers
Adds the following header files:
* SystemAgent/Include
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Isaac Oram
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../Include/ConfigBlock/MemoryDxeConfig.h | 126 ++
.../ConfigBlock/SaMiscPeiPreMemConfig.h | 112 +
.../Include/Library/DxeSaPolicyLib.h | 58 +
.../Include/Library/PeiSaPolicyLib.h | 13 ++
.../SystemAgent/Include/MemInfoHob.h | 220 ++
.../SystemAgent/Include/Protocol/SaPolicy.h | 54 +
.../SystemAgent/Include/SaDataHob.h | 28 +++
7 files changed, 611 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Library/DxeSaPolicyLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Library/PeiSaPolicyLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/SaDataHob.h
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
new file mode 100644
index 00..eca0c2f1ba
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/ConfigBlock/
+++ MemoryDxeConfig.h
@@ -0,0 +1,126 @@
+/** @file
+ Memory DXE Policy definitions
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_MEMORY_DXE_CONFIG_H_ #define _MEMORY_DXE_CONFIG_H_
+
+#pragma pack(push, 1)
+
+/**
+ Making any setup structure change after code frozen will need to
+maintain backward compatibility, bump up structure revision and update
+below history table\n
+ Revision 1: - Initial version.
+**/
+#define MEMORY_DXE_CONFIG_REVISION 2
+
+typedef struct _MEMORY_DXE_CONFIG MEMORY_DXE_CONFIG;
+
+/**
+ Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocator
field.
+ Implementation of this function is optional, if this function pointer
+is NULL then
+ the reference implementation of DeviceLocator will be used.
+
+ @param[in] This A pointer to this instance of
MEMORY_DXE_CONFIG.
+ @param[in] ControllerDesired Controller to get a
DeviceLocator string for.
+ @param[in] Dimm Desired DIMM to get a
DeviceLocator string for.
+ @param[in] MdSocket 0 = Memory Down, 1 = Socketed.
+
+ @retval The DeviceLocator string
+ @retval NULL If the return value is NULL, the
default value will be used.
+**/
+typedef
+CHAR8*
+(EFIAPI *MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING)(
+ IN CONSTMEMORY_DXE_CONFIG *This,
+ IN UINT8 Controller,
+ IN UINT8 Dimm,
+ IN UINT8 MdSocket
+ );
+
+/**
+ Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator
field.
+ Implementation of this function is optional, if this function pointer
+is NULL then
+ the reference implementation of DeviceLocator will be used.
+
+ @param[in] This A pointer to this instance of
MEMORY_DXE_CONFIG.
+ @param[in] ControllerDesired Controller to get a
BankLocator string for.
+ @param[in] Dimm Desired DIMM to get a BankLocator
string for.
+ @param[in] MdSocket 0 = Memory Down, 1 = Socketed.
+
+ @retval The BankLocator string
+ @retval NULL If the return value is NULL, the
default value will be used.
+**/
+typedef
+CHAR8*
+(EFIAPI *MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING)(
+ IN CONSTMEMORY_DXE_CONFIG *This,
+ IN UINT8 Controller,
+ IN UINT8 Dimm,
+ IN UINT8 MdSocket
+ );
+
+/**
+ The Memory Configuration includes DIMM SPD address Map and DIMM Slot
Mechanical present bit map.
+ The data elements should be initialized by a Platform Module.\n
+ Revision 1:
+ - Initial version.
+**/
+struct _MEMORY_DXE_CONFIG {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config
Block Header
+/**
+ Off
Re: [edk2-devel] [PATCH 6/8] AlderlakeSiliconPkg/SystemAgent: Add NVS support
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Thursday, June 15, 2023 10:53 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Oram, Isaac W ;
Chuang, Rosen
Subject: [PATCH 6/8] AlderlakeSiliconPkg/SystemAgent: Add NVS support
Adds the System Agent NVS ACPI table and structures
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Isaac Oram
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../SystemAgent/AcpiTables/SaSsdt/SaNvs.asl | 18 +++
.../IncludePrivate/Protocol/SaNvsArea.h | 30 +++
.../SystemAgent/IncludePrivate/SaNvsAreaDef.h | 22 ++
3 files changed, 70 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaNvs.asl
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/IncludePrivate/SaNvsAreaDef.h
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaNvs.asl
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaNvs.asl
new file mode 100644
index 00..e9785873d2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Sa
+++ Nvs.asl
@@ -0,0 +1,18 @@
+/**@file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+ //
+ // Define SA NVS Area operation region.
+ //
+
+
+ OperationRegion(SANV,SystemMemory,SANB,SANL)
+ Field(SANV,AnyAcc,Lock,Preserve)
+ { Offset(0), M64B, 64, // Offset(0), Base of above 4GB MMIO resource
+ Offset(8),M64L, 64, // Offset(8), Length of above 4GB MMIO resource
+ Offset(16),M32B, 32, // Offset(16), Base of below 4GB MMIO resource
+ Offset(20),M32L, 32, // Offset(20), Length of below 4GB MMIO resource
+ }
\ No newline at end of file
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNvsArea.h
new file mode 100644
index 00..3a75465843
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/IncludePrivate/Proto
+++ col/SaNvsArea.h
@@ -0,0 +1,30 @@
+/** @file
+ Definition of the System Agent global NVS area protocol.
+ This protocol publishes the address and format of a global ACPI NVS
+buffer
+ used as a communications buffer between SMM/DXE/PEI code and ASL code.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _SYSTEM_AGENT_NVS_AREA_H_
+#define _SYSTEM_AGENT_NVS_AREA_H_
+
+//
+// SA NVS Area definition
+//
+#include
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gSaNvsAreaProtocolGuid;
+
+///
+/// System Agent Global NVS Area Protocol /// typedef struct {
+ SYSTEM_AGENT_NVS_AREA *Area;///< System Agent Global NVS Area
Structure
+} SYSTEM_AGENT_NVS_AREA_PROTOCOL;
+
+#endif // _SYSTEM_AGENT_NVS_AREA_H_
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/IncludePrivate/SaNvsAreaDef.h
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/IncludePrivate/SaNvsAreaDef.h
new file mode 100644
index 00..5b8136866a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/IncludePrivate/SaNvs
+++ AreaDef.h
@@ -0,0 +1,22 @@
+/**@file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+ //
+ // Define SA NVS Area operation region.
+ //
+#ifndef _SA_NVS_AREA_DEF_H_
+#define _SA_NVS_AREA_DEF_H_
+
+#pragma pack (push,1)
+typedef struct {
+ UINT64 Mmio64Base; ///< Offset 0 Base of
above 4GB MMIO resource
+ UINT64 Mmio64Length;///< Offset 8 Length
of above 4GB MMIO resource
+ UINT32 Mmio32Base; ///< Offset 16 Base of
below 4GB MMIO resource
+ UINT32 Mmio32Length;///< Offset 20 Length
of below 4GB MMIO resource
+} SYSTEM_AGENT_NVS_AREA;
+
+#pragma pack(pop)
+#endif
--
2.36.1.windows.1
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Re: [edk2-devel] [PATCH 4/8] AlderlakeSiliconPkg/Pch: Add libraries
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Thursday, June 15, 2023 10:53 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Oram, Isaac W ;
Chuang, Rosen
Subject: [PATCH 4/8] AlderlakeSiliconPkg/Pch: Add libraries
Adds the following libraries:
- BasePchPciBdfLib
- BaseResetSystemLib
- PeiDxeSmmPchCycleDecodingLib
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Isaac Oram
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../BasePchPciBdfLib/BasePchPciBdfLib.inf | 32 ++
.../Library/BasePchPciBdfLib/PchPciBdfLib.c | 308 ++
.../BaseResetSystemLib/BaseResetSystemLib.c | 114 +++
.../BaseResetSystemLib/BaseResetSystemLib.inf | 37 +++
.../PchCycleDecodingLib.c | 194 +++
.../PeiDxeSmmPchCycleDecodingLib.inf | 41 +++
6 files changed, 726 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf
b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf
new file mode 100644
index 00..e65f564c1b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/Bas
+++ ePchPciBdfLib.inf
@@ -0,0 +1,32 @@
+## @file
+# PCH PCIe Bus Device Function Library.
+#
+# All functions from this library are available in PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchPciBdfLib
+FILE_GUID = A36363FC-2951-4DCF-AC81-16F4ED3FDA47
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchPciBdfLib
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PciSegmentLib
+PchInfoLib
+PchPcieRpLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PchPciBdfLib.c
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfLib.c
b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfLib.c
new file mode 100644
index 00..c26625e2eb
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/Pch
+++ PciBdfLib.c
@@ -0,0 +1,308 @@
+/** @file
+ PCH PCIe Bus Device Function Library.
+ All functions from this library are available in PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ Check if a Device is present for PCH FRU
+ If the data is defined for PCH RFU return it
+ If the data is not defined (Device is NOT present) assert.
+
+ @param[in] DataToCheck Device or Function number to check
+
+ @retval Device or Function number value if defined for PCH FRU
+ 0xFF if not present in PCH FRU **/
+UINT8
+CheckAndReturn (
+ UINT8 DataToCheck
+ )
+{
+ if (DataToCheck == NOT_PRESENT) {
+ASSERT (FALSE);
+ }
+ return DataToCheck;
+}
+
+/**
+ Get P2SB PCI device number
+
+ @retval PCI dev number
+**/
+UINT8
+P2sbDevNumber (
+ VOID
+ )
+{
+ return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_P2SB); }
+
+/**
+ Get P2SB PCI function number
+
+ @retval PCI fun number
+**/
+UINT8
+P2sbFuncNumber (
+ VOID
+ )
+{
+ return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_P2SB); }
+
+/**
+ Get P2SB controller address that can be passed to the PCI Segment Library
functions.
+
+ @retval P2SB controller address in PCI Segment Library representation
+**/
+UINT64
+P2sbPciCfgBase (
+ VOID
+ )
+{
+ return PCI_SEGMENT_LIB_ADDRESS (
+ DEFAULT_PCI_SEGMENT_NUMBER_PCH,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ P2sbDevNumber (),
+ P2sbFuncNumber (),
+ 0
+ );
+}
+
+
+
+/**
+ Returns PCH SPI Device number
+
+ @retval UINT8 PCH SPI Device number
+**/
+UINT8
+SpiDevNumber (
+ VOID
+ )
+{
+ return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SPI); }
+
+/**
+ Returns PCH SPI Function number
+
+ @retval UINT8 PCH SPI Function number
+**/
+UINT8
+SpiFuncNumber (
+ VOID
+ )
+{
+ return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SPI
Re: [edk2-devel] [PATCH 3/8] AlderlakeSiliconPkg/Pch: Add include headers
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Thursday, June 15, 2023 10:53 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Oram, Isaac W ;
Chuang, Rosen
Subject: [PATCH 3/8] AlderlakeSiliconPkg/Pch: Add include headers
Adds the following header files:
* Pch/Include
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Isaac Oram
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../Include/ConfigBlock/PchGeneralConfig.h| 86
.../Pch/Include/Library/PchCycleDecodingLib.h | 59 ++
.../Pch/Include/Library/PchInfoDefs.h | 19 ++
.../Pch/Include/Library/PchInfoLib.h | 108 ++
.../Pch/Include/Library/PchPciBdfLib.h| 187 ++
.../Pch/Include/PchPolicyCommon.h | 30 +++
.../Pch/Include/PchPreMemPolicyCommon.h | 53 +
.../Pch/Include/PchResetPlatformSpecific.h| 21 ++
.../Pch/Include/Protocol/PchAcpiSmiDispatch.h | 134 +
.../Pch/Include/Protocol/PchPcieSmiDispatch.h | 166
.../Pch/Include/Protocol/PchSmiDispatch.h | 132 +
.../Include/Protocol/PchSmmIoTrapControl.h| 65 ++
.../Protocol/PchSmmPeriodicTimerControl.h | 65 ++
.../Pch/Include/Protocol/PchTcoSmiDispatch.h | 150 ++
.../Pch/Include/Protocol/SmmSmbus.h | 13 ++
.../Pch/Include/Register/PchRegs.h| 45 +
16 files changed, 1333 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchInfoDefs.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchPolicyCommon.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Register/PchRegs.h
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h
b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h
new file mode 100644
index 00..4501537fe2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGener
+++ alConfig.h
@@ -0,0 +1,86 @@
+/** @file
+ PCH General policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_GENERAL_CONFIG_H_ #define _PCH_GENERAL_CONFIG_H_
+
+
+extern EFI_GUID gPchGeneralConfigGuid;
+extern EFI_GUID gPchGeneralPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+enum PCH_RESERVED_PAGE_ROUTE {
+ PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC.
+ PchReservedPageToPcie ///< Port 80h cycles are sent to
PCIe.
+};
+
+/**
+ PCH General Configuration
+ Revision 1: - Initial version.
+ Revision 2: - Added AcpiL6dPmeHandling **/ typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+This member describes whether or not the Compatibility Revision ID (CRID)
feature
+of PCH should be enabled. 0: Disable; 1: Enable
+ **/
+ UINT32Crid: 1;
+ /**
+Set to enable low latency of legacy IO.
+Some systems require lower IO latency irrespective of power.
+This is a tradeoff between power and IO latency.
+@note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent
+and ITSS Clock Gating are forced to disabled.
+0: Disable, 1: Enable
+ **/
+ UINT32LegacyIoLowLatency : 1;
+ /**
+ Enables _L6D ACPI handler.
+ PME GPE is shared by multiple devices So BIOS must verify the same in
+the ASL handler by reading offset for PMEENABLE and PMESTATUS bit
+ 0: Disable, 1: Enable
+ **/
+ UINT32AcpiL6dPmeHandling : 1;
+ UINT32RsvdBits0 : 29; ///< Reserved bits
+} PCH_GENERAL_CONFIG;
+
+/**
+ PCH
Re: [edk2-devel] [PATCH 1/8] AlderlakeSiliconPkg: Add package and library instances
Looks good. One feedback though, in PeiDxeSmmReserveMmioSizeLib.inf. The file comments states that the functions in the library are available for PEI, DXE and SMM only. Yet, MODULE_TYPE is set to BASE, which contradicts the above the line. >From the .inf specification, we have the following guideline around MODULE_TYPE MODULE_TYPE This is the type of module. One of the EDK II Module Types. For Library Modules, the MODULE_TYPE must specify the MODULE_TYPE of the module that will typically use the library. As such, I think MODULE_TYPE for the library .inf should be set to PEIM, instead of BASE. With that, Reviewed-by: Sai Chaganty Regards, Sai -Original Message- From: Kasbekar, Saloni Sent: Thursday, June 15, 2023 10:53 AM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Oram, Isaac W ; Chuang, Rosen Subject: [PATCH 1/8] AlderlakeSiliconPkg: Add package and library instances Create the AlderlakeSiliconPkg to provide an initial package for silicon initialization code for Alder Lake (ADL) products. Add the following libraries - - BasePciSegmentMultiSegLibPci - BaseSiConfigBlockLib - PeiDxeSmmReserveMmio64SizeLib - PeiPostMemSiliconPolicyInitLib Cc: Sai Chaganty Cc: Nate DeSimone Cc: Isaac Oram Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../BasePciSegmentMultiSegLibPci.inf | 37 ++ .../BasePciSegmentMultiSegLibPci.uni | 14 + .../PciSegmentLib.c | 597 ++ .../BaseSiConfigBlockLib.c| 87 +++ .../BaseSiConfigBlockLib.inf | 32 + .../PeiDxeSmmReserveMmio64SizeLib.c | 22 + .../PeiDxeSmmReserveMmio64SizeLib.inf | 28 + .../PeiPostMemSiliconPolicyInitLib.c | 94 +++ .../PeiPostMemSiliconPolicyInitLib.inf| 39 ++ .../PeiPreMemSiliconPolicyInitLib.c | 98 +++ .../PeiPreMemSiliconPolicyInitLib.inf | 36 ++ 11 files changed, 1084 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.uni create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/PciSegmentLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/PeiDxeSmmReserveMmio64SizeLib/PeiDxeSmmReserveMmio64SizeLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/PeiDxeSmmReserveMmio64SizeLib/PeiDxeSmmReserveMmio64SizeLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPostMemSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPostMemSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPreMemSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPreMemSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf b/Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf new file mode 100644 index 00..f3764d0187 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmentMultiSegLi +++ bPci/BasePciSegmentMultiSegLibPci.inf @@ -0,0 +1,37 @@ +## @file +# Instance of PCI Segment Library based on PCI Library. +# +# PCI Segment Library that layers on top of the PCI Library which only +# supports segment 0 and segment 1 PCI configuration access. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION= 0x00010005 + BASE_NAME = BasePciSegmentMultiSegLibPci + MODULE_UNI_FILE= BasePciSegmentMultiSegLibPci.uni + FILE_GUID = AC65B409-DF03-466e-8D2B-6FCE1079F0B2 + MODULE_TYPE= BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciSegmentLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources] + PciSegmentLib.c + +[Packages] + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + +[LibraryClasses] + BaseLib + PciLib + DebugLib + PcdLib diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.uni b/Silicon/Intel/AlderlakeSiliconPkg/Libr
Re: [edk2-devel] [PATCH] [IntelFsp2Pkg]: Fix GCC Compiler warning
Reviewed-by: Sai Chaganty -Original Message- From: S, Ashraf Ali Sent: Thursday, March 09, 2023 8:06 AM To: devel@edk2.groups.io Cc: S, Ashraf Ali ; Chiu, Chasel ; Desimone, Nathaniel L ; Chaganty, Rangasai V ; Zeng, Star Subject: [PATCH] [IntelFsp2Pkg]: Fix GCC Compiler warning Function defination should match with declaration. [-Wlto-type-mismatch] Cc: Chasel Chiu Cc: Nate DeSimone Cc: Sai Chaganty Cc: Star Zeng Signed-off-by: Ashraf Ali S --- IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c | 1 + 1 file changed, 1 insertion(+) diff --git a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c index 795bb28c0f..a5a51c804c 100644 --- a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c +++ b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c @@ -296,6 +296,7 @@ FspTempRamExitDone2 ( **/ VOID +EFIAPI FspWaitForNotify ( VOID ) -- 2.38.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100967): https://edk2.groups.io/g/devel/message/100967 Mute This Topic: https://groups.io/mt/97499164/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][edk2-platforms][PATCH V1 1/1] Features/Intel: Prepare for edk2-platforms CI
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Monday, January 09, 2023 4:05 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Gao, Liming ; Dong, Eric ; Bi, Dandan Subject: [edk2-devel][edk2-platforms][PATCH V1 1/1] Features/Intel: Prepare for edk2-platforms CI Fix some build issues with GCC5 targets Add a Readme.md for AdvancedFeaturePkg Add VS2019, CLANGPDB, and GCC5 build targets to Readme.md for each feature Cc: Sai Chaganty Cc: Nate DeSimone Cc: Liming Gao Cc: Eric Dong Cc: Dandan Bi Signed-off-by: Isaac Oram --- .../AdvancedFeaturePkg/AdvancedFeaturePkg.dsc | 6 ++- Features/Intel/AdvancedFeaturePkg/Readme.md | 38 +++ .../AcpiDebugFeaturePkg.dsc | 3 ++ .../Debugging/AcpiDebugFeaturePkg/Readme.md | 9 ++--- .../Debugging/BeepDebugFeaturePkg/Readme.md | 6 +++ .../PostCodeDebugFeaturePkg/Readme.md | 5 ++- .../Debugging/Usb3DebugFeaturePkg/Readme.md | 9 ++--- .../Intel/Network/NetworkFeaturePkg/Readme.md | 9 ++--- .../AsfFeaturePkg/Readme.md | 5 ++- .../GenericIpmi/Common/IpmiHooks.c| 2 + .../GenericIpmi/Common/IpmiHooks.h| 2 + .../GenericIpmi/Dxe/GenericIpmi.c | 2 +- .../Library/IpmiBaseLib/IpmiBaseLib.c | 2 +- .../IpmiFeaturePkg/Readme.md | 9 ++--- .../SpcrFeaturePkg/Readme.md | 5 ++- .../Library/PcdInitLib/PcdInitLib.c | 2 +- .../PowerManagement/S3FeaturePkg/Readme.md| 9 ++--- .../SmbiosFeaturePkg/Readme.md| 9 ++--- Features/Intel/TemplateFeaturePkg/Readme.md | 9 - .../UserInterface/LogoFeaturePkg/Readme.md| 6 ++- .../UserAuthFeaturePkg/Readme.md | 9 ++--- .../VirtualKeyboardFeaturePkg/Readme.md | 5 ++- .../VirtualKeyboardFeaturePkg.dsc | 4 ++ 23 files changed, 119 insertions(+), 46 deletions(-) create mode 100644 Features/Intel/AdvancedFeaturePkg/Readme.md diff --git a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc b/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc index 18929589c5..226d41522d 100644 --- a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc +++ b/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc @@ -25,7 +25,7 @@ DSC_SPECIFICATION = 0x00010005 OUTPUT_DIRECTORY= Build/AdvancedFeaturePkg SUPPORTED_ARCHITECTURES = IA32|X64 - BUILD_TARGETS = DEBUG|RELEASE + BUILD_TARGETS = DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER= DEFAULT PEI_ARCH= IA32 DXE_ARCH= X64 @@ -95,6 +95,10 @@ [PcdsFixedAtBuild] gUsb3DebugFeaturePkgTokenSpaceGuid.PcdUsb3DebugPortLibInstance|1 +[PcdsDynamicExDefault.X64] + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow + # # MinPlatform common include for required feature PCD # These PCD must be set before the core include files, CoreCommonLib, diff --git a/Features/Intel/AdvancedFeaturePkg/Readme.md b/Features/Intel/AdvancedFeaturePkg/Readme.md new file mode 100644 index 00..ba50560328 --- /dev/null +++ b/Features/Intel/AdvancedFeaturePkg/Readme.md @@ -0,0 +1,38 @@ +# Overview +Build all advanced features for testing build and integration. + +Please refer to individual feature packages for details on intended uses. + +# High-Level Theory of Operation +Enable all features and build a reasonable default configuration. This is not expected to produce binaries that are directly usable in a product as features may require board or silicon specific configuration and libraries. + +## Firmware Volumes +Produces: +* FvAdvancedPreMemory +* FvAdvancedUncompressed +* FvAdvanced + +## Build +Supported build targets +* VS2019 +* CLANGPDB +* GCC5 + +## Windows Example: +With current working directory at O:\ + +git clone https://github.com/tianocore/edk2.git + +git clone https://github.com/tianocore/edk2-platforms.git + +set workspace=O:\ + +set EDK_TOOLS_PATH=O:\Edk2\BaseTools + +set +packages_path=O:\edk2;O:\edk2-non-osi;O:\edk2-platforms\Platform\Intel; +O:\edk2-platforms\Silicon\Intel;O:\edk2-platforms\Platform\Qemu;O:\edk2 +-platforms\Silicon\Qemu;O:\edk2-platforms\Features\Intel;O:\edk2-platfo +rms\Features\Intel\Debugging;O:\edk2-platforms\Features\Intel\Network;O +:\edk2-platforms\Features\Intel\OutOfBandManagement;O:\edk2-platforms\F +eatures\Intel\PowerManagement;O:\edk2-platforms\Features\Intel\SystemIn +formation;O:\edk2-platforms\Features\Intel\UserInterface + +cd \edk2 + +edksetup.bat Rebuild + +build -a IA32 -a X64 -t CLANGPDB -b NOOPT -p +AdvancedFeaturePkg\AdvancedFeaturePkg.dsc diff --git a/Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugFeaturePkg.dsc b/Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugFeaturePkg.dsc index
Re: [edk2-devel] [Patch edk2-platforms] IntelSiliconPkg/IntelVTdDxe: Fix CLANG detected incorrect return
Reviewed-by: Sai Chaganty
-Original Message-
From: Kinney, Michael D
Sent: Thursday, November 10, 2022 10:24 AM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V
; Oram, Isaac W ; S,
Ashraf Ali
Subject: [Patch edk2-platforms] IntelSiliconPkg/IntelVTdDxe: Fix CLANG detected
incorrect return
CreateSecondLevelPagingEntryTable() has a return type of
VTD_SECOND_LEVEL_PAGING_ENTRY * and an error condition returns a value of NULL.
Change return value of EFI_SUCCESS (value 0) to NULL to address CLANG compiler
detection of incorrect return type.
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Isaac Oram
Cc: Ashraf Ali S
Signed-off-by: Michael D Kinney
---
.../IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index 3220789080..6788c86531 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationT
+++ able.c
@@ -196,7 +196,7 @@ CreateSecondLevelPagingEntryTable (
UINT64 EndAddress;
if (MemoryLimit == 0) {
-return EFI_SUCCESS;
+return NULL;
}
Lvl4PagesStart = 0;
--
2.37.1.windows.1
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Re: [edk2-devel] [edk2-platforms][PATCH v1 2/3] TigerLakeOpenBoardPkg: Remove unnecessary debug macro argument
Reviewed-by: Sai Chaganty
-Original Message-
From: mikub...@linux.microsoft.com
Sent: Tuesday, October 04, 2022 8:36 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Desimone, Nathaniel L
; Luo, Heng ; Oram, Isaac W
Subject: [edk2-platforms][PATCH v1 2/3] TigerLakeOpenBoardPkg: Remove
unnecessary debug macro argument
From: Michael Kubacki
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4094
Removes an argument passed to a debug macro without a print specifier. The
argument appears to be useless.
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Heng Luo
Cc: Isaac Oram
Signed-off-by: Michael Kubacki
---
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c
| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c
b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c
index f0eb3f3f141f..f31cec231e8c 100644
---
a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMe
+++ mDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c
@@ -32,7 +32,7 @@ PeiSiPreMemDefaultPolicyInitLibConstructor (
if (PeiPreMemSiDefaultPolicyInitPpi == NULL) {
return Status;
}
- DEBUG ((DEBUG_INFO, "PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit
()\n", Status));
+ DEBUG ((DEBUG_INFO,
+ "PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit ()\n"));
Status = PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit ();
ASSERT_EFI_ERROR (Status);
--
2.28.0.windows.1
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Re: [edk2-devel] [edk2-platforms][PATCH V2 1/3] MinPlatformPkg/Include: Add PEI DevicePathLib instance
Reviewed-by: Sai Chaganty < rangasai.v.chaga...@intel.com > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93665): https://edk2.groups.io/g/devel/message/93665 Mute This Topic: https://groups.io/mt/93605308/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][edk2-platforms][PATCH V2 2/3] PlatformPayloadFeaturePkg/Build: Use MinPlatform PCD include
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Saturday, September 10, 2022 6:52 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Chaganty, Rangasai V ; Desimone, Nathaniel L Subject: [edk2-devel][edk2-platforms][PATCH V2 2/3] PlatformPayloadFeaturePkg/Build: Use MinPlatform PCD include Fix build issue from removed PCD and use MinPlatformFeaturesPcd.dsc.inc. Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Isaac Oram --- .../PlatformPayloadFeaturePkg.dsc | 13 + 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/Features/Intel/PlatformPayloadFeaturePkg/PlatformPayloadFeaturePkg.dsc b/Features/Intel/PlatformPayloadFeaturePkg/PlatformPayloadFeaturePkg.dsc index 1b79e0039b..e36e5d6e1e 100644 --- a/Features/Intel/PlatformPayloadFeaturePkg/PlatformPayloadFeaturePkg.dsc +++ b/Features/Intel/PlatformPayloadFeaturePkg/PlatformPayloadFeaturePkg +++ .dsc @@ -48,16 +48,13 @@ # -# -# Since there are no 32b libraries or components in this package, these PCD are specified for 64b only -# -[PcdsFeatureFlag] # - # PCD needed for MinPlatform build includes + # MinPlatform common include for required feature PCD # These PCD + must be set before the core include files, CoreCommonLib, # + CorePeiLib, and CoreDxeLib. + # Optional MinPlatformPkg features should be enabled after this # - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable |FALSE - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable |FALSE + !include MinPlatformPkg/Include/Dsc/MinPlatformFeaturesPcd.dsc.inc [PcdsPatchableInModule] gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x7 -- 2.36.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93631): https://edk2.groups.io/g/devel/message/93631 Mute This Topic: https://groups.io/mt/93605310/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][edk2-platforms][PATCH V2 3/3] Platform/Intel: Fix missing package issue
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Saturday, September 10, 2022 6:52 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Chaganty, Rangasai V ; Desimone, Nathaniel L Subject: [edk2-devel][edk2-platforms][PATCH V2 3/3] Platform/Intel: Fix missing package issue Update all consumers of PcdAcpiBaseAddress to include IntelSiliconPkg/IntelSiliconPkg.dec. Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Isaac Oram --- .../CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +- .../KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf| 1 + .../Library/BasePlatformHookLib/BasePlatformHookLib.inf | 1 + .../Library/BasePlatformHookLib/BasePlatformHookLib.inf | 1 + .../WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +- 5 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf index c4dd863c3e..9f6d43172f 100644 --- a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf +++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtS +++ mm.inf @@ -41,6 +41,7 @@ MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec MinPlatformPkg/MinPlatformPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec CometlakeOpenBoardPkg/OpenBoardPkg.dec CoffeelakeSiliconPkg/SiPkg.dec @@ -77,4 +78,3 @@ gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuidAND gEfiSmmVariableProtocolGuid - diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf index 13116488ea..8d932ed094 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSm +++ m.inf @@ -39,6 +39,7 @@ MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec MinPlatformPkg/MinPlatformPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec KabylakeOpenBoardPkg/OpenBoardPkg.dec KabylakeSiliconPkg/SiPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf index 5f65f02a9f..e30ca0c438 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatfor +++ mHookLib/BasePlatformHookLib.inf @@ -31,6 +31,7 @@ MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec MinPlatformPkg/MinPlatformPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec KabylakeOpenBoardPkg/OpenBoardPkg.dec KabylakeSiliconPkg/SiPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf index 8bdf13b1ce..ba73140a6b 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatf +++ ormHookLib/BasePlatformHookLib.inf @@ -31,6 +31,7 @@ MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec MinPlatformPkg/MinPlatformPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec KabylakeOpenBoardPkg/OpenBoardPkg.dec KabylakeSiliconPkg/SiPkg.dec diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf index 83ebc790ae..c3ba13c037 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/Tb +++ tSmm.inf @@ -41,6 +41,7 @@ MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec MinPlatformPkg/MinPlatformPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec CoffeelakeSiliconPkg/SiPkg.dec @@ -77,4 +78,3 @@ gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuidAND gEfiSmmVariableProtocolGuid - -- 2.36.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93630): https://edk2.groups.io/g/devel/message/93630 Mute This Topic: https://groups.io/mt/93605309/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition
Reviewed-by: Sai Chaganty
-Original Message-
From: Benjamin Doron
Sent: Tuesday, September 06, 2022 10:02 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Oram, Isaac W
; Desimone, Nathaniel L
; Sinha, Ankit ; Ni, Ray
; Chiu, Chasel ; Luo, Heng
Subject: [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel:
Move PcdAcpiBaseAddress definition
All these platforms have an ABase, so move the definition to enable common
silicon code in IntelSiliconPkg. Otherwise, library shims would be required,
because PCDs are GUID-ed and package DEC specific.
Cc: Rangasai V Chaganty
Cc: Isaac Oram
Cc: Nate DeSimone
Cc: Ankit Sinha
Cc: Ray Ni
Cc: Chasel Chiu
Cc: Sai Chaganty
Cc: Heng Luo
Signed-off-by: Benjamin Doron
---
.../CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc | 1 +
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc| 1 +
.../KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../Library/BasePlatformHookLib/BasePlatformHookLib.inf | 2 +-
.../KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc | 1 +
.../Library/BasePlatformHookLib/BasePlatformHookLib.inf | 2 +-
.../KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc| 1 +
.../TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc | 1 +
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 1 +
.../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 1 +
Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc | 1 +
.../Library/PeiSiliconInitLib/PeiSiliconInitLib.inf | 5 +++--
.../Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 3 ++-
.../PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf | 2 +-
Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec | 1 -
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec| 4
Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc | 1 +
.../Library/PeiSiliconInitLib/PeiSiliconInitLib.inf | 2 +-
.../Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf| 3 ++-
.../Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf | 2 +-
.../KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf | 2 +-
Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 1 -
.../IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 3 ++-
.../PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf| 3 ++-
Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec | 1 -
Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc| 1 +
28 files changed, 34 insertions(+), 18 deletions(-)
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
index 79924f1fda7f..81dc0747fab8 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd
+++ .dsc
@@ -65,6 +65,7 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE000
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x1000+
gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 # # PCIe Reserved
Memory Space Range #diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index e3fdd3981653..c4dd863c3ee8 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtS
+++ mm.inf
@@ -49,7 +49,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES
[FixedPcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+
gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress## CONSUMES
[Sources] TbtSmiHandler.hdiff --git
a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
index a4ea524e26bc..3ed7aa0a2b10 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg
+++ Pcd.dsc
@@ -241,6 +241,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 !endif
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE000+
gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01diff --git
a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index e6c185a4bd91..13116488eaa0 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b
Re: [edk2-devel][edk2-platforms][PATCH v1 2/5] Silicon/Intel: Port SmmControl protocol to PPI for S3
Yes. PcdAcpiBaseAddress declaration can be moved to IntelSiliconPkg.dec Regards, Sai From: Oram, Isaac W Sent: Tuesday, August 30, 2022 11:40 AM To: devel@edk2.groups.io; benjamin.doro...@gmail.com; Chaganty, Rangasai V Cc: Desimone, Nathaniel L ; Sinha, Ankit ; Ni, Ray Subject: RE: [edk2-devel][edk2-platforms][PATCH v1 2/5] Silicon/Intel: Port SmmControl protocol to PPI for S3 @Chaganty, Rangasai V<mailto:rangasai.v.chaga...@intel.com> Is it fair to say that the build time address for ACPI BAR is the cross silicon design? I think it is and therefore we should move the PCD to IntelSiliconPkg. I agree with Benjamin that we don’t really want features depending on specific silicon packages. We want API definitions in IntelSiliconPkg. Regards, Isaac From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> mailto:devel@edk2.groups.io>> On Behalf Of Benjamin Doron Sent: Monday, August 29, 2022 5:58 PM To: Oram, Isaac W mailto:isaac.w.o...@intel.com>> Cc: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Desimone, Nathaniel L mailto:nathaniel.l.desim...@intel.com>>; Sinha, Ankit mailto:ankit.si...@intel.com>>; Ni, Ray mailto:ray...@intel.com>>; Chaganty, Rangasai V mailto:rangasai.v.chaga...@intel.com>> Subject: Re: [edk2-devel][edk2-platforms][PATCH v1 2/5] Silicon/Intel: Port SmmControl protocol to PPI for S3 Right, but Kabylake has a different implementation that retrieves it from HW registers - PchAcpiBaseGet(). This is probably optional, there is a PCD, but it's in a different package scope. I don't know how to handle the Packages in the INF to keep this silicon package agnostic. For that matter, it might not really be a CFL plus shim, because Tigerlake, etc are different package DECs too. Best regards, Benjamin On Mon, 29 Aug 2022 at 19:17, Oram, Isaac W mailto:isaac.w.o...@intel.com>> wrote: I think that the shim lib might be overkill. PmcGetAcpiBase just resolves to PcdGet16 (PcdAcpiBaseAddress); I think that you should be able to use that PCD for any Intel chipset/silicon for the foreseeable future. I would prefer to see contents of sections in INF files indented, but it is a nit. Regards, Isaac -Original Message- From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> mailto:devel@edk2.groups.io>> On Behalf Of Benjamin Doron Sent: Monday, August 29, 2022 1:36 PM To: devel@edk2.groups.io<mailto:devel@edk2.groups.io> Cc: Desimone, Nathaniel L mailto:nathaniel.l.desim...@intel.com>>; Sinha, Ankit mailto:ankit.si...@intel.com>>; Ni, Ray mailto:ray...@intel.com>>; Chaganty, Rangasai V mailto:rangasai.v.chaga...@intel.com>>; Oram, Isaac W mailto:isaac.w.o...@intel.com>> Subject: [edk2-devel][edk2-platforms][PATCH v1 2/5] Silicon/Intel: Port SmmControl protocol to PPI for S3 S3 resume may require communication with SMM, for which we need the SmmControl PPI. Therefore, port the DXE drivers to a library, like there is for SMM Access. As the registers are common across Intel platforms in the tree, while a helper function definition is not, implement a new library as a compatibility shim. Tested, working on Kabylake. Further testing required after the refactor for compatibility. Cc: Nate DeSimone mailto:nathaniel.l.desim...@intel.com>> Cc: Ankit Sinha mailto:ankit.si...@intel.com>> Cc: Ray Ni mailto:ray...@intel.com>> Cc: Rangasai V Chaganty mailto:rangasai.v.chaga...@intel.com>> Cc: Isaac Oram mailto:isaac.w.o...@intel.com>> Signed-off-by: Benjamin Doron mailto:benjamin.doro...@gmail.com>> --- .../BaseIntelCompatShimLibCfl.c | 24 ++ .../BaseIntelCompatShimLibCfl.inf | 24 ++ .../PeiSmmControlLib/PeiSmmControlLib.c | 309 ++ .../PeiSmmControlLib/PeiSmmControlLib.inf | 36 ++ .../Include/Library/IntelCompatShimLib.h | 20 ++ .../Include/Library/SmmControlLib.h | 26 ++ .../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 4 + .../BaseIntelCompatShimLibKbl.c | 29 ++ .../BaseIntelCompatShimLibKbl.inf | 24 ++ 9 files changed, 496 insertions(+) create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.c create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/IntelCompatShimLib.h create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl.c create mode 100644 Si
Re: [edk2-devel] [PATCH V2] Maintainers.txt: Update reviewers for IntelSiliconPkg
Reviewed-by: Sai Chaganty -Original Message- From: S, Ashraf Ali Sent: Tuesday, August 23, 2022 12:27 AM To: devel@edk2.groups.io Cc: S, Ashraf Ali ; Ni, Ray ; Chaganty, Rangasai V ; Oram, Isaac W Subject: [PATCH V2] Maintainers.txt: Update reviewers for IntelSiliconPkg Add Ashraf Ali S as IntelSiliconPkg reviewers Signed-off-by: Ashraf Ali S Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Isaac Oram --- Maintainers.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Maintainers.txt b/Maintainers.txt index 5e403ce851..3fe5dc21a8 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -277,6 +277,7 @@ F: Silicon/Intel/IntelSiliconPkg/ M: Ray Ni M: Rangasai V Chaganty M: Isaac Oram +R: Ashraf Ali S Silicon/Intel/QuarkSocPkg F: Silicon/Intel/QuarkSocPkg/ -- 2.30.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92680): https://edk2.groups.io/g/devel/message/92680 Mute This Topic: https://groups.io/mt/93199674/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][edk2-platforms][PATCH V1 3/3] PlatformPayloadFeaturePkg: Update contents to match feature conventions
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Wednesday, August 10, 2022 3:47 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Gao, Liming ; Ni, Ray ; Dong, Guo Subject: [edk2-devel][edk2-platforms][PATCH V1 3/3] PlatformPayloadFeaturePkg: Update contents to match feature conventions Rename gPlatformPayloadPkgTokenSpaceGuid to gPlatformPayloadFeaturePkgTokenSpaceGuid Rename PcdPayloadPackageFeatureEnable to PcdPlatformPayloadFeatureEnable Update Readme including format improvements Cc: Sai Chaganty Cc: Nate DeSimone Cc: Liming Gao Cc: Ray Ni Cc: Guo Dong Signed-off-by: Isaac Oram --- .../AdvancedFeaturePkg/AdvancedFeaturePkg.dsc | 2 +- .../Include/AdvancedFeatures.dsc | 2 +- .../Include/AdvancedFeaturesPcd.dsc | 2 +- .../AdvancedFeaturePkg/Include/PostMemory.fdf | 2 +- .../AdvancedFeaturePkg/Include/PreMemory.fdf | 2 +- .../PlatformPayloadFeaturePkg/Fvb/FvbSmm.inf | 2 +- .../PlatformPayloadFeaturePkg.dec | 6 +- .../Intel/PlatformPayloadFeaturePkg/Readme.md | 73 ++- 8 files changed, 48 insertions(+), 43 deletions(-) diff --git a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc b/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc index df8e678ae8..236c5570ca 100644 --- a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc +++ b/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc @@ -84,7 +84,7 @@ # # Individual features # - gPlatformPayloadPkgTokenSpaceGuid.PcdPayloadPackageFeatureEnable |TRUE + + gPlatformPayloadFeaturePkgTokenSpaceGuid.PcdPlatformPayloadFeatureEnab + le |TRUE # # PCD that are required to be set by the build target should be configured here for test purposes diff --git a/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeatures.dsc b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeatures.dsc index 6a80546592..804aab89bc 100644 --- a/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeatures.dsc +++ b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeatures.dsc @@ -79,6 +79,6 @@ # # Individual features # -!if gPlatformPayloadPkgTokenSpaceGuid.PcdPayloadPackageFeatureEnable == TRUE +!if +gPlatformPayloadFeaturePkgTokenSpaceGuid.PcdPlatformPayloadFeatureEnabl +e == TRUE !include PlatformPayloadFeaturePkg/Include/PlatformPayloadFeature.dsc !endif diff --git a/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc index 08f258a48c..0af5a8bfbc 100644 --- a/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc +++ b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc @@ -82,7 +82,7 @@ gUserAuthFeaturePkgTokenSpaceGuid.PcdUserAuthenticationFeatureEnable |FALSE gVirtualKeyboardFeaturePkgTokenSpaceGuid.PcdVirtualKeyboardFeatureEnable |FALSE - gPlatformPayloadPkgTokenSpaceGuid.PcdPayloadPackageFeatureEnable |FALSE + + gPlatformPayloadFeaturePkgTokenSpaceGuid.PcdPlatformPayloadFeatureEnab + le |FALSE # # There seems to be some build parsing odd behavior that requires this PCD to be specified even though diff --git a/Features/Intel/AdvancedFeaturePkg/Include/PostMemory.fdf b/Features/Intel/AdvancedFeaturePkg/Include/PostMemory.fdf index 66032ba117..349bdcc491 100644 --- a/Features/Intel/AdvancedFeaturePkg/Include/PostMemory.fdf +++ b/Features/Intel/AdvancedFeaturePkg/Include/PostMemory.fdf @@ -80,6 +80,6 @@ # # Individual features # -!if gPlatformPayloadPkgTokenSpaceGuid.PcdPayloadPackageFeatureEnable == TRUE +!if +gPlatformPayloadFeaturePkgTokenSpaceGuid.PcdPlatformPayloadFeatureEnabl +e == TRUE !include PlatformPayloadFeaturePkg/Include/PostMemory.fdf !endif diff --git a/Features/Intel/AdvancedFeaturePkg/Include/PreMemory.fdf b/Features/Intel/AdvancedFeaturePkg/Include/PreMemory.fdf index 9cd6de833b..b991a5aabf 100644 --- a/Features/Intel/AdvancedFeaturePkg/Include/PreMemory.fdf +++ b/Features/Intel/AdvancedFeaturePkg/Include/PreMemory.fdf @@ -80,6 +80,6 @@ # # Individual features # -!if gPlatformPayloadPkgTokenSpaceGuid.PcdPayloadPackageFeatureEnable == TRUE +!if +gPlatformPayloadFeaturePkgTokenSpaceGuid.PcdPlatformPayloadFeatureEnabl +e == TRUE !include PlatformPayloadFeaturePkg/Include/PreMemory.fdf !endif diff --git a/Features/Intel/PlatformPayloadFeaturePkg/Fvb/FvbSmm.inf b/Features/Intel/PlatformPayloadFeaturePkg/Fvb/FvbSmm.inf index f973465cba..a692d9bf41 100644 --- a/Features/Intel/PlatformPayloadFeaturePkg/Fvb/FvbSmm.inf +++ b/Features/Intel/PlatformPayloadFeaturePkg/Fvb/FvbSmm.inf @@ -60,7 +60,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize - gPlatformPayloadPkgTokenSpaceGuid.PcdNvsDataFile + gPlatformPayloadFeaturePkgTokenSpaceGuid.PcdNvsDataFile
Re: [edk2-devel][edk2-platforms][PATCH V1 2/3] PlatformPayloadPkg: Rename to match other feature conventions
Reviewed-by: Sai Chaganty
-Original Message-
From: Oram, Isaac W
Sent: Wednesday, August 10, 2022 3:47 PM
To: devel@edk2.groups.io
Cc: Oram, Isaac W ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Gao, Liming ; Ni,
Ray ; Dong, Guo
Subject: [edk2-devel][edk2-platforms][PATCH V1 2/3] PlatformPayloadPkg: Rename
to match other feature conventions
Rename PlatformPayloadPkg to PlatformPayloadFeaturePkg.
Rename Package DEC, DSC, FDF and py scripts to match.
Search and replace PlatformPayloadPkg with PlatformPayloadFeaturePkg.
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Liming Gao
Cc: Ray Ni
Cc: Guo Dong
Signed-off-by: Isaac Oram
---
.../Include/AdvancedFeatures.dsc | 2 +-
.../Include/AdvancedFeaturesPcd.dsc| 2 +-
.../AdvancedFeaturePkg/Include/PostMemory.fdf | 2 +-
.../Intel/AdvancedFeaturePkg/Include/PreMemory.fdf | 2 +-
.../Fvb/FvbInfo.c | 0
.../Fvb/FvbService.c | 0
.../Fvb/FvbService.h | 0
.../Fvb/FvbServiceSmm.c| 0
.../Fvb/FvbSmm.inf | 2 +-
.../Fvb/FvbSmmCommon.h | 0
.../Include/Guid/NvVariableInfoGuid.h | 0
.../Include/Guid/SpiFlashInfoGuid.h| 0
.../Include/Library/FlashDeviceLib.h | 0
.../Include/Library/SpiFlashLib.h | 0
.../Include/PlatformPayloadFeature.dsc | 14 +++---
.../Include/PostMemory.fdf | 4 ++--
.../Include/PreMemory.fdf | 0
.../Library/FlashDeviceLib/FlashDeviceLib.c| 0
.../Library/FlashDeviceLib/FlashDeviceLib.inf | 3 +--
.../Library/PcdInitLib/PcdInitLib.c| 0
.../Library/PcdInitLib/PcdInitLib.inf | 3 +--
.../Library/SpiFlashLib/PchSpi.c | 0
.../Library/SpiFlashLib/RegsSpi.h | 0
.../Library/SpiFlashLib/SpiCommon.h| 0
.../Library/SpiFlashLib/SpiFlashLib.c | 0
.../Library/SpiFlashLib/SpiFlashLib.inf| 2 +-
.../PchSmiDispatchSmm/PchSmiDispatchSmm.c | 0
.../PchSmiDispatchSmm/PchSmiDispatchSmm.h | 0
.../PchSmiDispatchSmm/PchSmiDispatchSmm.inf| 0
.../PlatformPayloadFeaturePkg.dec} | 2 +-
.../PlatformPayloadFeaturePkg.dsc} | 4 ++--
.../PlatformPayloadFeaturePkg.fdf} | 0
.../PlatformPayloadFeaturePkg.py} | 4 ++--
.../Readme.md | 9 -
34 files changed, 26 insertions(+), 29 deletions(-) rename
Features/Intel/{PlatformPayloadPkg => PlatformPayloadFeaturePkg}/Fvb/FvbInfo.c
(100%) rename Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Fvb/FvbService.c (100%) rename
Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Fvb/FvbService.h (100%) rename
Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Fvb/FvbServiceSmm.c (100%) rename
Features/Intel/{PlatformPayloadPkg => PlatformPayloadFeaturePkg}/Fvb/FvbSmm.inf
(92%) rename Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Fvb/FvbSmmCommon.h (100%) rename
Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Include/Guid/NvVariableInfoGuid.h (100%) rename
Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Include/Guid/SpiFlashInfoGuid.h (100%) rename
Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Include/Library/FlashDeviceLib.h (100%) rename
Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Include/Library/SpiFlashLib.h (100%) rename
Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Include/PlatformPayloadFeature.dsc (87%) rename
Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Include/PostMemory.fdf (77%) rename
Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Include/PreMemory.fdf (100%) rename
Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Library/FlashDeviceLib/FlashDeviceLib.c (100%)
rename Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Library/FlashDeviceLib/FlashDeviceLib.inf (90%)
rename Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Library/PcdInitLib/PcdInitLib.c (100%) rename
Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Library/PcdInitLib/PcdInitLib.inf (92%) rename
Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Library/SpiFlashLib/PchSpi.c (100%) rename
Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Library/SpiFlashLib/RegsSpi.h (100%) rename
Features/Intel/{PlatformPayloadPkg =>
PlatformPayloadFeaturePkg}/Library/SpiFlashLib/SpiCommon.h (100%) rename
Features/Intel/{PlatformP
Re: [edk2-devel][edk2-platforms][PATCH V1 1/3] PlatformPayloadPkg: Fix AdvancedFeaturePkg build issue
Small cosmetic feedback. There is an (unnecessary) open "(" in line 145. Please
remove it before checking in.
# (Optional for variable modules debug output
With that:
Reviewed-by: Sai Chaganty
-Original Message-
From: Oram, Isaac W
Sent: Wednesday, August 10, 2022 3:47 PM
To: devel@edk2.groups.io
Cc: Oram, Isaac W ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Gao, Liming ; Ni,
Ray ; Dong, Guo
Subject: [edk2-devel][edk2-platforms][PATCH V1 1/3] PlatformPayloadPkg: Fix
AdvancedFeaturePkg build issue
Feature packages should build with -a IA32 -a X64.
The commonly board selected libraries were moved to the PlatformPayloadPkg
build so as not to conflict with other advanced features.
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Liming Gao
Cc: Ray Ni
Cc: Guo Dong
Signed-off-by: Isaac Oram
---
.../Include/PlatformPayloadFeature.dsc| 42 +--
.../PlatformPayloadPkg/PlatformPayloadPkg.dsc | 26 +++-
2 files changed, 46 insertions(+), 22 deletions(-)
diff --git
a/Features/Intel/PlatformPayloadPkg/Include/PlatformPayloadFeature.dsc
b/Features/Intel/PlatformPayloadPkg/Include/PlatformPayloadFeature.dsc
index 3003c563c9..bc776659b6 100644
--- a/Features/Intel/PlatformPayloadPkg/Include/PlatformPayloadFeature.dsc
+++ b/Features/Intel/PlatformPayloadPkg/Include/PlatformPayloadFeature.d
+++ sc
@@ -19,7 +19,9 @@
!error "DXE_ARCH must be specified to build this feature!"
!endif
- DEFINE SMM_VARIABLE = TRUE
+ !ifndef SMM_VARIABLE
+DEFINE SMM_VARIABLE = TRUE
+ !endif
@@ -28,7 +30,7 @@
#
-[PcdsPatchableInModule.X64]
+[PcdsPatchableInModule]
!if $(SMM_VARIABLE) == TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0
@@ -45,24 +47,11 @@
#
-[LibraryClasses]
- !if $(SMM_VARIABLE) == TRUE
-PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
-PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
-# (Optional for variable modules debug output
-PlatformHookLib|UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
-
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
-PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
-DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
- !endif
-
[LibraryClasses.common.DXE_SMM_DRIVER,LibraryClasses.common.DXE_RUNTIME_DRIVER]
!if $(SMM_VARIABLE) == TRUE
SpiFlashLib|PlatformPayloadPkg/Library/SpiFlashLib/SpiFlashLib.inf
FlashDeviceLib|PlatformPayloadPkg/Library/FlashDeviceLib/FlashDeviceLib.inf
DxeHobListLib|UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.inf
-HobLib|UefiPayloadPkg/Library/DxeHobLib/DxeHobLib.inf
-TimerLib|UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
!endif
@@ -90,13 +79,20 @@
# SMM Variable Support
#
!if $(SMM_VARIABLE) == TRUE
-PlatformPayloadPkg/PchSmiDispatchSmm/PchSmiDispatchSmm.inf
- PlatformPayloadPkg/Fvb/FvbSmm.inf {
-
- NULL|PlatformPayloadPkg/Library/PcdInitLib/PcdInitLib.inf
- }
+PlatformPayloadPkg/PchSmiDispatchSmm/PchSmiDispatchSmm.inf {
+
+
PlatformHookLib|UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
+}
+
+PlatformPayloadPkg/Fvb/FvbSmm.inf {
+
+
PlatformHookLib|UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
+NULL|PlatformPayloadPkg/Library/PcdInitLib/PcdInitLib.inf
+}
+
MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf {
+
+ PlatformHookLib|UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib
+ .inf
NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
NULL|MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLib.inf
NULL|MdeModulePkg/Library/VarCheckPcdLib/VarCheckPcdLib.inf
@@ -106,7 +102,11 @@
MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf {
+
+ PlatformHookLib|UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib
+ .inf
NULL|PlatformPayloadPkg/Library/PcdInitLib/PcdInitLib.inf
}
-MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
+MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf {
+
+
PlatformHookLib|UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
+}
!endif
diff --git a/Features/Intel/PlatformPayloadPkg/PlatformPayloadPkg.dsc
b/Features/Intel/PlatformPayloadPkg/PlatformPayloadPkg.dsc
index adf028c511..702523a73f 100644
Re: [edk2-devel] [edk2-platforms][PATCH v2 1/1] IntelSiliconPkg/SpiFvbService: Add support for VariableFlashInfoLib
Reviewed-by: Sai Chaganty
-Original Message-
From: Michael Kubacki
Sent: Tuesday, July 12, 2022 4:04 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Ni, Ray
; Oram, Isaac W ; Desimone, Nathaniel
L
Subject: Re: [edk2-devel] [edk2-platforms][PATCH v2 1/1]
IntelSiliconPkg/SpiFvbService: Add support for VariableFlashInfoLib
Reminder about this patch.
Thanks,
Michael
On 7/1/2022 10:39 AM, Michael Kubacki wrote:
> From: Michael Kubacki
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3478
>
> Adds support for getting the variable flash information from
> VariableFlashInfoLib. This library abstracts the source of flash
> information so platforms could expect the information to come from a
> different source in the library implementation than the PCDs
> previously used as the information source in this module.
>
> In particular, the library allows Standalone MM platforms to
> dynamically pass the information behind the library API.
>
> Cc: Rangasai V Chaganty
> Cc: Ray Ni
> Cc: Isaac Oram
> Cc: Nate DeSimone
> Signed-off-by: Michael Kubacki
> ---
>
> Notes:
> V2 changes:
>
> 1. Updated the buffer that is returned from
> GetFvbInfo() to be allocated from pool.
> 2. Updated calls to that function in FvbInitialize()
> to free the new buffer after usage.
> 3. Updated the multiplication operation to determine
> the FV length to use safe multiplication in
> GenerateNvStorageFvbMediaInfo().
>
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.c
> | 128 +---
>
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
> | 93 --
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> | 49 ++--
>
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.h
> | 18 ++-
>
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> | 6 +-
>
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceStandaloneMm.inf
> | 6 +-
> Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
> | 7 ++
> 7 files changed, 243 insertions(+), 64 deletions(-)
>
> diff --git
> a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.c
> b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.c
> index 7f2678fa9e5a..634a44218c7a 100644
> ---
> a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.c
> +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInf
> +++ o.c
> @@ -3,6 +3,7 @@
> These data is intent to decouple FVB driver with FV header.
>
> Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) Microsoft Corporation.
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -11,51 +12,92 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #define FIRMWARE_BLOCK_SIZE 0x1
> #define FVB_MEDIA_BLOCK_SIZEFIRMWARE_BLOCK_SIZE
> -
> -#define NV_STORAGE_BASE_ADDRESS
> FixedPcdGet32(PcdFlashNvStorageVariableBase)
> -#define SYSTEM_NV_BLOCK_NUM
> ((FixedPcdGet32(PcdFlashNvStorageVariableSize)+
> FixedPcdGet32(PcdFlashNvStorageFtwWorkingSize) +
> FixedPcdGet32(PcdFlashNvStorageFtwSpareSize))/ FVB_MEDIA_BLOCK_SIZE)
> -
> typedef struct {
> EFI_PHYSICAL_ADDRESSBaseAddress;
> EFI_FIRMWARE_VOLUME_HEADER FvbInfo;
> EFI_FV_BLOCK_MAP_ENTRY End[1];
> } EFI_FVB2_MEDIA_INFO;
>
> -//
> -// This data structure contains a template of all correct FV headers,
> which is used to restore -// Fv header if it's corrupted.
> -//
> -EFI_FVB2_MEDIA_INFO mPlatformFvbMediaInfo[] = {
> - //
> - // Systen NvStorage FVB
> - //
> - {
> -NV_STORAGE_BASE_ADDRESS,
> -{
> - {0,}, //ZeroVector[16]
> - EFI_SYSTEM_NV_DATA_FV_GUID,
> - FVB_MEDIA_BLOCK_SIZE * SYSTEM_NV_BLOCK_NUM,
> - EFI_FVH_SIGNATURE,
> - 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details
> on EFI_FVB_ATTRIBUTES_2
> - sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
> - 0,//CheckSum which will be calucated dynamically.
> - 0,//ExtHeaderOffset
> - {0,}, //Reserved[1]
> - 2,//Revision
> - {
> -{
> - SYSTEM_NV_BLOCK_NUM,
> - FVB_MEDIA_BLOCK_SIZE,
> -}
> - }
> -},
> -{
> - {
> -0,
> -0
> - }
> -}
> +/**
> + Retur
Re: [edk2-devel] [PATCH v1] Silicon/Intel/FitGen: Fix Type 2 entry version value from BiosInfo would always 0x0
Reviewed-by: Sai Chaganty -Original Message- From: Lin, Jason1 Sent: Tuesday, July 12, 2022 10:56 PM To: devel@edk2.groups.io Cc: Lin, Jason1 ; Feng, Bob C ; Gao, Liming ; Chen, Christine ; Oram, Isaac W ; Chaganty, Rangasai V ; Chiang, Dakota Subject: [PATCH v1] Silicon/Intel/FitGen: Fix Type 2 entry version value from BiosInfo would always 0x0 From: Jason1 Lin REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3988 With the change #3958 using the incorrect variable to store the S-ACM entry version. That would cause the value always 0x0. gFitTableContext.StartupAcm[gFitTableContext.StartupAcmNumber].Version variable should be corrected to gFitTableContext.StartupAcmVersion[gFitTableContext.StartupAcmNumber]. Signed-off-by: Jason1 Lin Cc: Bob Feng Cc: Liming Gao Cc: Yuwei Chen Cc: Isaac W Oram Cc: Rangasai V Chaganty Cc: Dakota Chiang --- Silicon/Intel/Tools/FitGen/FitGen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c b/Silicon/Intel/Tools/FitGen/FitGen.c index 577ce48b10..21dfcf1ebb 100644 --- a/Silicon/Intel/Tools/FitGen/FitGen.c +++ b/Silicon/Intel/Tools/FitGen/FitGen.c @@ -1182,7 +1182,7 @@ Returns: gFitTableContext.StartupAcm[gFitTableContext.StartupAcmNumber].Type = FIT_TABLE_TYPE_STARTUP_ACM; gFitTableContext.StartupAcm[gFitTableContext.StartupAcmNumber].Address = (UINT32)BiosInfoStruct[BiosInfoIndex].Address; gFitTableContext.StartupAcm[gFitTableContext.StartupAcmNumber].Size= (UINT32)BiosInfoStruct[BiosInfoIndex].Size;- gFitTableContext.StartupAcm[gFitTableContext.StartupAcmNumber].Version = BiosInfoStruct[BiosInfoIndex].Version;+ gFitTableContext.StartupAcmVersion[gFitTableContext.StartupAcmNumber] = BiosInfoStruct[BiosInfoIndex].Version; gFitTableContext.StartupAcmNumber ++; gFitTableContext.FitEntryNumber ++; break;-- 2.37.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#91298): https://edk2.groups.io/g/devel/message/91298 Mute This Topic: https://groups.io/mt/92352273/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][edk2-platforms][PATCH V1 1/1] Maintainters.txt: Add Platform and Silicon Intel maintainers
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Tuesday, June 07, 2022 7:33 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Leif Lindholm ; Kinney, Michael D ; Chaganty, Rangasai V ; Desimone, Nathaniel L Subject: [edk2-devel][edk2-platforms][PATCH V1 1/1] Maintainters.txt: Add Platform and Silicon Intel maintainers Enable maintainers for Platform/Intel/ subtree. Enable maintainers for Silicon/Intel/ subtree. This is consistent with Features/Intel/ subtree. Cc: Leif Lindholm Cc: Michael D Kinney Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Isaac Oram --- Maintainers.txt | 12 1 file changed, 12 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index da6abc7344..643e05b293 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -168,6 +168,12 @@ F: Features/Intel/UserInterface/ M: Dandan Bi R: Liming Gao +Platform/Intel +F: Platform/Intel/ +M: Sai Chaganty +M: Isaac Oram +M: Nate DeSimone + Platform/Intel/QuarkPlatformPkg F: Platform/Intel/QuarkPlatformPkg/ M: Michael D Kinney @@ -257,6 +263,12 @@ M: Abner Chang R: Gilbert Chen R: Daniel Schaefer +Silicon/Intel +F: Silicon/Intel/ +M: Rangasai V Chaganty +M: Isaac Oram +M: Nate DeSimone + Silicon/Intel/IntelSiliconPkg F: Silicon/Intel/IntelSiliconPkg/ M: Ray Ni -- 2.36.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90335): https://edk2.groups.io/g/devel/message/90335 Mute This Topic: https://groups.io/mt/91616083/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-non-osi] [PATCH] ElkhartlakeSiliconBinPkg: Update EHL microcode
Reviewed-by: Sai Chaganty
-Original Message-
From: Chan, Kok Wei
Sent: Thursday, March 31, 2022 2:20 AM
To: devel@edk2.groups.io
Cc: Chan, Kok Wei ; Desimone, Nathaniel L
; Chaganty, Rangasai V
; Lim, Jin Jhu
Subject: [edk2-devel] [edk2-non-osi] [PATCH] ElkhartlakeSiliconBinPkg: Update
EHL microcode
Updated "production" microcode version m0190661_0016
Signed-off-by: kokweich
Cc: Nate DeSimone
Cc: Sai Chaganty
Cc: jinjhuli
---
.../Microcode/IntelMicrocodeLicense.txt | 2 +-
.../Microcode/MicrocodeUpdates.inf | 2 +-
.../Microcode/m0190661_0015.mcb | Bin 20480 -> 0 bytes
.../Microcode/m0190661_0016.mcb | Bin 0 -> 20480 bytes
4 files changed, 2 insertions(+), 2 deletions(-)
delete mode 100644
Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/m0190661_0015.mcb
create mode 100644
Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/m0190661_0016.mcb
diff --git
a/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/IntelMicrocodeLicense.txt
b/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/IntelMicrocodeLicense.txt
index 78536ba..7907207 100644
--- a/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/IntelMicrocodeLicense.txt
+++ b/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/IntelMicrocodeLicense.txt
@@ -1,4 +1,4 @@
-Copyright (c) 2018 - 2021 Intel Corporation.
+Copyright (c) 2018 - 2022 Intel Corporation.
All rights reserved.
Redistribution.
diff --git
a/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
b/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
index f99f0a5..669cf69 100644
--- a/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
+++ b/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
@@ -15,4 +15,4 @@
MODULE_TYPE= USER_DEFINED
[Sources]
- m0190661_0015.mcb
+ m0190661_0016.mcb
diff --git
a/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/m0190661_0015.mcb
b/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/m0190661_0015.mcb
deleted file mode 100644
index
06548466d37a06c1342c79f66f149d648dccf40e..
GIT binary patch
literal 0
HcmV?d1
literal 20480
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Re: [edk2-devel][edk2-platforms][PATCH V1 1/1] BeepDebugFeaturePkg: Enable FixedAtBuild PCD type
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Friday, February 11, 2022 4:13 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Desimone, Nathaniel L ; Gao, Liming Subject: [edk2-devel][edk2-platforms][PATCH V1 1/1] BeepDebugFeaturePkg: Enable FixedAtBuild PCD type Enable PcdStatusCodeUseBeep to allow FixedAtBuild type for backwards compatibility. Cc: Sai Chaganty Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Isaac Oram --- Features/Intel/Debugging/BeepDebugFeaturePkg/BeepDebugFeaturePkg.dec | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Features/Intel/Debugging/BeepDebugFeaturePkg/BeepDebugFeaturePkg.dec b/Features/Intel/Debugging/BeepDebugFeaturePkg/BeepDebugFeaturePkg.dec index d90611da51..9f44f228d1 100644 --- a/Features/Intel/Debugging/BeepDebugFeaturePkg/BeepDebugFeaturePkg.dec +++ b/Features/Intel/Debugging/BeepDebugFeaturePkg/BeepDebugFeaturePkg.d +++ ec @@ -34,6 +34,5 @@ [PcdsFeatureFlag] gBeepDebugFeaturePkgTokenSpaceGuid.PcdBeepDebugFeatureEnable|FALSE|BOOLEAN|0x -[PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] - # Beep is a legacy feature, disabled it by default +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] gBeepDebugFeaturePkgTokenSpaceGuid.PcdStatusCodeUseBeep|TRUE|BOOLEAN|0x0001 -- 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#86675): https://edk2.groups.io/g/devel/message/86675 Mute This Topic: https://groups.io/mt/89084754/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v1] Add maintainers for advanced features
Reviewed-by: Sai Chaganty -Original Message- From: Desimone, Nathaniel L Sent: Wednesday, January 19, 2022 3:59 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Oram, Isaac W ; Gao, Liming ; Kinney, Michael D Subject: [PATCH v1] Add maintainers for advanced features Add maintainers to Features/Intel to enable expedient approval of new advanced features. Cc: Sai Chaganty Cc: Isaac Oram Cc: Liming Gao Cc: Michael D Kinney Signed-off-by: Nate DeSimone --- Maintainers.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index a6ce4eee0f..8dcc34ed0c 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -148,6 +148,8 @@ M: Pedro Falcato Features/Intel F: Features/Intel/ M: Sai Chaganty +M: Isaac Oram +M: Nate DeSimone R: Liming Gao Features/Intel/Debugging -- 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85840): https://edk2.groups.io/g/devel/message/85840 Mute This Topic: https://groups.io/mt/88548334/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][edk2-platforms][PATCH V1 20/27] SpcrFeaturePkg: Use MinPlatform build include files
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Tuesday, January 11, 2022 6:20 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Chaganty, Rangasai V ; Gao, Liming Subject: [edk2-devel][edk2-platforms][PATCH V1 20/27] SpcrFeaturePkg: Use MinPlatform build include files Also added feature enable flag Cc: Sai Chaganty Cc: Liming Gao Signed-off-by: Isaac Oram --- Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/Library/SpcrDeviceLib.h | 2 +- Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/PostMemory.fdf | 13 Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/PreMemory.fdf | 11 Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/SpcrFeature.dsc | 62 Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Readme.md | 12 ++-- Features/Intel/OutOfBandManagement/SpcrFeaturePkg/SpcrFeaturePkg.dec | 6 ++ Features/Intel/OutOfBandManagement/SpcrFeaturePkg/SpcrFeaturePkg.dsc | 18 ++ 7 files changed, 55 insertions(+), 69 deletions(-) diff --git a/Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/Library/SpcrDeviceLib.h b/Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/Library/SpcrDeviceLib.h index 947813815e..2e50270ee6 100644 --- a/Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/Library/SpcrDeviceLib.h +++ b/Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/Library/ +++ SpcrDeviceLib.h @@ -12,7 +12,7 @@ /** Get a Serial Port device used for SPCR. - The caller should call FreePool() to free the memory if return value is not NULL. + The caller should call FreePool () to free the memory if return value is not NULL. @retval NULL Can not get device. @retval OthersA serial port device path. diff --git a/Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/PostMemory.fdf b/Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/PostMemory.fdf new file mode 100644 index 00..f963f567c2 --- /dev/null +++ b/Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/PostMemo +++ ry.fdf @@ -0,0 +1,13 @@ +## @file +# FDF file for post-memory SpcrFeature advanced feature. +# +# This file is intended to be included into another package so +advanced features # can be conditionally included in the flash image +by enabling the respective # feature via its FeaturePCD. +# +# Copyright (C) 2022 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent ## + +INF SpcrFeaturePkg/SpcrAcpiDxe/SpcrAcpiDxe.inf diff --git a/Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/PreMemory.fdf b/Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/PreMemory.fdf new file mode 100644 index 00..3c461e7fbc --- /dev/null +++ b/Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/PreMemor +++ y.fdf @@ -0,0 +1,11 @@ +## @file +# FDF file for pre-memory SpcrFeature advanced feature. +# +# This file is intended to be included into another package so +advanced features # can be conditionally included in the flash image +by enabling the respective # feature via its FeaturePCD. +# +# Copyright (C) 2022 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent ## diff --git a/Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/SpcrFeature.dsc b/Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/SpcrFeature.dsc index c51e552df5..b06ddf4fe6 100644 --- a/Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/SpcrFeature.dsc +++ b/Features/Intel/OutOfBandManagement/SpcrFeaturePkg/Include/SpcrFeat +++ ure.dsc @@ -25,40 +25,9 @@ !error "DXE_ARCH must be specified to build this feature!" !endif - -# -# Library Class section - list of all Library Classes needed by this feature. -# - - -!include MdePkg/MdeLibs.dsc.inc - [LibraryClasses] - ### - # Edk2 Packages - ### - BaseLib|MdePkg/Library/BaseLib/BaseLib.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf - UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf - UefiLib|MdePkg/Library/UefiLib/UefiLib.inf - PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf - DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf - UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf - - ### - # SpcrFeaturePk
Re: [edk2-devel][edk2-platforms][PATCH V1 21/27] TemplateFeaturePkg: Use MinPlatform build include files
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Tuesday, January 11, 2022 6:20 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Chaganty, Rangasai V ; Gao, Liming Subject: [edk2-devel][edk2-platforms][PATCH V1 21/27] TemplateFeaturePkg: Use MinPlatform build include files Extend the template to leverage common library build files. Cc: Sai Chaganty Cc: Liming Gao Signed-off-by: Isaac Oram --- Features/Intel/TemplateFeaturePkg/Include/TemplateFeature.dsc | 2 +- Features/Intel/TemplateFeaturePkg/TemplateFeaturePkg.dsc | 18 ++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/Features/Intel/TemplateFeaturePkg/Include/TemplateFeature.dsc b/Features/Intel/TemplateFeaturePkg/Include/TemplateFeature.dsc index 6742eddcf9..dd6d033aca 100644 --- a/Features/Intel/TemplateFeaturePkg/Include/TemplateFeature.dsc +++ b/Features/Intel/TemplateFeaturePkg/Include/TemplateFeature.dsc @@ -73,7 +73,7 @@ #is completed. [Components.IA32] # - # Feature Package + # Feature Package # # Add library instances here that are not included in package components and should be tested diff --git a/Features/Intel/TemplateFeaturePkg/TemplateFeaturePkg.dsc b/Features/Intel/TemplateFeaturePkg/TemplateFeaturePkg.dsc index 0ce8debee0..03657047dc 100644 --- a/Features/Intel/TemplateFeaturePkg/TemplateFeaturePkg.dsc +++ b/Features/Intel/TemplateFeaturePkg/TemplateFeaturePkg.dsc @@ -24,6 +24,24 @@ PEI_ARCH = IA32 DXE_ARCH = X64 +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + +[PcdsFeatureFlag] + # + # PCD needed for MinPlatform build includes + # + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable |FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable |FALSE + +# +# Include common libraries +# +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc + # # This package always builds the feature. # -- 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85706): https://edk2.groups.io/g/devel/message/85706 Mute This Topic: https://groups.io/mt/88365331/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][edk2-platforms][PATCH V1 24/27] MinPlatformPkg/Build: Add an include file for the common SPI FV info
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Tuesday, January 11, 2022 6:20 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Gao, Liming ; Dong, Eric Subject: [edk2-devel][edk2-platforms][PATCH V1 24/27] MinPlatformPkg/Build: Add an include file for the common SPI FV info This include file allows for elimination of a lot of duplicate code and makes FDF files more readable. Cc: Sai Chaganty Cc: Nate DeSimone Cc: Liming Gao Cc: Eric Dong Signed-off-by: Isaac Oram --- Platform/Intel/MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf | 24 1 file changed, 24 insertions(+) diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf b/Platform/Intel/MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf new file mode 100644 index 00..fdda085a41 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fd +++ f @@ -0,0 +1,24 @@ +## @file CommonSpiFvHeaderInfo.fdf +# +# @copyright +# Copyright (C) 2020 - 2021 Intel Corporation # # +SPDX-License-Identifier: BSD-2-Clause-Patent ## + +FvAlignment= 16 #FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS= TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS= TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE -- 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85705): https://edk2.groups.io/g/devel/message/85705 Mute This Topic: https://groups.io/mt/88365353/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][edk2-platforms][PATCH V1 15/27] NetworkFeaturePkg: Use MinPlatformPkg build include files
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Tuesday, January 11, 2022 6:20 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Chaganty, Rangasai V ; Gao, Liming Subject: [edk2-devel][edk2-platforms][PATCH V1 15/27] NetworkFeaturePkg: Use MinPlatformPkg build include files Standalong build was not working due to missing libraries. Leverage MinPlatformPkg common includes for core libraries. Cc: Sai Chaganty Cc: Liming Gao Signed-off-by: Isaac Oram --- Features/Intel/Network/NetworkFeaturePkg/Include/NetworkFeature.dsc | 89 ++-- Features/Intel/Network/NetworkFeaturePkg/NetworkFeaturePkg.dsc | 18 2 files changed, 24 insertions(+), 83 deletions(-) diff --git a/Features/Intel/Network/NetworkFeaturePkg/Include/NetworkFeature.dsc b/Features/Intel/Network/NetworkFeaturePkg/Include/NetworkFeature.dsc index bbc91ecbb1..ca151b4e33 100644 --- a/Features/Intel/Network/NetworkFeaturePkg/Include/NetworkFeature.dsc +++ b/Features/Intel/Network/NetworkFeaturePkg/Include/NetworkFeature.dsc @@ -18,12 +18,12 @@ # [Defines] -!ifndef $(PEI_ARCH) - !error "PEI_ARCH must be specified to build this feature!" -!endif -!ifndef $(DXE_ARCH) - !error "DXE_ARCH must be specified to build this feature!" -!endif + !ifndef $(PEI_ARCH) +!error "PEI_ARCH must be specified to build this feature!" + !endif + !ifndef $(DXE_ARCH) +!error "DXE_ARCH must be specified to build this feature!" + !endif !include NetworkPkg/NetworkDefines.dsc.inc @@ -41,56 +41,9 @@ # -!include MdePkg/MdeLibs.dsc.inc - [LibraryClasses] !include NetworkPkg/NetworkLibs.dsc.inc - - ### - # Edk2 Packages - ### - BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf - BaseLib|MdePkg/Library/BaseLib/BaseLib.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf - DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf - FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf - HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf - IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf - OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf - PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf - PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf - ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf - SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf - SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf - TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf - UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf - UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf - UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf - UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf - UefiLib|MdePkg/Library/UefiLib/UefiLib.inf - UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf - -[LibraryClasses.common.SEC,LibraryClasses.common.PEI_CORE,LibraryClasses.common.PEIM] - ### - # Edk2 Packages - ### - HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf - MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - -[LibraryClasses.common.DXE_CORE,LibraryClasses.common.DXE_SMM_DRIVER,LibraryClasses.common.SMM_CORE,LibraryClasses.common.DXE_DRIVER,LibraryClasses.common.DXE_RUNTIME_DRIVER,LibraryClasses.common.UEFI_DRIVER,LibraryClasses.common.UEFI_APPLICATION] - ### - # Edk2 Packages - ### - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf - HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf - MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf # @@ -106,21 +59,6 @@ # generated for it, but the binary w
Re: [edk2-devel][edk2-platforms][PATCH V1 22/27] AdvancedFeaturePkg: Fix all relative package paths
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Tuesday, January 11, 2022 6:20 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Chaganty, Rangasai V ; Gao, Liming Subject: [edk2-devel][edk2-platforms][PATCH V1 22/27] AdvancedFeaturePkg: Fix all relative package paths Packages should be at the root of a PACKAGES_PATH entry. At some point, paths were relative to edk2-platforms/Features/Intel which was functional, but interferes with the proper functioning of packaging tools. Cc: Sai Chaganty Cc: Liming Gao Signed-off-by: Isaac Oram --- Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeatures.dsc | 15 --- Features/Intel/AdvancedFeaturePkg/Include/PostMemory.fdf | 15 --- Features/Intel/AdvancedFeaturePkg/Include/PreMemory.fdf| 15 --- 3 files changed, 24 insertions(+), 21 deletions(-) diff --git a/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeatures.dsc b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeatures.dsc index ac9ab80e8e..874b8ce7db 100644 --- a/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeatures.dsc +++ b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeatures.dsc @@ -14,45 +14,46 @@ # Debug Advanced Features # !if gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureEnable == TRUE - !include Debugging/AcpiDebugFeaturePkg/Include/AcpiDebugFeature.dsc + !include AcpiDebugFeaturePkg/Include/AcpiDebugFeature.dsc !endif + !if gUsb3DebugFeaturePkgTokenSpaceGuid.PcdUsb3DebugFeatureEnable == TRUE - !include Debugging/Usb3DebugFeaturePkg/Include/Usb3DebugFeature.dsc + !include Usb3DebugFeaturePkg/Include/Usb3DebugFeature.dsc !endif # # Network Advanced Features # !if gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable == TRUE - !include Network/NetworkFeaturePkg/Include/NetworkFeature.dsc + !include NetworkFeaturePkg/Include/NetworkFeature.dsc !endif # # Out-of-Band Management Advanced Features # !if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable == TRUE - !include OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc + !include IpmiFeaturePkg/Include/IpmiFeature.dsc !endif # # Power Management Advanced Features # !if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable == TRUE - !include PowerManagement/S3FeaturePkg/Include/S3Feature.dsc + !include S3FeaturePkg/Include/S3Feature.dsc !endif # # System Information Advanced Features # !if gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable == TRUE - !include SystemInformation/SmbiosFeaturePkg/Include/SmbiosFeature.dsc + !include SmbiosFeaturePkg/Include/SmbiosFeature.dsc !endif # # User Interface Advanced Features # !if gUserAuthFeaturePkgTokenSpaceGuid.PcdUserAuthenticationFeatureEnable == TRUE - !include UserInterface/UserAuthFeaturePkg/Include/UserAuthFeature.dsc + !include UserAuthFeaturePkg/Include/UserAuthFeature.dsc !endif !if gLogoFeaturePkgTokenSpaceGuid.PcdLogoFeatureEnable == TRUE diff --git a/Features/Intel/AdvancedFeaturePkg/Include/PostMemory.fdf b/Features/Intel/AdvancedFeaturePkg/Include/PostMemory.fdf index c49a0fd875..e710fe7f01 100644 --- a/Features/Intel/AdvancedFeaturePkg/Include/PostMemory.fdf +++ b/Features/Intel/AdvancedFeaturePkg/Include/PostMemory.fdf @@ -15,45 +15,46 @@ # Debug Advanced Features # !if gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureEnable == TRUE - !include Debugging/AcpiDebugFeaturePkg/Include/PostMemory.fdf + !include AcpiDebugFeaturePkg/Include/PostMemory.fdf !endif + !if gUsb3DebugFeaturePkgTokenSpaceGuid.PcdUsb3DebugFeatureEnable == TRUE - !include Debugging/Usb3DebugFeaturePkg/Include/PostMemory.fdf + !include Usb3DebugFeaturePkg/Include/PostMemory.fdf !endif # # Network Advanced Features # !if gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable == TRUE - !include Network/NetworkFeaturePkg/Include/PostMemory.fdf + !include NetworkFeaturePkg/Include/PostMemory.fdf !endif # # Out-of-Band Management Advanced Features # !if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable == TRUE - !include OutOfBandManagement/IpmiFeaturePkg/Include/PostMemory.fdf + !include IpmiFeaturePkg/Include/PostMemory.fdf !endif # # Power Management Advanced Features # !if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable == TRUE - !include PowerManagement/S3FeaturePkg/Include/PostMemory.fdf + !include S3FeaturePkg/Include/PostMemory.fdf !endif # # System Information Advanced Features # !if gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable == TRUE - !include SystemInformation/SmbiosFeaturePkg/Include/PostMemory.fdf + !include SmbiosFeaturePkg/Include/PostMemory.fdf !endif # # User Interface Advanced Features # !if gUserAuthFeaturePkgTokenSpaceGuid.PcdUserAuthenticationFeatureEnable == TRUE - !include UserInterface/UserAuthFeaturePkg/Include/PostMemory.fdf + !include UserAuthFeaturePkg/Include/PostMemory.fdf !endif !if gLogoFeaturePkgTokenSpaceGuid.PcdLogoFeatureEnable
Re: [edk2-devel][edk2-platforms][PATCH V1 23/27] AdvancedFeaturePkg: Add missing features
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Tuesday, January 11, 2022 6:20 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Chaganty, Rangasai V ; Gao, Liming Subject: [edk2-devel][edk2-platforms][PATCH V1 23/27] AdvancedFeaturePkg: Add missing features The AdvancedFeaturePkg is supposed to include all features. Add Beep Debug feature to include DSC and FDF. Order features based on their domains. Cc: Sai Chaganty Cc: Liming Gao Signed-off-by: Isaac Oram --- Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc | 66 Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeatures.dsc| 36 --- Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc | 64 +++ Features/Intel/AdvancedFeaturePkg/Include/PostMemory.fdf | 36 --- Features/Intel/AdvancedFeaturePkg/Include/PreMemory.fdf | 36 --- Features/Intel/Readme.md | 49 ++- 6 files changed, 219 insertions(+), 68 deletions(-) diff --git a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc b/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc index 0c7a29cc75..02636da916 100644 --- a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc +++ b/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc @@ -36,7 +36,6 @@ !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc - # # Advanced Feature Enable section - all advanced features are enabling for the @@ -44,26 +43,71 @@ # [PcdsFeatureFlag] - gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureEnable|TRUE - gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |TRUE - gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable|TRUE - gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable |TRUE - gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable |TRUE - gUsb3DebugFeaturePkgTokenSpaceGuid.PcdUsb3DebugFeatureEnable|TRUE - gUserAuthFeaturePkgTokenSpaceGuid.PcdUserAuthenticationFeatureEnable|TRUE - gLogoFeaturePkgTokenSpaceGuid.PcdLogoFeatureEnable |TRUE - gLogoFeaturePkgTokenSpaceGuid.PcdJpgEnable |FALSE + # + # Debugging features + # + gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureEnable |TRUE + gBeepDebugFeaturePkgTokenSpaceGuid.PcdBeepDebugFeatureEnable |TRUE + gPostCodeDebugFeaturePkgTokenSpaceGuid.PcdPostCodeDebugFeatureEnable |TRUE + gUsb3DebugFeaturePkgTokenSpaceGuid.PcdUsb3DebugFeatureEnable |TRUE + + # + # Network features + # + gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable |TRUE + + # + # OutOfBandManagement features + # + gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |TRUE + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrFeatureEnable |TRUE + + # + # PowerManagement features + # + gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable |TRUE + + # + # SystemInformation features + # + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable |TRUE + + # + # UserInterface features + # + gLogoFeaturePkgTokenSpaceGuid.PcdLogoFeatureEnable |TRUE + gUserAuthFeaturePkgTokenSpaceGuid.PcdUserAuthenticationFeatureEnable |TRUE + + gVirtualKeyboardFeaturePkgTokenSpaceGuid.PcdVirtualKeyboardFeatureEnab + le |TRUE + +# +# PCD that are required to be set by the build target should be +configured here for test purposes # These settings are only for the purposes of buildings, boards should follow instructions in Readme files. +# + +[PcdsFixedAtBuild] + gUsb3DebugFeaturePkgTokenSpaceGuid.PcdUsb3DebugPortLibInstance|1 + +[PcdsFeatureFlag] + # + # MinPlatform common include currently required PCD + # gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable |FALSE gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable |FALSE # -# Include common library +# Include common libraries # !include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc !include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc !include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# +# Libraries required to be specified by the build target # +[LibraryClasses.Common] + +PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatfo +rmHookLibNull.inf # Required by BeepDebugFeature + # # This package builds all advanced features. # diff --git a/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeatures.dsc b/Features/Intel/AdvancedFeaturePkg
Re: [edk2-devel][edk2-platforms][PATCH V1 08/27] SmbiosFeaturePkg: Fix all relative package paths
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Tuesday, January 11, 2022 6:20 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Chaganty, Rangasai V ; Gao, Liming Subject: [edk2-devel][edk2-platforms][PATCH V1 08/27] SmbiosFeaturePkg: Fix all relative package paths Packages should be at the root of a PACKAGES_PATH entry. At some point, paths were relative to edk2-platforms/Features/Intel which was functional, but interferes with the proper functioning of packaging tools. Cc: Sai Chaganty Cc: Liming Gao Signed-off-by: Isaac Oram --- Features/Intel/SystemInformation/SmbiosFeaturePkg/Include/PostMemory.fdf | 2 +- Features/Intel/SystemInformation/SmbiosFeaturePkg/Include/SmbiosFeature.dsc | 2 +- Features/Intel/SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf | 2 +- Features/Intel/SystemInformation/SmbiosFeaturePkg/SmbiosFeaturePkg.dec | 10 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/Features/Intel/SystemInformation/SmbiosFeaturePkg/Include/PostMemory.fdf b/Features/Intel/SystemInformation/SmbiosFeaturePkg/Include/PostMemory.fdf index 3ed23bd937..c3a3e81503 100644 --- a/Features/Intel/SystemInformation/SmbiosFeaturePkg/Include/PostMemory.fdf +++ b/Features/Intel/SystemInformation/SmbiosFeaturePkg/Include/PostMemo +++ ry.fdf @@ -7,4 +7,4 @@ # ## - INF SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + INF SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf diff --git a/Features/Intel/SystemInformation/SmbiosFeaturePkg/Include/SmbiosFeature.dsc b/Features/Intel/SystemInformation/SmbiosFeaturePkg/Include/SmbiosFeature.dsc index 31d44b68b3..094dd957b8 100644 --- a/Features/Intel/SystemInformation/SmbiosFeaturePkg/Include/SmbiosFeature.dsc +++ b/Features/Intel/SystemInformation/SmbiosFeaturePkg/Include/SmbiosFe +++ ature.dsc @@ -100,7 +100,7 @@ # in the package build. # Add components here that should be included in the package build. - SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf ### # diff --git a/Features/Intel/SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf b/Features/Intel/SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf index bd8736b621..8e530c4945 100644 --- a/Features/Intel/SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf +++ b/Features/Intel/SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/S +++ mbiosBasicDxe.inf @@ -33,7 +33,7 @@ [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec - SystemInformation/SmbiosFeaturePkg/SmbiosFeaturePkg.dec + SmbiosFeaturePkg/SmbiosFeaturePkg.dec [LibraryClasses] BaseLib diff --git a/Features/Intel/SystemInformation/SmbiosFeaturePkg/SmbiosFeaturePkg.dec b/Features/Intel/SystemInformation/SmbiosFeaturePkg/SmbiosFeaturePkg.dec index 6170f37969..db3cdbb0d0 100644 --- a/Features/Intel/SystemInformation/SmbiosFeaturePkg/SmbiosFeaturePkg.dec +++ b/Features/Intel/SystemInformation/SmbiosFeaturePkg/SmbiosFeaturePkg +++ .dec @@ -38,7 +38,7 @@ IndustryStandard/SmBios.h MdePkg/MdePkg.dec - SystemInformation/SmbiosFeaturePkg/SmbiosFeaturePkg.dec + SmbiosFeaturePkg/SmbiosFeaturePkg.dec } gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.Vendor|0x1 gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosVersion|0x2 @@ -71,7 +71,7 @@ IndustryStandard/SmBios.h MdePkg/MdePkg.dec - SystemInformation/SmbiosFeaturePkg/SmbiosFeaturePkg.dec + SmbiosFeaturePkg/SmbiosFeaturePkg.dec } gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Manufacturer|0x1 gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.ProductName|0x2 @@ -87,7 +87,7 @@ IndustryStandard/SmBios.h MdePkg/MdePkg.dec - SystemInformation/SmbiosFeaturePkg/SmbiosFeaturePkg.dec + SmbiosFeaturePkg/SmbiosFeaturePkg.dec } # @@ -111,7 +111,7 @@ IndustryStandard/SmBios.h MdePkg/MdePkg.dec - SystemInformation/SmbiosFeaturePkg/SmbiosFeaturePkg.dec + SmbiosFeaturePkg/SmbiosFeaturePkg.dec } gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3SystemEnclosureChassis.Manufacturer|0x1 gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3SystemEnclosureChassis.Type|MiscChassisTypeRackMountChassis @@ -131,7 +131,7 @@ IndustryStandard/SmBios.h MdePkg/MdePkg.dec - SystemInformation/SmbiosFeaturePkg/SmbiosFeaturePkg.dec + SmbiosFeaturePkg/SmbiosFeaturePkg.dec } gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType32SystemBootInformation.BootStatus|BootInformationStatusNoError -- 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online
Re: [edk2-devel][edk2-platforms][PATCH V1 07/27] S3FeaturePkg: Use MinPlatformPkg build include files
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Tuesday, January 11, 2022 6:20 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Chaganty, Rangasai V ; Gao, Liming Subject: [edk2-devel][edk2-platforms][PATCH V1 07/27] S3FeaturePkg: Use MinPlatformPkg build include files Use the MinPlatformPkg common core build files to build libraries needed by this feature. Cc: Sai Chaganty Cc: Liming Gao Signed-off-by: Isaac Oram --- Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf | 2 +- Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc | 72 ++-- Features/Intel/PowerManagement/S3FeaturePkg/S3FeaturePkg.dsc | 18 + 3 files changed, 26 insertions(+), 66 deletions(-) diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf index 34caf3dacc..fdd16a4e03 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf @@ -7,4 +7,4 @@ # ## - INF S3FeaturePkg/S3Pei/S3Pei.inf +INF S3FeaturePkg/S3Pei/S3Pei.inf diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc index f94bd2b431..cc34e78507 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc @@ -18,12 +18,12 @@ # [Defines] -!ifndef $(PEI_ARCH) - !error "PEI_ARCH must be specified to build this feature!" -!endif -!ifndef $(DXE_ARCH) - !error "DXE_ARCH must be specified to build this feature!" -!endif + !ifndef $(PEI_ARCH) +!error "PEI_ARCH must be specified to build this feature!" + !endif + !ifndef $(DXE_ARCH) +!error "DXE_ARCH must be specified to build this feature!" + !endif # @@ -31,34 +31,7 @@ # -!include MdePkg/MdeLibs.dsc.inc - -[LibraryClasses] - ### - # Edk2 Packages - ### - BaseLib|MdePkg/Library/BaseLib/BaseLib.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf - IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf - PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf - PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf - PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf - -[LibraryClasses.common.PEI_CORE,LibraryClasses.common.PEIM] - ### - # Edk2 Packages - ### - HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf - MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf - PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf - PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf - - ### - # Silicon Initialization Package - ### +[LibraryClasses.common.PEIM] SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf @@ -92,34 +65,3 @@ # Add components here that should be included in the package build. S3FeaturePkg/S3Pei/S3Pei.inf - -# -# Feature DXE Components -# - -# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzilla.tianocore.org/show_bug.cgi?id=2308 -#is completed. -[Components.X64] - # - # S3 Feature Package - # - - # Add library instances here that are not included in package components and should be tested - # in the package build. - - # Add components here that should be included in the package build. - -### -# -# BuildOptions Section - Define the module specific tool chain flags that should be used as -#the default flags for a module. These flags are appended to any -#standard flags that are defined by the build process. They can be -#applied for any modules or only those modules with the specific -#module style (EDK or EDKII) specified in [Components] section. -# -#
Re: [edk2-devel][edk2-platforms][PATCH V1 02/27] BeepDebugFeaturePkg: Fix all relative package paths
Reviewed-by: Sai Chaganty
-Original Message-
From: Oram, Isaac W
Sent: Tuesday, January 11, 2022 6:20 PM
To: devel@edk2.groups.io
Cc: Oram, Isaac W ; Chaganty, Rangasai V
; Gao, Liming ; Dong,
Eric
Subject: [edk2-devel][edk2-platforms][PATCH V1 02/27] BeepDebugFeaturePkg: Fix
all relative package paths
Packages should be at the root of a PACKAGES_PATH entry.
At some point, paths were relative to edk2-platforms/Features/Intel which was
functional, but interferes with the proper functioning of packaging tools.
Cc: Sai Chaganty
Cc: Liming Gao
Cc: Eric Dong
Signed-off-by: Isaac Oram
---
Features/Intel/Debugging/BeepDebugFeaturePkg/Include/BeepDebugFeature.dsc | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git
a/Features/Intel/Debugging/BeepDebugFeaturePkg/Include/BeepDebugFeature.dsc
b/Features/Intel/Debugging/BeepDebugFeaturePkg/Include/BeepDebugFeature.dsc
index 251de6932b..00ef022657 100644
--- a/Features/Intel/Debugging/BeepDebugFeaturePkg/Include/BeepDebugFeature.dsc
+++ b/Features/Intel/Debugging/BeepDebugFeaturePkg/Include/BeepDebugFeat
+++ ure.dsc
@@ -54,17 +54,17 @@
gBeepDebugFeaturePkgTokenSpaceGuid.PcdStatusCodeUseBeep
[LibraryClasses.Common]
- BeepLib|Debugging/BeepDebugFeaturePkg/Library/BeepLib/BeepLibNull.inf
- BeepMapLib|Debugging/BeepDebugFeaturePkg/Library/BeepMapLib/BeepMapLib.inf
+ BeepLib|BeepDebugFeaturePkg/Library/BeepLib/BeepLibNull.inf
+ BeepMapLib|BeepDebugFeaturePkg/Library/BeepMapLib/BeepMapLib.inf
[LibraryClasses.PEIM, LibraryClasses.PEI_CORE]
-
StatusCodeHandlerLib|Debugging/BeepDebugFeaturePkg/Library/BeepStatusCodeHandlerLib/PeiBeepStatusCodeHandlerLib.inf
+
+ StatusCodeHandlerLib|BeepDebugFeaturePkg/Library/BeepStatusCodeHandler
+ Lib/PeiBeepStatusCodeHandlerLib.inf
[LibraryClasses.DXE_RUNTIME_DRIVER]
-
StatusCodeHandlerLib|Debugging/BeepDebugFeaturePkg/Library/BeepStatusCodeHandlerLib/RuntimeDxeBeepStatusCodeHandlerLib.inf
+
+ StatusCodeHandlerLib|BeepDebugFeaturePkg/Library/BeepStatusCodeHandler
+ Lib/RuntimeDxeBeepStatusCodeHandlerLib.inf
[LibraryClasses.DXE_SMM_DRIVER]
-
StatusCodeHandlerLib|Debugging/BeepDebugFeaturePkg/Library/BeepStatusCodeHandlerLib/SmmBeepStatusCodeHandlerLib.inf
+
+ StatusCodeHandlerLib|BeepDebugFeaturePkg/Library/BeepStatusCodeHandler
+ Lib/SmmBeepStatusCodeHandlerLib.inf
[Components.IA32]
@@ -77,7 +77,7 @@
#
FILE_GUID = $(BEEP_PEIM_FILENAME)
-
NULL|Debugging/BeepDebugFeaturePkg/Library/BeepStatusCodeHandlerLib/PeiBeepStatusCodeHandlerLib.inf
+
+ NULL|BeepDebugFeaturePkg/Library/BeepStatusCodeHandlerLib/PeiBeepStatu
+ sCodeHandlerLib.inf
}
[Components.X64]
@@ -90,7 +90,7 @@
#
FILE_GUID = $(BEEP_DXE_FILENAME)
-
NULL|Debugging/BeepDebugFeaturePkg/Library/BeepStatusCodeHandlerLib/RuntimeDxeBeepStatusCodeHandlerLib.inf
+
+ NULL|BeepDebugFeaturePkg/Library/BeepStatusCodeHandlerLib/RuntimeDxeBe
+ epStatusCodeHandlerLib.inf
}
MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf { @@
-102,5 +102,5 @@
#
FILE_GUID = $(BEEP_SMM_FILENAME)
-
NULL|Debugging/BeepDebugFeaturePkg/Library/BeepStatusCodeHandlerLib/SmmBeepStatusCodeHandlerLib.inf
+
+ NULL|BeepDebugFeaturePkg/Library/BeepStatusCodeHandlerLib/SmmBeepStatu
+ sCodeHandlerLib.inf
}
--
2.27.0.windows.1
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Re: [edk2-devel][edk2-platforms][PATCH V1 06/27] S3FeaturePkg: Fix all relative package paths
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Tuesday, January 11, 2022 6:20 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Chaganty, Rangasai V ; Gao, Liming Subject: [edk2-devel][edk2-platforms][PATCH V1 06/27] S3FeaturePkg: Fix all relative package paths Packages should be at the root of a PACKAGES_PATH entry. At some point, paths were relative to edk2-platforms/Features/Intel which was functional, but interferes with the proper functioning of packaging tools. Cc: Sai Chaganty Cc: Liming Gao Signed-off-by: Isaac Oram --- Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf | 2 +- Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc | 2 +- Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf index 3cd5cd9628..34caf3dacc 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf @@ -7,4 +7,4 @@ # ## - INF PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf + INF S3FeaturePkg/S3Pei/S3Pei.inf diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc index 312870981e..f94bd2b431 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc @@ -91,7 +91,7 @@ # in the package build. # Add components here that should be included in the package build. - PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf + S3FeaturePkg/S3Pei/S3Pei.inf # # Feature DXE Components diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf index 46fbb62a46..e485eac952 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf @@ -23,7 +23,7 @@ [Packages] MdePkg/MdePkg.dec IntelSiliconPkg/IntelSiliconPkg.dec - PowerManagement/S3FeaturePkg/S3FeaturePkg.dec + S3FeaturePkg/S3FeaturePkg.dec [Sources] S3Pei.c -- 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85698): https://edk2.groups.io/g/devel/message/85698 Mute This Topic: https://groups.io/mt/88365334/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][edk2-platforms][PATCH V1 03/27] AcpiDebugFeaturePkg: Fix all relative package paths
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Tuesday, January 11, 2022 6:20 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Chaganty, Rangasai V ; Gao, Liming ; Dong, Eric Subject: [edk2-devel][edk2-platforms][PATCH V1 03/27] AcpiDebugFeaturePkg: Fix all relative package paths Packages should be at the root of a PACKAGES_PATH entry. At some point, paths were relative to edk2-platforms/Features/Intel which was functional, but interferes with the proper functioning of packaging tools. Cc: Sai Chaganty Cc: Liming Gao Cc: Eric Dong Signed-off-by: Isaac Oram --- Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugDxe.inf | 2 +- Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugSmm.inf | 2 +- Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugFeaturePkg.dec | 2 +- Features/Intel/Debugging/AcpiDebugFeaturePkg/Include/AcpiDebugFeature.dsc | 4 ++-- Features/Intel/Debugging/AcpiDebugFeaturePkg/Include/PostMemory.fdf | 4 ++-- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugDxe.inf b/Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugDxe.inf index b293d83cd9..04b5953bf6 100644 --- a/Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugDxe.inf +++ b/Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiD +++ ebugDxe.inf @@ -32,7 +32,7 @@ [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec - Debugging/AcpiDebugFeaturePkg/AcpiDebugFeaturePkg.dec + AcpiDebugFeaturePkg/AcpiDebugFeaturePkg.dec [Pcd] gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureActive ## CONSUMES diff --git a/Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugSmm.inf b/Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugSmm.inf index dbb33e4ae2..a0058b51ab 100644 --- a/Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugSmm.inf +++ b/Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiD +++ ebugSmm.inf @@ -33,7 +33,7 @@ [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec - Debugging/AcpiDebugFeaturePkg/AcpiDebugFeaturePkg.dec + AcpiDebugFeaturePkg/AcpiDebugFeaturePkg.dec [Pcd] gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureActive ## CONSUMES diff --git a/Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugFeaturePkg.dec b/Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugFeaturePkg.dec index c3bd89fe2b..9159231007 100644 --- a/Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugFeaturePkg.dec +++ b/Features/Intel/Debugging/AcpiDebugFeaturePkg/AcpiDebugFeaturePkg.d +++ ec @@ -29,7 +29,7 @@ [PcdsFeatureFlag] gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureEnable|FALSE|BOOLEAN|0xA001 -[PcdsFixedAtBuild,PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx] +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] ## This PCD specifies the ACPI debug message buffer size. gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugBufferSize|0x1|UINT32|0xF001 diff --git a/Features/Intel/Debugging/AcpiDebugFeaturePkg/Include/AcpiDebugFeature.dsc b/Features/Intel/Debugging/AcpiDebugFeaturePkg/Include/AcpiDebugFeature.dsc index 856222a53d..b142978be1 100644 --- a/Features/Intel/Debugging/AcpiDebugFeaturePkg/Include/AcpiDebugFeature.dsc +++ b/Features/Intel/Debugging/AcpiDebugFeaturePkg/Include/AcpiDebugFeat +++ ure.dsc @@ -109,8 +109,8 @@ # in the package build. # Add components here that should be included in the package build. - Debugging/AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugDxe.inf - Debugging/AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugSmm.inf + AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugDxe.inf + AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugSmm.inf ### # diff --git a/Features/Intel/Debugging/AcpiDebugFeaturePkg/Include/PostMemory.fdf b/Features/Intel/Debugging/AcpiDebugFeaturePkg/Include/PostMemory.fdf index bbd6eca87b..84560dae50 100644 --- a/Features/Intel/Debugging/AcpiDebugFeaturePkg/Include/PostMemory.fdf +++ b/Features/Intel/Debugging/AcpiDebugFeaturePkg/Include/PostMemory.fd +++ f @@ -7,5 +7,5 @@ # ## - INF RuleOverride = DRIVER_ACPITABLE Debugging/AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugDxe.inf - INF RuleOverride = DRIVER_ACPITABLE Debugging/AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugSmm.inf + INF RuleOverride = DRIVER_ACPITABLE + AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugDxe.inf + INF RuleOverride = DRIVER_ACPITABLE + AcpiDebugFeaturePkg/AcpiDebugDxeSmm/AcpiDebugSmm.inf -- 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85697): https://edk2.groups.io/g/devel/message/85697 Mute This Topic: https
Re: [edk2-devel] [PATCH] IntelSiliconPkg/IntelVTdDxe: Reduce Debug Level
Reviewed-by: Sai Chaganty -Original Message- From: Sheng, W Sent: Monday, January 10, 2022 5:27 PM To: devel@edk2.groups.io Cc: Ni, Ray ; Chaganty, Rangasai V ; Huang, Jenny ; Kowalewski, Robert Subject: [PATCH] IntelSiliconPkg/IntelVTdDxe: Reduce Debug Level Reduce the debug level from DEBUG_INFO to DEBUG_VERBOSE in function SubmitQueuedInvalidationDescriptor (). REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3801 Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Jenny Huang Cc: Robert Kowalewski Signed-off-by: Sheng Wei --- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c index 1ce9c1c0..c88f462b 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -238,7 +238,7 @@ SubmitQueuedInvalidationDescriptor ( QiDescLength = mVtdUnitInformation[VtdIndex].QiDescLength; BaseDesc = mVtdUnitInformation[VtdIndex].QiDesc; - DEBUG((DEBUG_INFO, "[%d] Submit QI Descriptor [0x%08x, 0x%08x] Free Head (%d)\n", VtdIndex, Desc->Low, Desc->High, mVtdUnitInformation[VtdIndex].QiFreeHead)); + DEBUG((DEBUG_VERBOSE, "[%d] Submit QI Descriptor [0x%08x, 0x%08x] + Free Head (%d)\n", VtdIndex, Desc->Low, Desc->High, + mVtdUnitInformation[VtdIndex].QiFreeHead)); BaseDesc[mVtdUnitInformation[VtdIndex].QiFreeHead].Low = Desc->Low; BaseDesc[mVtdUnitInformation[VtdIndex].QiFreeHead].High = Desc->High; -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85518): https://edk2.groups.io/g/devel/message/85518 Mute This Topic: https://groups.io/mt/88339715/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2platforms][PATCH v4 1/1] IntelSiliconPkg: Add IntelDieInfoProtocol
Reviewed-by: Sai Chaganty
-Original Message-
From: Czajkowski, Maciej
Sent: Tuesday, December 07, 2021 7:21 AM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V
Subject: [edk2platforms][PATCH v4 1/1] IntelSiliconPkg: Add IntelDieInfoProtocol
Added IntelDieInfo header into IntelSiliconPkg tree.
The purpose is to have generic and unified interface for getting information
about dies installed in the system.
It will be implemented by silicon code.
Cc: Ray Ni
Cc: Rangasai V Chaganty
Signed-off-by: Maciej Czajkowski
---
Notes:
v4:
- removed Signature field
v3:
- added EDKII_ prefix to interface
- removed GUID definitons from .h file
- corrected descriptions
- made PPI/protocol GUIDs unique
v2:
- added interface description
- added die specific GUIDs into .dec file
Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfo.h | 94
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 9 ++
2 files changed, 103 insertions(+)
diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfo.h
b/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfo.h
new file mode 100644
index ..bba2908bf598
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfo.h
@@ -0,0 +1,94 @@
+/** @file+ IntelDieInfo definition++ Copyright (c) 2021, Intel Corporation.
All rights reserved.+ SPDX-License-Identifier:
BSD-2-Clause-Patent++**/+#ifndef _DIE_INFO_PROTOCOL_H_+#define
_DIE_INFO_PROTOCOL_H_++typedef struct _EDKII_INTEL_DIE_INFO_PROTOCOL
EDKII_INTEL_DIE_INFO_PROTOCOL;+typedef EDKII_INTEL_DIE_INFO_PROTOCOL
EDKII_INTEL_DIE_INFO_PPI;++extern EFI_GUID gIntelDieInfoProtocolGuid;+extern
EFI_GUID gIntelDieInfoPpiGuid;++extern EFI_GUID gIntelDieInfoPchGuid;+extern
EFI_GUID gIntelDieInfoSocGuid;+extern EFI_GUID gIntelDieInfoIoGuid;+extern
EFI_GUID gIntelDieInfoCpuGuid;+extern EFI_GUID gIntelDieInfoGfxGuid;++#define
DIE_INFO_PROTOCOL_REVISION 1++/**+ Returns pointer to constant string
representing die name.+ Name is specific to die type.++ @param[in] This
Pointer to the DieInfoProtocol context structure+ @retval Pointer to the const
string+**/+typedef+CONST CHAR8*+(EFIAPI *EDKII_INTEL_DIE_INFO_GET_DIE_NAME_STR)
(+ IN EDKII_INTEL_DIE_INFO_PROTOCOL *This+ );++/**+ Returns pointer to
constant string representing stepping of the die.++ @param[in] This Pointer
to the DieInfoProtocol context structure+ @retval Pointer to the const
string+**/+typedef+CONST CHAR8*+(EFIAPI *EDKII_INTEL_DIE_INFO_GET_STEPPING_STR)
(+ IN EDKII_INTEL_DIE_INFO_PROTOCOL *This+ );++/**+ Returns pointer to
constant string representing SKU of the die.++ @param[in] This Pointer to the
DieInfoProtocol context structure+ @retval Pointer to the const
string+**/+typedef+CONST CHAR8*+(EFIAPI *EDKII_INTEL_DIE_INFO_GET_SKU_STR) (+
IN EDKII_INTEL_DIE_INFO_PROTOCOL *This+ );++/**+ Protocol/PPI definition.+
The purpose of this interface is to serve die-specific informations in a
unified, generic way.+ It will be produced by silicon code per die, and can be
consumed by any module that needs contained information.++ Revision 1:+
- Initial version.+**/+struct _EDKII_INTEL_DIE_INFO_PROTOCOL {+ UINT32
Revision; ///< Current protocol revision+ /**+
Type of the die that particular instance is reffering to.+ **/+ EFI_GUID
Type;+ /**+Index of the die in the package.+
**/+ UINT32 DieIndex;+ /**+Unique ID
specific to the die and the associated generation.+ **/+ UINT64
DieId;+ /**+Generation and die specific stepping ID.+
**/+ UINT32 SteppingId;++
EDKII_INTEL_DIE_INFO_GET_DIE_NAME_STR GetNameStr;+
EDKII_INTEL_DIE_INFO_GET_STEPPING_STR GetSteppingStr;+
EDKII_INTEL_DIE_INFO_GET_SKU_STR GetSkuStr;+};++#endif //
_DIE_INFO_PROTOCOL_H_diff --git
a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index f950c3d1c72b..e5b785ae6204 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -92,12 +92,20 @@ [Guids]
gFlashRegionAllGuid = { 0xbabe60dc, 0xf88d, 0x4584, {0x9e,
0x54, 0x57, 0x44, 0x4b, 0xe2, 0x6e, 0xf3 } } gFlashRegionMaxGuid
= { 0x74c2e3c1, 0x8faa, 0x4659, {0xa7, 0xbb, 0x87, 0x1f, 0xbb, 0x61, 0xd3,
0xb4 } } + ## Include/Protocol/IntelDieInfo.h+ gIntelDieInfoPchGuid = {
0x62CB6D68, 0x4771, 0x4569, { 0x81, 0xFA, 0x1E, 0x99, 0x6E, 0xA9, 0x91, 0xC5
}}+ gIntelDieInfoSocGuid = { 0x63287105, 0x578E, 0x4799, { 0xBE, 0x55, 0x5D,
0xDA, 0xCA, 0x03, 0x74, 0xD0 }}+ gIntelDieInfoIoGuid = { 0x23DA4C74, 0x54A0,
0x4E01, { 0x83, 0xB1, 0x8C, 0xA7, 0x43, 0x43, 0x1F, 0xF0 }}+
gIntelDieInfoCpuGuid = { 0x6E5AF2E3, 0x5D84, 0x48F2, { 0
Re: [edk2-devel] [edk2-non-osi] [PATCH] ElkhartlakeSiliconBinPkg: Update EHL microcode
Reviewed-by: Sai Chaganty
-Original Message-
From: Chan, Kok Wei
Sent: Tuesday, November 30, 2021 11:55 PM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Chaganty, Rangasai
V ; Lim, Jin Jhu
Subject: [edk2-devel] [edk2-non-osi] [PATCH] ElkhartlakeSiliconBinPkg: Update
EHL microcode
Updated "production" microcode version m0190661_0015
Signed-off-by: kokweich
Cc: Nate DeSimone
Cc: Sai Chaganty
Cc: jinjhuli
---
.../Microcode/IntelMicrocodeLicense.txt | 2 +-
.../Microcode/MicrocodeUpdates.inf | 2 +-
.../Microcode/m0190661_0014.mcb | Bin 20480 -> 0 bytes
.../Microcode/m0190661_0015.mcb | Bin 0 -> 20480 bytes
4 files changed, 2 insertions(+), 2 deletions(-)
delete mode 100644
Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/m0190661_0014.mcb
create mode 100644
Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/m0190661_0015.mcb
diff --git
a/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/IntelMicrocodeLicense.txt
b/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/IntelMicrocodeLicense.txt
index ea33b61..78536ba 100644
--- a/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/IntelMicrocodeLicense.txt
+++ b/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/IntelMicrocodeLicense.txt
@@ -1,4 +1,4 @@
-Copyright (c) 2018 - 2020 Intel Corporation.
+Copyright (c) 2018 - 2021 Intel Corporation.
All rights reserved.
Redistribution.
diff --git
a/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
b/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
index fda220a..f99f0a5 100644
--- a/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
+++ b/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
@@ -15,4 +15,4 @@
MODULE_TYPE= USER_DEFINED
[Sources]
- m0190661_0014.mcb
+ m0190661_0015.mcb
diff --git
a/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/m0190661_0014.mcb
b/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/m0190661_0014.mcb
deleted file mode 100644
index
1a7eb9a4ffd7544255b1d20f94c877aed02bfa07..
GIT binary patch
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zG7Zky3=1rg^f(eSU~teZL||gLHMC=bd%SWY>G@2QrkuGEl&|vj969C^d;B8Pg;t
zo@+>evH;$B5@oahiVu>t>~{(!98Jr$)FW4x3Ef@ll{ft-gQq9@
z-iObU2sXwjzr-k1Fo^E-*9`bz{7Z==TUlaCnMeyJq5DP=)|HyvlX!1_rcq!Z+_
zoXn%vZTRjS8HGIto{pjFlAQ!e5xk5?8iTh!I>q7HQ2uC~n<=6DZ|ix5u-F5~uKb{Or>o{35)a9wh+6i6@5~&)ElEZi
z@S@W|xt}L|HQ%#(^(6d<4w*ZZG6cmR5o0dhL@dy2ZX7&?NJpB|uI6j)b
Re: [edk2-devel] [PATCH v1 0/3] IntelSiliconPkg: Remove v1 PCH SPI PPI and Protocol
For the series, Reviewed-by: Sai Chaganty -Original Message- From: mikub...@linux.microsoft.com Sent: Wednesday, November 03, 2021 7:45 AM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Chaganty, Rangasai V ; Kethi Reddy, Deepika ; Esakkithevar, Kathappan ; Ni, Ray ; Oram, Isaac W Subject: [PATCH v1 0/3] IntelSiliconPkg: Remove v1 PCH SPI PPI and Protocol From: Michael Kubacki REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3717 V2 of the PCH SPI PPI and PCH SPI Protocol were recently added to IntelSiliconPkg. This change removes the v1 definitions. V2 is intended to better support multiple silicon generations which aligns with the goals of IntelSiliconPkg. Minor changes are also made in board packages that have stale references to the SPI PPI and Protocol. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Rangasai V Chaganty Cc: Deepika Kethi Reddy Cc: Kathappan Esakkithevar Cc: Ray Ni Cc: Isaac Oram Signed-off-by: Michael Kubacki Michael Kubacki (3): CometlakeOpenBoardPkg/PeiPolicyUpdateLib: Remove unneeded SPI header WhiskeylakeOpenBoardPkg/PeiPolicyUpdateLib: Remove unneeded SPI header IntelSiliconPkg: Remove SPI v1 PPI and Protocol definitions Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c | 1 - Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c | 1 - Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf | 1 - Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h | 25 -- Silicon/Intel/IntelSiliconPkg/Include/Protocol/Spi.h | 301 Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 7 - 6 files changed, 336 deletions(-) delete mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h delete mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Protocol/Spi.h -- 2.28.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#83286): https://edk2.groups.io/g/devel/message/83286 Mute This Topic: https://groups.io/mt/86792794/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2platforms][PATCH v2 1/1] IntelSiliconPkg: Add IntelDieInfoProtocol
Thanks for incorporating the feedback.
Few more minor comments based on the new patch:
1. The description of "DieIndex" perhaps should be modified to " Index of the
die in the package" to make it more apt.
2. The description of "DieId" perhaps should be modified to " Unique ID
specific to the die and the associated generation" to make it more apt.
Regards,
Sai
-Original Message-
From: Czajkowski, Maciej
Sent: Monday, October 18, 2021 6:57 AM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V
Subject: [edk2platforms][PATCH v2 1/1] IntelSiliconPkg: Add IntelDieInfoProtocol
Added IntelDieInfoProtocol header into IntelSiliconPkg tree.
The purpose is to have generic and unified interface for getting information
about dies installed in the system.
It will be implemented by silicon code.
Change-Id: Iedc414d435c27f37e6f12e7affd046a0a9e7e19d
Cc: Ray Ni
Cc: Rangasai V Chaganty
Signed-off-by: Maciej Czajkowski
---
Notes:
v2:
- added interface description
- added die specific GUIDs into .dec file
Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfoProtocol.h | 117
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 9 ++
2 files changed, 126 insertions(+)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfoProtocol.h
b/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfoProtocol.h
new file mode 100644
index ..954c9ee10c22
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfoProtoco
+++ l.h
@@ -0,0 +1,117 @@
+/** @file+ IntelDieInfoProtocol definition++ Copyright (c) 2021, Intel
Corporation. All rights reserved.+ SPDX-License-Identifier:
BSD-2-Clause-Patent++**/+#ifndef _DIE_INFO_PROTOCOL_H_+#define
_DIE_INFO_PROTOCOL_H_++typedef struct _INTEL_DIE_INFO_PROTOCOL
INTEL_DIE_INFO_PROTOCOL;+typedef INTEL_DIE_INFO_PROTOCOL
INTEL_DIE_INFO_PPI;++extern EFI_GUID gIntelDieInfoProtocolGuid;+extern EFI_GUID
gIntelDieInfoPpiGuid;++extern EFI_GUID gIntelDieInfoPchGuid;+extern EFI_GUID
gIntelDieInfoSocGuid;+extern EFI_GUID gIntelDieInfoIoGuid;+extern EFI_GUID
gIntelDieInfoCpuGuid;+extern EFI_GUID gIntelDieInfoGfxGuid;++#define
INTEL_DIE_INFO_PPI_GUID \+{ 0xAED8A0A1, 0xFDE6, 0x4CF2, { 0xA3, 0x85, 0x08,
0xF1, 0x25, 0xF2, 0x40, 0x37 }}++#define INTEL_DIE_INFO_PROTOCOL_GUID \+{
0xAED8A0A1, 0xFDE6, 0x4CF2, { 0xA3, 0x85, 0x08, 0xF1, 0x25, 0xF2, 0x40, 0x37
}}++#define DIE_INFO_PROTOCOL_REVISION 1+#define DIE_INFO_PROTOCOL_SIGNATURE
SIGNATURE_32 ('I', 'D', 'I', 'P')++#define DIE_INFO_PCH_GUID \+{ 0x62CB6D68,
0x4771, 0x4569, { 0x81, 0xFA, 0x1E, 0x99, 0x6E, 0xA9, 0x91, 0xC5 }}++#define
DIE_INFO_SOC_GUID \+{ 0x63287105, 0x578E, 0x4799, { 0xBE, 0x55, 0x5D, 0xDA,
0xCA, 0x03, 0x74, 0xD0 }}++#define DIE_INFO_IO_GUID \+{ 0x23DA4C74, 0x54A0,
0x4E01, { 0x83, 0xB1, 0x8C, 0xA7, 0x43, 0x43, 0x1F, 0xF0 }}++#define
DIE_INFO_CPU_GUID \+{ 0x6E5AF2E3, 0x5D84, 0x48F2, { 0x84, 0x28, 0x99, 0xE4,
0x93, 0x4F, 0x51, 0xE4 }}++#define DIE_INFO_GFX_GUID \+{ 0x1D3D2599, 0x7A1C,
0x4B1E, { 0x8C, 0xC5, 0x0F, 0x88, 0x27, 0xA0, 0x2E, 0xEC }}++/**+ Returns
pointer to constant string representing die name.+ Name is specific to die
type.++ @param[in] This Pointer to the DieInfoProtocol context structure+
@retval Pointer to the const string+**/+typedef+CONST CHAR8*+(EFIAPI
*INTEL_DIE_INFO_GET_DIE_NAME_STR) (+ IN INTEL_DIE_INFO_PROTOCOL *This+
);++/**+ Returns pointer to constant string representing stepping of the
die.++ @param[in] This Pointer to the DieInfoProtocol context structure+
@retval Pointer to the const string+**/+typedef+CONST CHAR8*+(EFIAPI
*INTEL_DIE_INFO_GET_STEPPING_STR) (+ IN INTEL_DIE_INFO_PROTOCOL *This+
);++/**+ Returns pointer to constant string representing SKU of the die.++
@param[in] This Pointer to the DieInfoProtocol context structure+ @retval
Pointer to the const string+**/+typedef+CONST CHAR8*+(EFIAPI
*INTEL_DIE_INFO_GET_SKU_STR) (+ IN INTEL_DIE_INFO_PROTOCOL *This+ );++/**+
Protocol/PPI definition.+ The purpose of this interface is to serve
die-specific informations in a unified, generic way.+ It will be produced by
silicon code per die, and can be consumed by any module that needs contained
information.++ Revision 1:+ - Initial version.+**/+struct
_INTEL_DIE_INFO_PROTOCOL {+ UINT32 Signature; ///<
Protocol signature+ UINT32 Revision; ///< Current
protocol revision+ /**+Type of the die that particular instance is
reffering to. See DIE_INFO_*_GUID+ **/+ EFI_GUID
Type;+ /**+Index of the die in the system.+ **/+ UINT32
DieIndex;+ /**+Generation and die specific ID number.+ **/+
UINT64 DieId;+ /**+Generation and die specific
stepping ID.+ **/+ UINT32 SteppingId;++
Re: [edk2-devel][edk2-platforms][PATCH V1 11/11] MinPlatformPkg/ReportFvLib: Remove obsolete PeiReportFvLib instance
Reviewed-by: Sai Chaganty
-Original Message-
From: devel@edk2.groups.io On Behalf Of Oram, Isaac W
Sent: Friday, October 15, 2021 2:26 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L
; Liming Gao ; Dong,
Eric
Subject: [edk2-devel][edk2-platforms][PATCH V1 11/11]
MinPlatformPkg/ReportFvLib: Remove obsolete PeiReportFvLib instance
All boards have been updated to use the new libraries or custom instances.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Liming Gao
Cc: Eric Dong
Signed-off-by: Isaac Oram
---
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
| 1 -
Platform/Intel/MinPlatformPkg/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.c
| 143
Platform/Intel/MinPlatformPkg/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf
| 50 ---
3 files changed, 194 deletions(-)
diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
index 1dfca06a10..58415326f4 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
@@ -93,7 +93,6 @@
# PEI phase common
#
FspWrapperPlatformLib|MinPlatformPkg/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf
-
ReportFvLib|MinPlatformPkg/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf
ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf
TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf
diff --git
a/Platform/Intel/MinPlatformPkg/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.c
b/Platform/Intel/MinPlatformPkg/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.c
deleted file mode 100644
index 833a77c702..00
---
a/Platform/Intel/MinPlatformPkg/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/** @file
- Source code file for Report Firmware Volume (FV) library
-
-Copyright (c) 2018 - 2020, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-VOID
-ReportPreMemFv (
- VOID
- )
-{
- ///
- /// Note : FSP FVs except FSP-T FV are installed in IntelFsp2WrapperPkg in
Dispatch mode.
- ///
- if (PcdGetBool(PcdFspWrapperBootMode)) {
-DEBUG ((DEBUG_INFO, "Install FlashFvFspT - 0x%x, 0x%x\n", PcdGet32
(PcdFlashFvFspTBase), PcdGet32 (PcdFlashFvFspTSize)));
-PeiServicesInstallFvInfo2Ppi (
- &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32
(PcdFlashFvFspTBase))->FileSystemGuid),
- (VOID *) (UINTN) PcdGet32 (PcdFlashFvFspTBase),
- PcdGet32 (PcdFlashFvFspTSize),
- NULL,
- NULL,
- 0
- );
- }
- DEBUG ((DEBUG_INFO, "Install FlashFvSecurity - 0x%x, 0x%x\n", PcdGet32
(PcdFlashFvSecurityBase), PcdGet32 (PcdFlashFvSecuritySize)));
- PeiServicesInstallFvInfo2Ppi (
-&(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32
(PcdFlashFvSecurityBase))->FileSystemGuid),
-(VOID *) (UINTN) PcdGet32 (PcdFlashFvSecurityBase),
-PcdGet32 (PcdFlashFvSecuritySize),
-NULL,
-NULL,
-0
-);
- if (PcdGet8 (PcdBootStage) >= 6) {
-DEBUG ((
- DEBUG_INFO,
- "Install FlashFvAdvancedPreMemory - 0x%x, 0x%x\n",
- PcdGet32 (PcdFlashFvAdvancedPreMemoryBase),
- PcdGet32 (PcdFlashFvAdvancedPreMemorySize)
- ));
-PeiServicesInstallFvInfo2Ppi (
- &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32
(PcdFlashFvAdvancedPreMemoryBase))->FileSystemGuid),
- (VOID *) (UINTN) PcdGet32 (PcdFlashFvAdvancedPreMemoryBase),
- PcdGet32 (PcdFlashFvAdvancedPreMemorySize),
- NULL,
- NULL,
- 0
- );
- }
-}
-
-VOID
-ReportPostMemFv (
- VOID
- )
-{
- EFI_STATUSStatus;
- EFI_BOOT_MODE BootMode;
-
- Status = PeiServicesGetBootMode ();
- ASSERT_EFI_ERROR (Status);
-
- ///
- /// Note : FSP FVs except FSP-T FV are installed in IntelFsp2WrapperPkg in
Dispatch mode.
- ///
-
- ///
- /// Build HOB for DXE
- ///
- if (BootMode == BOOT_IN_RECOVERY_MODE) {
-///
-/// Prepare the recovery service
-///
- } else {
-DEBUG ((DEBUG_INFO, "Install FlashFvPostMemory - 0x%x, 0x%x\n", PcdGet32
(PcdFlashFvPostMemoryBase), PcdGet32 (PcdFlashFvPostMemorySize)));
-PeiServicesInstallFvInfo2Ppi (
- &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32
(PcdFlashFvPostMemoryBase))->FileSystemGuid),
- (VOID *) (UINTN) PcdGet32 (PcdFlashFvPostMemoryBase),
- PcdGet32 (PcdFlashFvPostMemorySize),
- NULL,
- NULL,
- 0
- );
-DEBUG ((DEBUG_INFO, "Install FlashFvUefiBoot - 0x%x, 0x%x\n", PcdGet32
(PcdFlashFvUefiBootBase), PcdGet32 (PcdFlashFvUefiBootSize)));
-PeiServicesInstallFvInfo2Ppi (
- &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32
Re: [edk2-devel][edk2-platforms][PATCH V1 03/11] KabyOpenBoardPkg/ReportFvLib: Switch to new library instances.
Reviewed-by: Sai Chaganty -Original Message- From: devel@edk2.groups.io On Behalf Of Oram, Isaac W Sent: Friday, October 15, 2021 2:25 PM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Benjamin Doron ; Jeremy Soller Subject: [edk2-devel][edk2-platforms][PATCH V1 03/11] KabyOpenBoardPkg/ReportFvLib: Switch to new library instances. MinPlatformPkg shared ReportFvLib has split into PEI and SMM instances. Default versions are already included via CorePeiLib.dsc and CoreDxeLib.dsc Cc: Chasel Chiu Cc: Nate DeSimone Cc: Benjamin Doron Cc: Jeremy Soller Signed-off-by: Isaac Oram --- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc | 1 - Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc| 1 - Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 1 - 3 files changed, 3 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc index 97573ab2e6..77055b489a 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc @@ -173,7 +173,6 @@ PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf - ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf ### diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc index 7f276d3512..75e4f3b2e9 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc @@ -119,7 +119,6 @@ PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf - ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf ### diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index f64555e391..50f95a1300 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -161,7 +161,6 @@ PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf - ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf ### -- 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82561): https://edk2.groups.io/g/devel/message/82561 Mute This Topic: https://groups.io/mt/86528538/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][edk2-platforms][PATCH V1 05/11] WhiskeyLakeOpenBoardPkg/ReportFvLib: Switch to new library instances.
Reviewed-by: Sai Chaganty -Original Message- From: devel@edk2.groups.io On Behalf Of Oram, Isaac W Sent: Friday, October 15, 2021 2:25 PM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L Subject: [edk2-devel][edk2-platforms][PATCH V1 05/11] WhiskeyLakeOpenBoardPkg/ReportFvLib: Switch to new library instances. MinPlatformPkg shared ReportFvLib has split into PEI and SMM instances. Default versions are already included via CorePeiLib.dsc and CoreDxeLib.dsc Cc: Chasel Chiu Cc: Nate DeSimone Signed-off-by: Isaac Oram --- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc| 1 - Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc | 1 - 2 files changed, 2 deletions(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc index ee2aedd978..af5e0b2116 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc @@ -121,7 +121,6 @@ PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf - ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf ### diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc index b69cc8deb0..11ecd6b91f 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc @@ -121,7 +121,6 @@ PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf - ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf ### -- 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82560): https://edk2.groups.io/g/devel/message/82560 Mute This Topic: https://groups.io/mt/86528531/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][edk2-platforms][PATCH V1 08/11] SimicsOpenBoardPkg/ReportFvLib: Update ReportFvLib
Reviewed-by: Sai Chaganty
-Original Message-
From: devel@edk2.groups.io On Behalf Of Oram, Isaac W
Sent: Friday, October 15, 2021 2:26 PM
To: devel@edk2.groups.io
Cc: Agyeman, Prince
Subject: [edk2-devel][edk2-platforms][PATCH V1 08/11]
SimicsOpenBoardPkg/ReportFvLib: Update ReportFvLib
Update file naming to match other ReportFvLib implementations.
Also fix duplicate GUID for libary name.
Cc: Agyeman Prince
Signed-off-by: Isaac Oram
---
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
| 2 +-
Platform/Intel/SimicsOpenBoardPkg/Library/{PeiReportFvLib => ReportFvLib}/Fv.c
| 0
Platform/Intel/SimicsOpenBoardPkg/Library/{PeiReportFvLib/PeiReportFvLib.c =>
ReportFvLib/ReportFvLibPei.c} | 0
Platform/Intel/SimicsOpenBoardPkg/Library/{PeiReportFvLib/PeiReportFvLib.inf
=> ReportFvLib/ReportFvLibPei.inf} | 10 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
index 93a7d1df55..bfd0320daf 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
@@ -117,7 +117,6 @@
DxeLoadLinuxLib|$(BOARD_PKG)/Library/LoadLinuxLib/DxeLoadLinuxLib.inf
LogoLib|$(BOARD_PKG)/Library/DxeLogoLib/DxeLogoLib.inf
NvVarsFileLib|$(BOARD_PKG)/Library/NvVarsFileLib/NvVarsFileLib.inf
- ReportFvLib|$(BOARD_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf
SerializeVariablesLib|$(BOARD_PKG)/Library/SerializeVariablesLib/SerializeVariablesLib.inf
SiliconPolicyInitLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.inf
SiliconPolicyUpdateLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf
@@ -151,6 +150,7 @@
!endif
TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf
SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
+ ReportFvLib|$(BOARD_PKG)/Library/ReportFvLib/ReportFvLibPei.inf
[LibraryClasses.common.DXE_DRIVER]
diff --git a/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/Fv.c
b/Platform/Intel/SimicsOpenBoardPkg/Library/ReportFvLib/Fv.c
similarity index 100%
rename from Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/Fv.c
rename to Platform/Intel/SimicsOpenBoardPkg/Library/ReportFvLib/Fv.c
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c
b/Platform/Intel/SimicsOpenBoardPkg/Library/ReportFvLib/ReportFvLibPei.c
similarity index 100%
rename from
Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c
rename to Platform/Intel/SimicsOpenBoardPkg/Library/ReportFvLib/ReportFvLibPei.c
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf
b/Platform/Intel/SimicsOpenBoardPkg/Library/ReportFvLib/ReportFvLibPei.inf
similarity index 84%
rename from
Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf
rename to
Platform/Intel/SimicsOpenBoardPkg/Library/ReportFvLib/ReportFvLibPei.inf
index 5d2e39532c..524ecf2847 100644
---
a/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf
+++ b/Platform/Intel/SimicsOpenBoardPkg/Library/ReportFvLib/ReportFvLibP
+++ ei.inf
@@ -1,7 +1,7 @@
### @file
# Component information file for the Report Firmware Volume (FV) library.
#
-# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2021, Intel Corporation. All rights
+reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -9,11 +9,11 @@
[Defines]
INF_VERSION= 0x00010017
- BASE_NAME = PeiReportFvLib
- FILE_GUID = 44328FA5-E4DD-4A15-ABDF-C6584AC363D9
+ BASE_NAME = ReportFvLibPei
+ FILE_GUID = 409fc85f-aec0-4a8f-8126-9c36d201b5c4
VERSION_STRING = 1.0
MODULE_TYPE= PEIM
- LIBRARY_CLASS = ReportFvLib
+ LIBRARY_CLASS = ReportFvLib | PEIM
[LibraryClasses]
BaseMemoryLib
@@ -32,7 +32,7 @@
SimicsIch10Pkg/Ich10Pkg.dec
[Sources]
- PeiReportFvLib.c
+ ReportFvLibPei.c
Fv.c
[Pcd]
--
2.27.0.windows.1
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Re: [edk2-devel][edk2-platforms][PATCH V1 02/11] CometlakeOpenBoardPkg/ReportFvLib: Switch to new library instances.
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Friday, October 15, 2021 2:25 PM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Chaganty, Rangasai V ; Kethi Reddy, Deepika ; Esakkithevar, Kathappan Subject: [edk2-devel][edk2-platforms][PATCH V1 02/11] CometlakeOpenBoardPkg/ReportFvLib: Switch to new library instances. MinPlatformPkg shared ReportFvLib has split into PEI and SMM instances. Default versions are already included via CorePeiLib.dsc and CoreDxeLib.dsc Cc: Chasel Chiu Cc: Nate DeSimone Cc: Rangasai V Chaganty Cc: Deepika Kethi Reddy Cc: Kathappan Esakkithevar Signed-off-by: Isaac Oram --- Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc | 1 - 1 file changed, 1 deletion(-) diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc index 44a1bd54d6..3a92eb4575 100644 --- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc @@ -121,7 +121,6 @@ PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf - ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf ### -- 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82558): https://edk2.groups.io/g/devel/message/82558 Mute This Topic: https://groups.io/mt/86360110/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][edk2-platforms][PATCH V1 04/11] TigerLakeOpenBoardPkg/ReportFvLib: Switch to new library instances.
Reviewed-by: Sai Chaganty -Original Message- From: Oram, Isaac W Sent: Friday, October 15, 2021 2:25 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Desimone, Nathaniel L ; Luo, Heng Subject: [edk2-devel][edk2-platforms][PATCH V1 04/11] TigerLakeOpenBoardPkg/ReportFvLib: Switch to new library instances. MinPlatformPkg shared ReportFvLib has split into PEI and SMM instances. Default versions are already included via CorePeiLib.dsc and CoreDxeLib.dsc Cc: Sai Chaganty Cc: Nate DeSimone Cc: Heng Luo Signed-off-by: Isaac Oram --- Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc | 1 - 1 file changed, 1 deletion(-) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc index 1adf634034..7d6ea20986 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc @@ -67,7 +67,6 @@ [LibraryClasses.common] PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf - ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.inf PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf -- 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82557): https://edk2.groups.io/g/devel/message/82557 Mute This Topic: https://groups.io/mt/86360113/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2platforms][PATCH v1 1/1] IntelSiliconPkg: Add IntelDieInfoProtocol
Maciej,
Please add description of the interface in the comment block in line 103,
specifically covering the purpose of the interface, the producer and consumer
of this interface.
DieId's description says "Generation and die specific ID number". Can you add
some details on how a producer of this interface would know the values to be
assigned here? Does this contain any sort of encoding of generation and Die
specific ID in a single UINT64 ?
Same question for Stepping ID.
Any reason the die specific GUIDs are not declared in the .dec file?
Thanks,
Sai
-Original Message-
From: Czajkowski, Maciej
Sent: Thursday, October 07, 2021 8:24 AM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V
Subject: [edk2platforms][PATCH v1 1/1] IntelSiliconPkg: Add IntelDieInfoProtocol
Added IntelDieInfoProtocol header into IntelSiliconPkg tree.
The purpose is to have generic and unified interface for getting information
about dies installed in the system.
It will be implemented by silicon code.
Change-Id: I219f238a6245eb81dbaebe6b826304baf3f78dc2
Cc: Ray Ni
Cc: Rangasai V Chaganty
Signed-off-by: Maciej Czajkowski
---
Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfoProtocol.h | 109
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 2 +
2 files changed, 111 insertions(+)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfoProtocol.h
b/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfoProtocol.h
new file mode 100644
index ..6182947e82fc
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfoProtoco
+++ l.h
@@ -0,0 +1,109 @@
+/** @file+ IntelDieInfoProtocol definition++ Copyright (c) 2021, Intel
Corporation. All rights reserved.+ SPDX-License-Identifier:
BSD-2-Clause-Patent++**/+#ifndef _DIE_INFO_PROTOCOL_H_+#define
_DIE_INFO_PROTOCOL_H_++typedef struct _INTEL_DIE_INFO_PROTOCOL
INTEL_DIE_INFO_PROTOCOL;+typedef INTEL_DIE_INFO_PROTOCOL
INTEL_DIE_INFO_PPI;++extern EFI_GUID gIntelDieInfoProtocolGuid;+extern EFI_GUID
gIntelDieInfoPpiGuid;++#define INTEL_DIE_INFO_PPI_GUID \+{ 0xAED8A0A1, 0xFDE6,
0x4CF2, { 0xA3, 0x85, 0x08, 0xF1, 0x25, 0xF2, 0x40, 0x37 }}++#define
INTEL_DIE_INFO_PROTOCOL_GUID \+{ 0xAED8A0A1, 0xFDE6, 0x4CF2, { 0xA3, 0x85,
0x08, 0xF1, 0x25, 0xF2, 0x40, 0x37 }}++#define DIE_INFO_PROTOCOL_REVISION
1+#define DIE_INFO_PROTOCOL_SIGNATURE SIGNATURE_32 ('I', 'D', 'I',
'P')++#define DIE_INFO_PCH_GUID \+{ 0x62CB6D68, 0x4771, 0x4569, { 0x81, 0xFA,
0x1E, 0x99, 0x6E, 0xA9, 0x91, 0xC5 }}++#define DIE_INFO_SOC_GUID \+{
0x63287105, 0x578E, 0x4799, { 0xBE, 0x55, 0x5D, 0xDA, 0xCA, 0x03, 0x74, 0xD0
}}++#define DIE_INFO_IO_GUID \+{ 0x23DA4C74, 0x54A0, 0x4E01, { 0x83, 0xB1,
0x8C, 0xA7, 0x43, 0x43, 0x1F, 0xF0 }}++#define DIE_INFO_CPU_GUID \+{
0x6E5AF2E3, 0x5D84, 0x48F2, { 0x84, 0x28, 0x99, 0xE4, 0x93, 0x4F, 0x51, 0xE4
}}++#define DIE_INFO_GFX_GUID \+{ 0x1D3D2599, 0x7A1C, 0x4B1E, { 0x8C, 0xC5,
0x0F, 0x88, 0x27, 0xA0, 0x2E, 0xEC }}++/**+ Returns pointer to constant string
representing die name.+ Name is specific to die type.++ @param[in] This
Pointer to the DieInfoProtocol context structure+ @retval Pointer to the const
string+**/+typedef+CONST CHAR8*+(EFIAPI *INTEL_DIE_INFO_GET_DIE_NAME_STR) (+
IN INTEL_DIE_INFO_PROTOCOL *This+ );++/**+ Returns pointer to constant
string representing stepping of the die.++ @param[in] This Pointer to the
DieInfoProtocol context structure+ @retval Pointer to the const
string+**/+typedef+CONST CHAR8*+(EFIAPI *INTEL_DIE_INFO_GET_STEPPING_STR) (+
IN INTEL_DIE_INFO_PROTOCOL *This+ );++/**+ Returns pointer to constant
string representing SKU of the die.++ @param[in] This Pointer to the
DieInfoProtocol context structure+ @retval Pointer to the const
string+**/+typedef+CONST CHAR8*+(EFIAPI *INTEL_DIE_INFO_GET_SKU_STR) (+ IN
INTEL_DIE_INFO_PROTOCOL *This+ );++/**+ Protocol/PPI definition.++
Revision 1:+ - Initial version.+**/+struct _INTEL_DIE_INFO_PROTOCOL {+
UINT32 Signature; ///< Protocol signature+ UINT32
Revision; ///< Current protocol revision+ /**+Type
of the die that particular instance is reffering to. See DIE_INFO_*_GUID+ **/+
EFI_GUID Type;+ /**+Index of the die in the
system.+ **/+ UINT32 DieIndex;+ /**+Generation
and die specific ID number.+ **/+ UINT64 DieId;+
/**+Generation and die specific stepping ID.+ **/+ UINT32
SteppingId;++ INTEL_DIE_INFO_GET_DIE_NAME_STR GetNameStr;+
INTEL_DIE_INFO_GET_STEPPING_STR GetSteppingStr;+ INTEL_DIE_INFO_GET_SKU_STR
GetSkuStr;+};++#endif // _DIE_INFO_PROTOCOL_H_diff --git
a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index 2461ab8e06e7..7af784d77abc 100644
--- a/Silicon/Intel
Re: [edk2-devel] [PATCH] IntelSiliconPkg/FirmwareInterfaceTable: Define FIT 4 record
Reviewed-by: Sai Chaganty mailto:rangasai.v.chaga...@intel.com>> From: Holland, Michael Sent: Monday, October 11, 2021 11:48 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Ni, Ray Subject: [PATCH] IntelSiliconPkg/FirmwareInterfaceTable: Define FIT 4 record -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#81961): https://edk2.groups.io/g/devel/message/81961 Mute This Topic: https://groups.io/mt/86257812/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH] Define FIT 4 record
HI Michael, The actual changes are fine. A couple of comments on the patch format. * It's good to include the repository and package name, in the subject line [Repo Name: [Optional] Patch Version# #/total #] PackageName: * Commit message is missing the BugZilla reference. * CC maintainers as part of the patch mail. You can get more details on these guidelines here<https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process>. Regards, Sai From: Holland, Michael Sent: Tuesday, September 28, 2021 7:15 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Ni, Ray Subject: [PATCH] Define FIT 4 record -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#81717): https://edk2.groups.io/g/devel/message/81717 Mute This Topic: https://groups.io/mt/85940948/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms] [PATCH V1] TigerlakeOpenBoardPkg: Remove inaccurate comment
Reviewed-by: Sai Chaganty -Original Message- From: Desimone, Nathaniel L Sent: Saturday, August 28, 2021 6:19 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Luo, Heng Subject: [edk2-platforms] [PATCH V1] TigerlakeOpenBoardPkg: Remove inaccurate comment A comment in OpenBoardPkgPcd.dsc states that FSP dispatch mode is not supported, which is inaccurate. Cc: Sai Chaganty Cc: Heng Luo Signed-off-by: Nate DeSimone --- .../TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc | 1 - 1 file changed, 1 deletion(-) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc index a048efcc18..ebbbc7b9f9 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd +++ .dsc @@ -30,7 +30,6 @@ # # 0: FSP Wrapper is running in Dispatch mode. # 1: FSP Wrapper is running in API mode. - # Note: Dispatch mode is currently NOT supported for this board. # gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0 -- 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79924): https://edk2.groups.io/g/devel/message/79924 Mute This Topic: https://groups.io/mt/85220695/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-non-osi] [PATCH] ElkhartlakeSiliconBinPkg: Update EHL microcode
Reviewed-by: Sai Chaganty
-Original Message-
From: Ong, Kok Tong
Sent: Tuesday, August 24, 2021 8:33 PM
To: devel@edk2.groups.io
Cc: Ong, Kok Tong ; Desimone, Nathaniel L
; Chaganty, Rangasai V
; Lim, Jin Jhu
Subject: [edk2-devel] [edk2-non-osi] [PATCH] ElkhartlakeSiliconBinPkg: Update
EHL microcode
Updated "production" version m0190661_0014 of microcode
Signed-off-by: Ong Kok Tong
Cc: Nate DeSimone
Cc: Sai Chaganty
Cc: jinjhuli
---
.../Microcode/MicrocodeUpdates.inf | 2 +-
.../Microcode/m0190661_0011.mcb | Bin 19456 -> 0 bytes
.../Microcode/m0190661_0014.mcb | Bin 0 -> 20480 bytes
3 files changed, 1 insertion(+), 1 deletion(-)
delete mode 100644
Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/m0190661_0011.mcb
create mode 100644
Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/m0190661_0014.mcb
diff --git
a/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
b/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
index afbb28b..8fd626b 100644
--- a/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
+++ b/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf
@@ -15,4 +15,4 @@
MODULE_TYPE= USER_DEFINED
[Sources]
- m0190661_0011.mcb
+ m0190661_0014.mcb
diff --git
a/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/m0190661_0011.mcb
b/Silicon/Intel/ElkhartlakeSiliconBinPkg/Microcode/m0190661_0011.mcb
deleted file mode 100644
index
8140fcc082340983a439fec96732faa7678ef6e1..
GIT binary patch
literal 0
HcmV?d1
literal 19456
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ze<{Dh>+la=l|mV
zm*@Y5|M~piaAZ(pX}#1Ws#Yu3N}hVq%a){NwTULgqb4Qyt}7N8U!7sZ+eO2)R6(XK
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zltH*1wY*B#$FBzJ)wjWCT^z!)vXM2gIx2N)qOwu5m+XE
z7I8>Wa61#OfN1uE_rBw5k`WR{KvLN@mPr{ej_!#qQ#uZt13N6Y_eiOwNuQdTN-}J_
zc)#S}HDM`$zx9U6#`vgBTlzvCq@YTBv9>m@B|7kp+Snh@aQ4ATe9PEWT9GXxYYt{t
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zQje5p1Vq+ZoBp1th;;?PCP9o%2lboFATuEt`rq46?CDimQ-lYNJIF@
z=fj7`x~(riNvsN^g;IEqb0Z29E7d=b9h8ipVkJ-(iU|xN7F7$BcgVTyE}~|sUH-vV
zepVN*AsUh~huh)#gaS>}B8yivmnuc^f5Nz5n9&|9vlE&1t)Pg`y6))Wij%Ty(O
zKsJv!p*#c=-W0!FO&#
Re: [edk2-devel] [edk2-non-osi] [PATCH] Maintainers.txt: Modify maintainer role for EHL
Reviewed-by: Sai Chaganty < rangasai.v.chaga...@intel.com > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79812): https://edk2.groups.io/g/devel/message/79812 Mute This Topic: https://groups.io/mt/85108528/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH v5 23/46] TigerlakeOpenBoardPkg: Update SpiFvbService & SpiFlashCommonLib
Reviewed-by: Sai Chaganty
-Original Message-
From: mikub...@linux.microsoft.com
Sent: Monday, August 02, 2021 7:39 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Desimone, Nathaniel L
; Luo, Heng
Subject: [edk2-platforms][PATCH v5 23/46] TigerlakeOpenBoardPkg: Update
SpiFvbService & SpiFlashCommonLib
From: Michael Kubacki
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307
Updates TigerlakeOpenBoardPkg to use the SmmSpiFlashCommonLib instance in
IntelSiliconPkg and the SpiFvbServiceSmm driver in IntelSiliconPkg.
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Heng Luo
Signed-off-by: Michael Kubacki
Reviewed-by: Nate DeSimone
---
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc | 7
+-- Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf |
2 +-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git
a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
index 1adf63403450..758b966fee81 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.ds
+++ c
@@ -173,7 +173,7 @@ [LibraryClasses.X64]
!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc
[LibraryClasses.X64.DXE_SMM_DRIVER]
-
SpiFlashCommonLib|$(PLATFORM_BOARD_PACKAGE)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
+
+ SpiFlashCommonLib|IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiF
+ lashCommonLib.inf
!if $(TARGET) == DEBUG
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf
!endif
@@ -297,6 +297,10 @@ [Components.X64]
!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc
$(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+!endif
+
#
# SmmAccess
#
@@ -326,7 +330,6 @@ [Components.X64]
NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
}
- $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
$(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { diff --git
a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf
b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf
index e3b2f048524c..b802c2167d06 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fd
+++ f
@@ -434,7 +434,7 @@ [FV.FvOsBootUncompact] !if
gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE INF
$(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
-INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
--
2.28.0.windows.1
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Re: [edk2-devel] [edk2-platforms][PATCH v5 31/46] TigerlakeOpenBoardPkg: Remove SmmSpiFlashCommonLib
Reviewed-by: Sai Chaganty
-Original Message-
From: mikub...@linux.microsoft.com
Sent: Monday, August 02, 2021 7:39 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Desimone, Nathaniel L
; Luo, Heng
Subject: [edk2-platforms][PATCH v5 31/46] TigerlakeOpenBoardPkg: Remove
SmmSpiFlashCommonLib
From: Michael Kubacki
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307
The library has been consolidated with instances in other Intel silicon
packages as a single instance in IntelSiliconPkg
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Heng Luo
Signed-off-by: Michael Kubacki
Reviewed-by: Nate DeSimone
---
Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
| 210
Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
| 58 --
Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
| 49 -
3 files changed, 317 deletions(-)
diff --git
a/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
deleted file mode 100644
index f86896dd1ff5..
---
a/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/** @file
- Wrap EFI_SPI_PROTOCOL to provide some library level interfaces
- for module use.
-
- Copyright (c) 2021, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent -**/
-
-#include
-#include
-#include
-
-PCH_SPI_PROTOCOL *mSpiProtocol;
-
-//
-// Variables for boottime and runtime usage.
-//
-UINTN mBiosAreaBaseAddress = 0;
-UINTN mBiosSize= 0;
-UINTN mBiosOffset = 0;
-
-/**
- Enable block protection on the Serial Flash device.
-
- @retval EFI_SUCCESS Opertion is successful.
- @retval EFI_DEVICE_ERROR If there is any device errors.
-
-**/
-EFI_STATUS
-EFIAPI
-SpiFlashLock (
- VOID
- )
-{
- return EFI_SUCCESS;
-}
-
-/**
- Read NumBytes bytes of data from the address specified by
- PAddress into Buffer.
-
- @param[in] Address The starting physical address of the read.
- @param[in,out] NumBytes On input, the number of bytes to read. On
output, the number
-of bytes actually read.
- @param[out] BufferThe destination data buffer for the read.
-
- @retval EFI_SUCCESS Operation is successful.
- @retval EFI_DEVICE_ERROR If there is any device errors.
-
-**/
-EFI_STATUS
-EFIAPI
-SpiFlashRead (
- IN UINTNAddress,
- IN OUT UINT32 *NumBytes,
- OUT UINT8*Buffer
- )
-{
- ASSERT ((NumBytes != NULL) && (Buffer != NULL));
- if ((NumBytes == NULL) || (Buffer == NULL)) {
-return EFI_INVALID_PARAMETER;
- }
-
- //
- // This function is implemented specifically for those platforms
- // at which the SPI device is memory mapped for read. So this
- // function just do a memory copy for Spi Flash Read.
- //
- CopyMem (Buffer, (VOID *) Address, *NumBytes);
-
- return EFI_SUCCESS;
-}
-
-/**
- Write NumBytes bytes of data from Buffer to the address specified by
- PAddresss.
-
- @param[in] Address The starting physical address of the write.
- @param[in,out] NumBytesOn input, the number of bytes to write. On
output,
- the actual number of bytes written.
- @param[in] Buffer The source data buffer for the write.
-
- @retval EFI_SUCCESSOperation is successful.
- @retval EFI_DEVICE_ERROR If there is any device errors.
- @retval EFI_INVALID_PARAMETER Invalid parameter.
-
-**/
-EFI_STATUS
-EFIAPI
-SpiFlashWrite (
- IN UINTN Address,
- IN OUT UINT32 *NumBytes,
- IN UINT8 *Buffer
- )
-{
- EFI_STATUSStatus;
- UINTN Offset;
- UINT32Length;
- UINT32RemainingBytes;
-
- ASSERT ((NumBytes != NULL) && (Buffer != NULL));
- if ((NumBytes == NULL) || (Buffer == NULL)) {
-return EFI_INVALID_PARAMETER;
- }
-
- ASSERT (Address >= mBiosAreaBaseAddress);
- if (Address < mBiosAreaBaseAddress) {
-return EFI_INVALID_PARAMETER;
- }
-
- Offset = Address - mBiosAreaBaseAddress;
-
- ASSERT ((*NumBytes + Offset) <= mBiosSize);
- if ((*NumBytes + Offset) > mBiosSize) {
-return EFI_INVALID_PARAMETER;
- }
-
- Status = EFI_SUCCESS;
- RemainingBytes = *NumBytes;
-
-
- while (RemainingBytes > 0) {
-if (RemainingBytes > SECTOR_SIZE_4KB) {
- Length = SECTOR_SIZE_4KB;
-} else {
- Length = RemainingBytes;
-}
-Status = mSpiProtocol->FlashWrite (
- mSpiProtocol,
-
Re: [edk2-devel] [edk2-platforms][PATCH v1 1/1] IntelSiliconPkg/PeiSmmAccessLib: Remove S3 requirement
I've looked into Intel Platforms and we have atleast one platform that could potentially get impacted. However, it can be addressed by adding BootMode checks by the caller. The more important question, as Ray pointed out is, are there security implications in installing these PPIs in normal boot, that justifies PeiSmmAccessLib to absorb the bootmode checks. If there are then it would be interesting to see how to support rationale #1 below - "Practical use cases exist to require this PPI in cases other than the boot mode being set to BOOT_ON_S3_RESUME". Regards, Sai -Original Message- From: Michael Kubacki Sent: Wednesday, August 18, 2021 11:47 AM To: devel@edk2.groups.io; Ni, Ray ; mikub...@linux.microsoft.com; Chaganty, Rangasai V ; Yao, Jiewen Subject: Re: [edk2-devel] [edk2-platforms][PATCH v1 1/1] IntelSiliconPkg/PeiSmmAccessLib: Remove S3 requirement Jiewen/Sai, are you thinking about this? Thanks, Michael On 8/12/2021 1:20 AM, Ni, Ray wrote: > Michael, > I need Jiewen's input on why MmAccess and MmCommunication PPIs were not > installed in normal boot path. Without understanding the reason, I don't have > confidence to approve the change. > > Sai, > Do you see other impacts to Intel platforms with this behavior change? > > Thanks, > Ray > > -Original Message- > From: devel@edk2.groups.io On Behalf Of Michael > Kubacki > Sent: Tuesday, August 10, 2021 11:36 PM > To: devel@edk2.groups.io; Ni, Ray ; Chaganty, > Rangasai V > Cc: Yao, Jiewen > Subject: Re: [edk2-devel] [edk2-platforms][PATCH v1 1/1] > IntelSiliconPkg/PeiSmmAccessLib: Remove S3 requirement > > Installation is a platform decision. The buried dependency on boot mode in > this particular function is just a roadblock platforms have to work around. > The role of this API is to install the PPI. > > Thanks, > Michael > > On 8/9/2021 9:47 PM, Ni, Ray wrote: >> Michael, >> Allowing the gPeiSmmAccessPpiGuid PPI installation in normal boot >> will further allow gEfiPeiSmmCommunicationPpiGuid installation in normal >> path, while without your change neither of the PPIs is installed in normal >> boot. >> >> + Jiewen for potential security concern. >> >> Thanks, >> Ray >> >>> -Original Message- >>> From: Chaganty, Rangasai V >>> Sent: Tuesday, August 10, 2021 6:46 AM >>> To: mikub...@linux.microsoft.com; devel@edk2.groups.io >>> Cc: Ni, Ray >>> Subject: RE: [edk2-platforms][PATCH v1 1/1] >>> IntelSiliconPkg/PeiSmmAccessLib: Remove S3 requirement >>> >>> Reviewed-by: Sai Chaganty >>> >>> -Original Message- >>> From: mikub...@linux.microsoft.com >>> Sent: Monday, August 09, 2021 6:40 AM >>> To: devel@edk2.groups.io >>> Cc: Ni, Ray ; Chaganty, Rangasai V >>> >>> Subject: [edk2-platforms][PATCH v1 1/1] >>> IntelSiliconPkg/PeiSmmAccessLib: Remove S3 requirement >>> >>> From: Michael Kubacki >>> >>> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3539 >>> >>> PeiInstallSmmAccessPpi() currently requires the boot mode be set to S3 to >>> actually install gEfiPeiMmAccessPpiGuid. >>> >>> This change removes this requirement in the function implementation for two >>> reasons: >>> >>> 1. Practical use cases exist to require this PPI in cases other than >>> the boot mode being set to BOOT_ON_S3_RESUME. >>> >>> 2. It is poor API design to implicitly bury this requirement within >>> a function whose responsibility is to install the PPI. The caller >>> can easily place arbitrary constraints around whether to call >>> based on conditions such as the boot mode being >>> BOOT_ON_S3_RESUME. >>> >>> Cc: Ray Ni >>> Cc: Rangasai V Chaganty >>> Signed-off-by: Michael Kubacki >>> --- >>> >>> Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c >>> | 12 >>>1 file changed, 12 deletions(-) >>> >>> diff --git >>> a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAcce >>> s >>> sLib/PeiSmmAccessLib.c >>> b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAcce >>> s sLib/PeiSmmAccessLib.c index d9bf4fba983e..4df0d695fdaf 100644 >>> --- >>> a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAcce >>> s >>> sLib/PeiSmmAccessLib.c >>> +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmm &g
Re: [edk2-devel] [edk2-platforms][PATCH v1] KabylakeSiliconPkg/PchPmcLib: Add GetSleepTypeAfterWakeup()
Reviewed-by: Sai Chaganty
-Original Message-
From: Desimone, Nathaniel L
Sent: Wednesday, August 11, 2021 6:22 PM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Michael Kubacki
; Chiu, Chasel ;
Chaganty, Rangasai V ; Benjamin Doron
Subject: [edk2-platforms][PATCH v1] KabylakeSiliconPkg/PchPmcLib: Add
GetSleepTypeAfterWakeup()
From: Michael Kubacki
Adds the capability to get the system sleep type after wakeup to PchPmcLib in
KabylakeSiliconPkg.
This is needed by platforms to determine the Sx resume state.
Cc: Chasel Chiu
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Benjamin Doron
Signed-off-by: Michael Kubacki
---
Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PchPmcLib.c
| 54
Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPmcLib.h
| 15 ++
Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
| 4 ++
3 files changed, 73 insertions(+)
diff --git
a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PchPmcLib.c
b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PchPmcLib.c
index 790af0a7a1..3c9c4c2a2d 100644
---
a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PchPmcLib.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/Pc
+++ hPmcLib.c
@@ -128,3 +128,57 @@ PchIsRtcBatteryGood (
}
return FALSE;
}
+
+/**
+ Returns the sleep type after system wakeup.
+
+ @param[out] SleepType Sleep type to be returned.
+
+ @retval TRUE A wake event occurred without power failure.
+ @retval FALSE Power failure occurred or not a wakeup.
+
+**/
+BOOLEAN
+EFIAPI
+GetSleepTypeAfterWakeup (
+ OUT UINT32*SleepType
+ )
+{
+ UINT16Pm1Sts;
+ UINT32Pm1Cnt;
+ UINTN PmcBaseAddress;
+
+ PmcBaseAddress = MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_PMC,
+ PCI_FUNCTION_NUMBER_PCH_PMC
+ );
+
+ ///
+ /// Read the ACPI registers
+ ///
+ Pm1Sts = IoRead16 (PcdGet16 (PcdAcpiBaseAddress) +
+ R_PCH_ACPI_PM1_STS); Pm1Cnt = IoRead32 (PcdGet16
+ (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_CNT);
+
+ ///
+ /// Get sleep type if a wake event occurred and there is no power
+ failure and reset /// if ((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) != 0) {
+if ((MmioRead16 (PmcBaseAddress + R_PCH_PMC_GEN_PMCON_B) &
(B_PCH_PMC_GEN_PMCON_B_RTC_PWR_STS | B_PCH_PMC_GEN_PMCON_B_PWR_FLR)) == 0) {
+ *SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;
+
+ return TRUE;
+} else {
+ ///
+ /// Clear Wake Status (WAK_STS) and Sleep Type (SLP_TYP)
+ ///
+ IoWrite16 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_STS,
B_PCH_ACPI_PM1_STS_WAK);
+ Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;
+ IoWrite32 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_CNT,
+ Pm1Cnt);
+
+ return FALSE;
+}
+ }
+
+ return FALSE;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPmcLib.h
b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPmcLib.h
index ec98e07100..f84606d31c 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPmcLib.h
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPmcLib.h
@@ -41,4 +41,19 @@ PchIsRtcBatteryGood (
VOID
);
+/**
+ Returns the sleep type after system wakeup.
+
+ @param[out] SleepType Sleep type to be returned.
+
+ @retval TRUE A wake event occurred without power failure.
+ @retval FALSE Power failure occurred or not a wakeup.
+
+**/
+BOOLEAN
+EFIAPI
+GetSleepTypeAfterWakeup (
+ OUT UINT32*SleepType
+ );
+
#endif // _PCH_PMC_LIB_H_
diff --git
a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
index 8b46a59b67..1e6103f4ca 100644
---
a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/Pe
+++ iDxeSmmPchPmcLib.inf
@@ -33,5 +33,9 @@ MdePkg/MdePkg.dec
KabylakeSiliconPkg/SiPkg.dec
+[Pcd]
+gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+
+
[Sources]
PchPmcLib.c
--
2.29.2.windows.2
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Re: [edk2-devel] [edk2-platforms][PATCH v1 1/1] IntelSiliconPkg/PeiSmmAccessLib: Remove S3 requirement
Reviewed-by: Sai Chaganty
-Original Message-
From: mikub...@linux.microsoft.com
Sent: Monday, August 09, 2021 6:40 AM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V
Subject: [edk2-platforms][PATCH v1 1/1] IntelSiliconPkg/PeiSmmAccessLib: Remove
S3 requirement
From: Michael Kubacki
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3539
PeiInstallSmmAccessPpi() currently requires the boot mode be set to S3 to
actually install gEfiPeiMmAccessPpiGuid.
This change removes this requirement in the function implementation for two
reasons:
1. Practical use cases exist to require this PPI in cases other than
the boot mode being set to BOOT_ON_S3_RESUME.
2. It is poor API design to implicitly bury this requirement within
a function whose responsibility is to install the PPI. The caller
can easily place arbitrary constraints around whether to call
based on conditions such as the boot mode being
BOOT_ON_S3_RESUME.
Cc: Ray Ni
Cc: Rangasai V Chaganty
Signed-off-by: Michael Kubacki
---
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
| 12
1 file changed, 12 deletions(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
index d9bf4fba983e..4df0d695fdaf 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAcce
+++ ssLib/PeiSmmAccessLib.c
@@ -252,19 +252,7 @@ PeiInstallSmmAccessPpi (
EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock;
SMM_ACCESS_PRIVATE_DATA *SmmAccessPrivate;
VOID*HobList;
- EFI_BOOT_MODE BootMode;
- Status = PeiServicesGetBootMode ();
- if (EFI_ERROR (Status)) {
-//
-// If not in S3 boot path. do nothing
-//
-return EFI_SUCCESS;
- }
-
- if (BootMode != BOOT_ON_S3_RESUME) {
-return EFI_SUCCESS;
- }
//
// Initialize private data
//
--
2.28.0.windows.1
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Re: [edk2-devel] [edk2-platforms][PATCH v1 1/1] IntelSiliconPkg: Add BaseSmmAccessLibNull
Reviewed-by: Sai Chaganty
-Original Message-
From: mikub...@linux.microsoft.com
Sent: Monday, August 09, 2021 7:16 AM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V
Subject: [edk2-platforms][PATCH v1 1/1] IntelSiliconPkg: Add
BaseSmmAccessLibNull
From: Michael Kubacki
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3540
Adds a NULL instance of SmmAccessLib.
Cc: Ray Ni
Cc: Rangasai V Chaganty
Signed-off-by: Michael Kubacki
---
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/BaseSmmAccessLibNull/BaseSmmAccessLibNull.c
| 33
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/BaseSmmAccessLibNull/BaseSmmAccessLibNull.inf
| 26 +++
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
| 1 +
3 files changed, 60 insertions(+)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/BaseSmmAccessLibNull/BaseSmmAccessLibNull.c
b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/BaseSmmAccessLibNull/BaseSmmAccessLibNull.c
new file mode 100644
index ..f5ad306b380b
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/BaseSmmAcc
+++ essLibNull/BaseSmmAccessLibNull.c
@@ -0,0 +1,33 @@
+/** @file
+ A NULL library instance of SmmAccessLib.
+
+ Copyright (c) 2019 - 2020, Intel Corporation. All rights
+ reserved. Copyright (c) Microsoft Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+
+/**
+ This function is to install an SMM Access PPI
+
+ @retval EFI_SUCCESS - Ppi successfully started and installed.
+ @retval EFI_NOT_FOUND - Ppi can't be found.
+ @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to
initialize the driver.
+ @retval EFI_UNSUPPORTED - The PPI was not installed and installation
is unsupported in
+ this instance of function implementation.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiInstallSmmAccessPpi (
+ VOID
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/BaseSmmAccessLibNull/BaseSmmAccessLibNull.inf
b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/BaseSmmAccessLibNull/BaseSmmAccessLibNull.inf
new file mode 100644
index ..7fd3b0b89655
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/BaseSmmAcc
+++ essLibNull/BaseSmmAccessLibNull.inf
@@ -0,0 +1,26 @@
+## @file
+# A NULL library instance of SmmAccessLib.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved. #
+Copyright (c) Microsoft Corporation. # SPDX-License-Identifier:
+BSD-2-Clause-Patent # ##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseSmmAccessLibNull
+FILE_GUID = C1A14AB6-B757-4046-9B92-9DCE1A2154C6
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = SmmAccessLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses]
+ DebugLib
+
+[Sources]
+ BaseSmmAccessLibNull.c
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
index 1092371d848e..dd0928ec58f3 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
@@ -90,6 +90,7 @@ [Components]
IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdateDxe.inf
IntelSiliconPkg/Feature/Capsule/Library/MicrocodeFlashAccessLibNull/MicrocodeFlashAccessLibNull.inf
IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.inf
+
+ IntelSiliconPkg/Feature/SmmAccess/Library/BaseSmmAccessLibNull/BaseSmm
+ AccessLibNull.inf
IntelSiliconPkg/Library/PeiDxeSmmBootMediaLib/PeiFirmwareBootMediaLib.inf
IntelSiliconPkg/Library/PeiDxeSmmBootMediaLib/DxeSmmFirmwareBootMediaLib.inf
IntelSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
--
2.28.0.windows.1
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Re: [edk2-devel] [edk2-platforms][PATCH v1 2/4] CometlakeOpenBoardPkg/Acpi: BoardAcpiDxe also installs all PcdAcpiTableStorageFile
Hi Benjamin, The problem statement is not clear to me. Could you share any background for this change - RFC, Bugzilla etc? Thanks, Sai Chaganty -Original Message- From: Benjamin Doron Sent: Wednesday, August 04, 2021 12:59 PM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Chaganty, Rangasai V ; Kethi Reddy, Deepika ; Esakkithevar, Kathappan Subject: [edk2-platforms][PATCH v1 2/4] CometlakeOpenBoardPkg/Acpi: BoardAcpiDxe also installs all PcdAcpiTableStorageFile Follow AcpiPlatformDxe (from which this module is derived) and install all ACPI tables added by board. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Rangasai V Chaganty Cc: Deepika Kethi Reddy Cc: Kathappan Esakkithevar Signed-off-by: Benjamin Doron --- Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c | 1 + Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf | 2 ++ 2 files changed, 3 insertions(+) diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c index 7fc71bca644a..11c1d619d1ea 100644 --- a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c +++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDx +++ e.c @@ -271,6 +271,7 @@ InstallAcpiBoard ( // Platform ACPI Tables // PublishAcpiTablesFromFv ();+ PublishAcpiTablesFromFv (PcdGetPtr (PcdAcpiTableStorageFile));// // This protocol publish must be done after PublishAcpiTablesFromFv.diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf index 09b67376fbc1..e201964a6896 100644 --- a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf +++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDx +++ e.inf @@ -62,6 +62,8 @@ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile+ [Depex] gEfiAcpiTableProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND-- 2.31.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78682): https://edk2.groups.io/g/devel/message/78682 Mute This Topic: https://groups.io/mt/84670594/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2] IntelSiliconPkg/VTd: Fix variables may be used uninitialized
Reviewed-by: Sai Chaganty
-Original Message-
From: Hsu, WesleyX
Sent: Thursday, July 29, 2021 12:23 AM
To: devel@edk2.groups.io
Cc: Hsu, WesleyX ; Chan, Amy ; Yeh,
HerbX ; Peng, NickX ; Ni, Ray
; Chaganty, Rangasai V
Subject: [PATCH v2] IntelSiliconPkg/VTd: Fix variables may be used uninitialized
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3491
Initialize several variables which may be used uninitialized after adding
"-ffat-lto-objects" option in GCC5 tool chain.
Change-Id: Ib2684aa70637d449f8bbddb18cf0a458a2742909
Signed-off-by: WesleyX Hsu
Cc: Amy Chan
Cc: HerbX Yeh
Cc: NickX Peng
Cc: Ray Ni
Cc: Rangasai V Chaganty
---
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c |
7 ++-
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c |
9 +++--
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c
index 341e2beb..6676b2a9 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Translat
+++ ionTable.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2020 - 2021, Intel Corporation. All rights
+ reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -111,6 +111,11 @@ CreateSecondLevelPagingEntryTable (
return EFI_SUCCESS;
}
+ Lvl4PagesStart = 0;
+ Lvl4PagesEnd = 0;
+ Lvl4PtEntry= NULL;
+ Lvl5PtEntry= NULL;
+
BaseAddress = ALIGN_VALUE_LOW (MemoryBase, SIZE_2MB);
EndAddress = ALIGN_VALUE_UP (MemoryLimit, SIZE_2MB);
DEBUG ((DEBUG_INFO, "CreateSecondLevelPagingEntryTable: BaseAddress -
0x%016lx, EndAddress - 0x%016lx\n", BaseAddress, EndAddress)); diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index d152039f..ca5f65a8 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationT
+++ able.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights
+ reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -133,7 +133,7 @@ CreateContextEntry (
mVtdUnitInformation[VtdIndex].Is5LevelPaging = TRUE;
if ((mAcpiDmarTable->HostAddressWidth <= 48) &&
((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) != 0)) {
-mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE;
+mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE;
}
} else if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) {
DEBUG((DEBUG_ERROR, " Page-table type is not supported on VTD %d
\n", VtdIndex)); @@ -199,6 +199,11 @@ CreateSecondLevelPagingEntryTable (
return EFI_SUCCESS;
}
+ Lvl4PagesStart = 0;
+ Lvl4PagesEnd = 0;
+ Lvl4PtEntry= NULL;
+ Lvl5PtEntry= NULL;
+
BaseAddress = ALIGN_VALUE_LOW(MemoryBase, SIZE_2MB);
EndAddress = ALIGN_VALUE_UP(MemoryLimit, SIZE_2MB);
DEBUG ((DEBUG_INFO,"CreateSecondLevelPagingEntryTable: BaseAddress -
0x%016lx, EndAddress - 0x%016lx\n", BaseAddress, EndAddress));
--
2.32.0.windows.2
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Re: [edk2-devel] [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0
Digant,
The notation "PATCH 3/3" indicates part 3 of a 3 patch series.
However since this is a single patch, the subject line could simply indicate
[PATCH v3]. Something to consider for future reviews.
Thanks,
Sai
-Original Message-----
From: Chaganty, Rangasai V
Sent: Wednesday, July 28, 2021 10:48 AM
To: Solanki, Digant H ; devel@edk2.groups.io
Cc: Ni, Ray ; S, Ashraf Ali
Subject: RE: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD
OpRegion v3.0
Reviewed-by: Sai Chaganty
-Original Message-
From: Solanki, Digant H
Sent: Thursday, July 22, 2021 4:47 AM
To: devel@edk2.groups.io
Cc: Solanki, Digant H ; Ni, Ray ;
Chaganty, Rangasai V ; S, Ashraf Ali
Subject: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD
OpRegion v3.0
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3426
- There are many OpRegion fields obsoleted in MBOX1
- MBOX2 is re-purposed for Backlight related fields for dual LFP.
- Backlight related fields moved to MBOX2 from MBOX3 and some fields are
obsoleted in MBOX3.
Signed-off-by: Digant H Solanki
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Ashraf Ali S
---
Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h | 101
+
1 file changed, 101 insertions(+)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h
b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h
new file mode 100644
index 00..c9948ab55f
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion
+++ 30.h
@@ -0,0 +1,101 @@
+/** @file
+ IGD OpRegion definition from Intel Integrated Graphics Device
+OpRegion
+ Specification based on version 3.0.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _IGD_OPREGION_3_0_H_
+#define _IGD_OPREGION_3_0_H_
+
+#include "IgdOpRegion.h"
+
+#define IGD_OPREGION_HEADER_MBOX2_VER_3_0 BIT5
+
+#pragma pack(1)
+///
+/// OpRegion Mailbox 1 - Public ACPI Methods /// Offset 0x100, Size
+0x100 /// typedef struct {
+ UINT32 DRDY; ///< Offset 0x100 Driver Readiness
+ UINT32 CSTS; ///< Offset 0x104 Status
+ UINT32 CEVT; ///< Offset 0x108 Current Event
+ UINT8 RM11[0x14];///< Offset 0x10C Reserved Must be Zero
+ UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List
+ UINT32 CPDL[8]; ///< Offset 0x140 obsolete
+ UINT32 CADL[8]; ///< Offset 0x160 obsolete
+ UINT32 NADL[8]; ///< Offset 0x180 obsolete
+ UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out
+ UINT32 TIDX; ///< Offset 0x1A4 obsolete
+ UINT32 CHPD; ///< Offset 0x1A8 obsolete
+ UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator
+ UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator
+ UINT32 SXSW; ///< Offset 0x1B4 obsolete
+ UINT32 EVTS; ///< Offset 0x1B8 obsolete
+ UINT32 CNOT; ///< Offset 0x1BC obsolete
+ UINT32 NRDY; ///< Offset 0x1C0 Driver Status
+ UINT8 DID2[0x1C];///< Offset 0x1C4 Extended Supported Devices ID List
(DOD)
+ UINT8 CPD2[0x1C];///< Offset 0x1E0 obsolete
+ UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero
+} IGD_OPREGION_MBOX1_VER_3_0;
+
+///
+/// OpRegion Mailbox 2 - Backlight communication /// Offset 0x200, Size
+0x100 /// typedef struct {
+ UINT32 BCL1; ///< Offset 0x200 Backlight Brightness for LFP1
+ UINT32 BCL2; ///< Offset 0x204 Backlight Brightness for LFP2
+ UINT32 CBL1; ///< Offset 0x208 Current User Brightness Level for
LFP1
+ UINT32 CBL2; ///< Offset 0x20C Current User Brightness Level for
LFP2
+ UINT32 BCM1[0x1E];///< Offset 0x210 Backlight Brightness Levels Duty
Cycle Mapping Table for LFP1
+ UINT32 BCM2[0x1E];///< Offset 0x288 Backlight Brightness Levels Duty
Cycle Mapping Table for LFP2
+} IGD_OPREGION_MBOX2_VER_3_0;
+
+///
+/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support ///
+Offset 0x300, Size 0x100 /// typedef struct {
+ UINT32 ARDY; ///< Offset 0x300 obsolete
+ UINT32 ASLC; ///< Offset 0x304 obsolete
+ UINT32 TCHE; ///< Offset 0x308 obsolete
+ UINT32 ALSI; ///< Offset 0x30C obsolete
+ UINT32 BCLP; ///< Offset 0x310 obsoleted in ver 3.0, moved to
Mailbox 2.
+ UINT32 PFIT; ///< Offset 0x314 obsolete
+ UINT32 CBLV; ///< Offset 0x318 obsoleted in ver 3.0, moved to
Mailbox 2.
+ UINT16 BCLM[0x14];///< Offset 0x31C obsoleted in ver 3.0, moved to
Mailbox 2.
+ UINT32 CPFM; ///< Offset 0x344 obsolete
+ UINT32 EPFM; ///< Offset 0x348 obsolete
+ UINT8 PLUT[0x4A];//
Re: [edk2-devel] [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0
Reviewed-by: Sai Chaganty
-Original Message-
From: Solanki, Digant H
Sent: Thursday, July 22, 2021 4:47 AM
To: devel@edk2.groups.io
Cc: Solanki, Digant H ; Ni, Ray ;
Chaganty, Rangasai V ; S, Ashraf Ali
Subject: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD
OpRegion v3.0
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3426
- There are many OpRegion fields obsoleted in MBOX1
- MBOX2 is re-purposed for Backlight related fields for dual LFP.
- Backlight related fields moved to MBOX2 from MBOX3 and some fields are
obsoleted in MBOX3.
Signed-off-by: Digant H Solanki
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Ashraf Ali S
---
Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h | 101
+
1 file changed, 101 insertions(+)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h
b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h
new file mode 100644
index 00..c9948ab55f
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion
+++ 30.h
@@ -0,0 +1,101 @@
+/** @file
+ IGD OpRegion definition from Intel Integrated Graphics Device
+OpRegion
+ Specification based on version 3.0.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _IGD_OPREGION_3_0_H_
+#define _IGD_OPREGION_3_0_H_
+
+#include "IgdOpRegion.h"
+
+#define IGD_OPREGION_HEADER_MBOX2_VER_3_0 BIT5
+
+#pragma pack(1)
+///
+/// OpRegion Mailbox 1 - Public ACPI Methods /// Offset 0x100, Size
+0x100 /// typedef struct {
+ UINT32 DRDY; ///< Offset 0x100 Driver Readiness
+ UINT32 CSTS; ///< Offset 0x104 Status
+ UINT32 CEVT; ///< Offset 0x108 Current Event
+ UINT8 RM11[0x14];///< Offset 0x10C Reserved Must be Zero
+ UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List
+ UINT32 CPDL[8]; ///< Offset 0x140 obsolete
+ UINT32 CADL[8]; ///< Offset 0x160 obsolete
+ UINT32 NADL[8]; ///< Offset 0x180 obsolete
+ UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out
+ UINT32 TIDX; ///< Offset 0x1A4 obsolete
+ UINT32 CHPD; ///< Offset 0x1A8 obsolete
+ UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator
+ UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator
+ UINT32 SXSW; ///< Offset 0x1B4 obsolete
+ UINT32 EVTS; ///< Offset 0x1B8 obsolete
+ UINT32 CNOT; ///< Offset 0x1BC obsolete
+ UINT32 NRDY; ///< Offset 0x1C0 Driver Status
+ UINT8 DID2[0x1C];///< Offset 0x1C4 Extended Supported Devices ID List
(DOD)
+ UINT8 CPD2[0x1C];///< Offset 0x1E0 obsolete
+ UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero
+} IGD_OPREGION_MBOX1_VER_3_0;
+
+///
+/// OpRegion Mailbox 2 - Backlight communication /// Offset 0x200, Size
+0x100 /// typedef struct {
+ UINT32 BCL1; ///< Offset 0x200 Backlight Brightness for LFP1
+ UINT32 BCL2; ///< Offset 0x204 Backlight Brightness for LFP2
+ UINT32 CBL1; ///< Offset 0x208 Current User Brightness Level for
LFP1
+ UINT32 CBL2; ///< Offset 0x20C Current User Brightness Level for
LFP2
+ UINT32 BCM1[0x1E];///< Offset 0x210 Backlight Brightness Levels Duty
Cycle Mapping Table for LFP1
+ UINT32 BCM2[0x1E];///< Offset 0x288 Backlight Brightness Levels Duty
Cycle Mapping Table for LFP2
+} IGD_OPREGION_MBOX2_VER_3_0;
+
+///
+/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support ///
+Offset 0x300, Size 0x100 /// typedef struct {
+ UINT32 ARDY; ///< Offset 0x300 obsolete
+ UINT32 ASLC; ///< Offset 0x304 obsolete
+ UINT32 TCHE; ///< Offset 0x308 obsolete
+ UINT32 ALSI; ///< Offset 0x30C obsolete
+ UINT32 BCLP; ///< Offset 0x310 obsoleted in ver 3.0, moved to
Mailbox 2.
+ UINT32 PFIT; ///< Offset 0x314 obsolete
+ UINT32 CBLV; ///< Offset 0x318 obsoleted in ver 3.0, moved to
Mailbox 2.
+ UINT16 BCLM[0x14];///< Offset 0x31C obsoleted in ver 3.0, moved to
Mailbox 2.
+ UINT32 CPFM; ///< Offset 0x344 obsolete
+ UINT32 EPFM; ///< Offset 0x348 obsolete
+ UINT8 PLUT[0x4A];///< Offset 0x34C obsolete
+ UINT32 PFMB; ///< Offset 0x396 obsolete
+ UINT32 CCDV; ///< Offset 0x39A obsolete
+ UINT32 PCFT; ///< Offset 0x39E obsolete
+ UINT32 SROT; ///< Offset 0x3A2 obsolete
+ UINT32 IUER; ///< Offset 0x3A6 obsolete
+ UINT64 FDSS; ///< Offset 0x3AA obsolete
+ UINT32 FDSP; ///< Offset 0x3B2 obsolete
+ UINT32 STAT; ///< Offset 0x3B6 obsolete
+ UINT64
Re: [edk2-devel] [edk2-platforms: PATCH] Features/Intel/IpmiFeaturePkg: Use MdePkg macros instead of redefining.
Reviewed-by: Sai Chaganty
-Original Message-
From: Chiu, Chasel
Sent: Thursday, July 15, 2021 7:38 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L
; Chaganty, Rangasai V
; Liming Gao ; Oram,
Isaac W
Subject: [edk2-platforms: PATCH] Features/Intel/IpmiFeaturePkg: Use MdePkg
macros instead of redefining.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3494
Renamed below macros and structure to use MdePkg ones.
IPMI_MSG_GET_BMC_EXEC_RSP
IPMI_GET_BMC_EXECUTION_CONTEXT
IPMI_BMC_IN_FORCED_UPDATE_MODE
Cc: Nate DeSimone
Cc: Sai Chaganty
Cc: Liming Gao
Cc: Isaac Oram
Signed-off-by: Chasel Chiu
---
Features/Intel/OutOfBandManagement/IpmiFeaturePkg/GenericIpmi/Dxe/IpmiInit.c |
8
Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/ServerManagement.h |
17 -
2 files changed, 4 insertions(+), 21 deletions(-)
diff --git
a/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/GenericIpmi/Dxe/IpmiInit.c
b/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/GenericIpmi/Dxe/IpmiInit.c
index 1e0c132508..d788b48867 100644
---
a/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/GenericIpmi/Dxe/IpmiInit.c
+++ b/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/GenericIpmi/Dxe/
+++ IpmiInit.c
@@ -242,7 +242,7 @@ Returns:
EFI_STATUS Status; UINT32
DataSize; SM_CTRL_INFO*pBmcInfo;-
EFI_IPMI_MSG_GET_BMC_EXEC_RSP *pBmcExecContext;+ IPMI_MSG_GET_BMC_EXEC_RSP
*pBmcExecContext; UINT32 Retries; #ifdef
FAST_VIDEO_SUPPORT EFI_VIDEOPRINT_PROTOCOL *VideoPrintProtocol;@@
-301,14 +301,14 @@ Returns:
Status = IpmiSendCommand (>IpmiTransport,
IPMI_NETFN_FIRMWARE, 0,-
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT,+
IPMI_GET_BMC_EXECUTION_CONTEXT,NULL, 0,
IpmiInstance->TempData, ); -pBmcExecContext =
(EFI_IPMI_MSG_GET_BMC_EXEC_RSP*)>TempData[0];+pBmcExecContext
= (IPMI_MSG_GET_BMC_EXEC_RSP*)>TempData[0]; DEBUG
((DEBUG_INFO, "[IPMI] Operational status of BMC: 0x%x\n",
pBmcExecContext->CurrentExecutionContext));-if
((pBmcExecContext->CurrentExecutionContext ==
EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE) &&+if
((pBmcExecContext->CurrentExecutionContext == IPMI_BMC_IN_FORCED_UPDATE_MODE)
&& !EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "[IPMI] BMC in
Forced Update mode, skip waiting for BMC_READY.\n"));
IpmiInstance->BmcStatus = BMC_UPDATE_IN_PROGRESS;diff --git
a/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/ServerManagement.h
b/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/ServerManagement.h
index 7591f33aba..244b86e91a 100644
---
a/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/ServerManagement.h
+++ b/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/ServerMa
+++ nagement.h
@@ -149,15 +149,6 @@ typedef enum {
#define UPPER_NON_RECOVER_GOING_LOW 0x400 #define UPPER_NON_RECOVER_GOING_HI
0x800 -//-// Definitions for Get BMC Execution Context-//-#define
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT 0x23-//-// Current Execution Context
responses-//-#define EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE 0x11- // // Server
Management COM Addressing types //@@ -327,14 +318,6 @@ typedef struct {
UINT16 IoBasePort; } IPMI_HOB_DATA; -//-// Constants and Structure
definitions for "Get Device ID" command to follow here-//-typedef struct {-
UINT8 CurrentExecutionContext;- UINT8 PartitionPointer;-}
EFI_IPMI_MSG_GET_BMC_EXEC_RSP;- // // COM Layer Callback //--
2.28.0.windows.1
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Re: [edk2-devel] [PATCH 2/2] Fix variables may be used uninitialize
Reviewed-by: Sai Chaganty
-Original Message-
From: Hsu, WesleyX
Sent: Sunday, July 18, 2021 8:59 PM
To: devel@edk2.groups.io
Cc: Hsu, WesleyX ; Ni, Ray ; Chaganty,
Rangasai V
Subject: [PATCH 2/2] Fix variables may be used uninitialize
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3491
Initialize variables may be used uninitialized after adding "-ffat-lto-objects"
option in GCC5 tool chain.
Change-Id: Iec8c9a884bac5cf1ce7258867c074c4668e5fa44
Signed-off-by: WesleyX Hsu
Cc: Ray Ni
Cc: Rangasai V Chaganty
---
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c |
5 +
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c |
7 ++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c
index 341e2beb..2a5fa637 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Translat
+++ ionTable.c
@@ -107,6 +107,11 @@ CreateSecondLevelPagingEntryTable (
UINT64EndAddress;
BOOLEAN Is5LevelPaging;
+ Lvl4PagesStart = 0;
+ Lvl4PagesEnd = 0;
+ Lvl4PtEntry= NULL;
+ Lvl5PtEntry= NULL;
+
if (MemoryLimit == 0) {
return EFI_SUCCESS;
}
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index d152039f..01375139 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationT
+++ able.c
@@ -133,7 +133,7 @@ CreateContextEntry (
mVtdUnitInformation[VtdIndex].Is5LevelPaging = TRUE;
if ((mAcpiDmarTable->HostAddressWidth <= 48) &&
((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) != 0)) {
-mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE;
+mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE;
}
} else if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) {
DEBUG((DEBUG_ERROR, " Page-table type is not supported on VTD %d
\n", VtdIndex)); @@ -195,6 +195,11 @@ CreateSecondLevelPagingEntryTable (
UINT64 BaseAddress;
UINT64 EndAddress;
+ Lvl4PagesStart = 0;
+ Lvl4PagesEnd = 0;
+ Lvl4PtEntry= NULL;
+ Lvl5PtEntry= NULL;
+
if (MemoryLimit == 0) {
return EFI_SUCCESS;
}
--
2.32.0.windows.2
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Re: [edk2-devel] [PATCH] Fix variables may be used uninitialize
Reviewed-by: Sai Chaganty
-Original Message-
From: Hsu, WesleyX
Sent: Friday, July 16, 2021 12:08 AM
To: devel@edk2.groups.io
Cc: Hsu, WesleyX ; Ni, Ray ; Chaganty,
Rangasai V
Subject: [PATCH] Fix variables may be used uninitialize
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3491
Initialize variables may be used uninitialized after adding "-ffat-lto-objects"
option in GCC5 tool chain.
Change-Id: Iec8c9a884bac5cf1ce7258867c074c4668e5fa44
Signed-off-by: WesleyX Hsu
Cc: Ray Ni
Cc: Rangasai V Chaganty
---
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c |
5 +
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c |
7 ++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c
index 341e2beb..2a5fa637 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Translat
+++ ionTable.c
@@ -107,6 +107,11 @@ CreateSecondLevelPagingEntryTable (
UINT64EndAddress;
BOOLEAN Is5LevelPaging;
+ Lvl4PagesStart = 0;
+ Lvl4PagesEnd = 0;
+ Lvl4PtEntry= NULL;
+ Lvl5PtEntry= NULL;
+
if (MemoryLimit == 0) {
return EFI_SUCCESS;
}
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index d152039f..01375139 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationT
+++ able.c
@@ -133,7 +133,7 @@ CreateContextEntry (
mVtdUnitInformation[VtdIndex].Is5LevelPaging = TRUE;
if ((mAcpiDmarTable->HostAddressWidth <= 48) &&
((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) != 0)) {
-mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE;
+mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE;
}
} else if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) {
DEBUG((DEBUG_ERROR, " Page-table type is not supported on VTD %d
\n", VtdIndex)); @@ -195,6 +195,11 @@ CreateSecondLevelPagingEntryTable (
UINT64 BaseAddress;
UINT64 EndAddress;
+ Lvl4PagesStart = 0;
+ Lvl4PagesEnd = 0;
+ Lvl4PtEntry= NULL;
+ Lvl5PtEntry= NULL;
+
if (MemoryLimit == 0) {
return EFI_SUCCESS;
}
--
2.32.0.windows.2
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Re: [edk2-devel] [PATCH] Fix variables may be used uninitialize
Reviewed-by: Sai Chaganty
-Original Message-
From: Hsu, WesleyX
Sent: Thursday, July 15, 2021 11:38 PM
To: devel@edk2.groups.io
Cc: Hsu, WesleyX ; Ni, Ray ; Chaganty,
Rangasai V
Subject: [PATCH] Fix variables may be used uninitialize
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3491
Initialize variables may be used uninitialized after adding "-ffat-lto-objects"
option in GCC5 tool chain.
Change-Id: Iec8c9a884bac5cf1ce7258867c074c4668e5fa44
Signed-off-by: WesleyX Hsu
Cc: Ray Ni
Cc: Rangasai V Chaganty
---
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c |
5 +
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c |
7 ++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c
index 341e2beb..2a5fa637 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Translat
+++ ionTable.c
@@ -107,6 +107,11 @@ CreateSecondLevelPagingEntryTable (
UINT64EndAddress;
BOOLEAN Is5LevelPaging;
+ Lvl4PagesStart = 0;
+ Lvl4PagesEnd = 0;
+ Lvl4PtEntry= NULL;
+ Lvl5PtEntry= NULL;
+
if (MemoryLimit == 0) {
return EFI_SUCCESS;
}
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index d152039f..01375139 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationT
+++ able.c
@@ -133,7 +133,7 @@ CreateContextEntry (
mVtdUnitInformation[VtdIndex].Is5LevelPaging = TRUE;
if ((mAcpiDmarTable->HostAddressWidth <= 48) &&
((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) != 0)) {
-mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE;
+mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE;
}
} else if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) {
DEBUG((DEBUG_ERROR, " Page-table type is not supported on VTD %d
\n", VtdIndex)); @@ -195,6 +195,11 @@ CreateSecondLevelPagingEntryTable (
UINT64 BaseAddress;
UINT64 EndAddress;
+ Lvl4PagesStart = 0;
+ Lvl4PagesEnd = 0;
+ Lvl4PtEntry= NULL;
+ Lvl5PtEntry= NULL;
+
if (MemoryLimit == 0) {
return EFI_SUCCESS;
}
--
2.26.2.windows.1
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Re: [edk2-devel] [PATCH] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0
Few comments:
1. Please pack the structures correctly using #pragma pack(1)/ #pragma pack()
pairs.
2. What is the purpose of IGD_OPREGION_HEADER_MBOX2_VER_3_0 macro definition
and assigning it to a value of BIT5.
3. Is the 3.0 version backward compatible to the one that is currently
available? I am wondering if there are reasons to carry obsolete members in 3.0
version.
Regards,
Sai
-Original Message-
From: Solanki, Digant H
Sent: Thursday, July 08, 2021 7:24 AM
To: devel@edk2.groups.io
Cc: Solanki, Digant H ; Ni, Ray ;
Chaganty, Rangasai V ; S, Ashraf Ali
Subject: [PATCH] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion
v3.0
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3426
- There are many OpRegion fields obsoleted in MBOX1
- MBOX2 is re-purposed for Backlight related fields for dual LFP.
- Backlight related fields moved to MBOX2 from MBOX3 and some fields are
obsoleted in MBOX3.
Signed-off-by: Digant H Solanki
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Ashraf Ali S
---
Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h | 100
1 file changed, 100 insertions(+)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h
b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h
new file mode 100644
index 00..422a60bdbd
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion
+++ 30.h
@@ -0,0 +1,100 @@
+/** @file
+ IGD OpRegion definition from Intel Integrated Graphics Device
+OpRegion
+ Specification based on version 3.0.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _IGD_OPREGION_3_0_H_
+#define _IGD_OPREGION_3_0_H_
+
+#include "IgdOpRegion.h"
+
+#define IGD_OPREGION_HEADER_MBOX2_VER_3_0 BIT5
+
+///
+/// OpRegion Mailbox 1 - Public ACPI Methods /// Offset 0x100, Size
+0x100 /// typedef struct {
+ UINT32 DRDY; ///< Offset 0x100 Driver Readiness
+ UINT32 CSTS; ///< Offset 0x104 Status
+ UINT32 CEVT; ///< Offset 0x108 Current Event
+ UINT8 RM11[0x14];///< Offset 0x10C Reserved Must be Zero
+ UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List
+ UINT32 CPDL[8]; ///< Offset 0x140 obsolete
+ UINT32 CADL[8]; ///< Offset 0x160 obsolete
+ UINT32 NADL[8]; ///< Offset 0x180 obsolete
+ UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out
+ UINT32 TIDX; ///< Offset 0x1A4 obsolete
+ UINT32 CHPD; ///< Offset 0x1A8 obsolete
+ UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator
+ UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator
+ UINT32 SXSW; ///< Offset 0x1B4 obsolete
+ UINT32 EVTS; ///< Offset 0x1B8 obsolete
+ UINT32 CNOT; ///< Offset 0x1BC obsolete
+ UINT32 NRDY; ///< Offset 0x1C0 Driver Status
+ UINT8 DID2[0x1C];///< Offset 0x1C4 Extended Supported Devices ID List
(DOD)
+ UINT8 CPD2[0x1C];///< Offset 0x1E0 obsolete
+ UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero
+} IGD_OPREGION_MBOX1_VER_3_0;
+
+///
+/// OpRegion Mailbox 2 - Backlight communication /// Offset 0x200, Size
+0x100 /// typedef struct {
+ UINT32 BCL1; ///< Offset 0x200 Backlight Brightness for LFP1
+ UINT32 BCL2; ///< Offset 0x204 Backlight Brightness for LFP2
+ UINT32 CBL1; ///< Offset 0x208 Current User Brightness Level for
LFP1
+ UINT32 CBL2; ///< Offset 0x20C Current User Brightness Level for
LFP2
+ UINT32 BCM1[0x1E];///< Offset 0x210 Backlight Brightness Levels Duty
Cycle Mapping Table for LFP1
+ UINT32 BCM2[0x1E];///< Offset 0x288 Backlight Brightness Levels Duty
Cycle Mapping Table for LFP2
+} IGD_OPREGION_MBOX2_VER_3_0;
+
+///
+/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support ///
+Offset 0x300, Size 0x100 /// typedef struct {
+ UINT32 ARDY; ///< Offset 0x300 obsolete
+ UINT32 ASLC; ///< Offset 0x304 obsolete
+ UINT32 TCHE; ///< Offset 0x308 obsolete
+ UINT32 ALSI; ///< Offset 0x30C obsolete
+ UINT32 BCLP; ///< Offset 0x310 obsoleted in ver 3.0, moved to
Mailbox 2.
+ UINT32 PFIT; ///< Offset 0x314 obsolete
+ UINT32 CBLV; ///< Offset 0x318 obsoleted in ver 3.0, moved to
Mailbox 2.
+ UINT16 BCLM[0x14];///< Offset 0x31C obsoleted in ver 3.0, moved to
Mailbox 2.
+ UINT32 CPFM; ///< Offset 0x344 obsolete
+ UINT32 EPFM; ///< Offset 0x348 obsolete
+ UINT8 PLUT[0x4A];///< Offset 0x34C obsolete
+ UINT32 PFMB; ///< Offset 0x396 obsolete
+ UINT32 CCDV; ///< Offset 0x39A obsolete
+ UINT32 PCF
