> -Original Message-
> From: Javeed, Ashraf
> Sent: Friday, July 26, 2019 9:47 AM
> To: Laszlo Ersek; devel@edk2.groups.io
> Cc: Kinney, Michael D; Gao, Liming; Ni, Ray; Wu, Hao A
> Subject: RE: [edk2-devel] [PATCH] MdePkg/PciExpress21.h: Fix the PCIe
> industry stand
Michael D ; Gao, Liming
> ; Ni, Ray ; Wu, Hao A
>
> Subject: Re: [edk2-devel] [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> standard registers
>
> Hi Javeed,
>
> On 07/25/19 20:23, Javeed, Ashraf wrote:
> > BZ: https://bugzilla.tianocore.org/show_bug.cgi
Subject: Re: [edk2-devel] [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> standard registers
>
> Hello Ashraf,
>
> On 07/25/19 23:20, Laszlo Ersek wrote:
> > Hi Javeed,
>
> [...]
>
> Sorry, I didn't mean to address you by surname.
>
> (I find that
Hello Ashraf,
On 07/25/19 23:20, Laszlo Ersek wrote:
> Hi Javeed,
[...]
Sorry, I didn't mean to address you by surname.
(I find that the comma notation in names is totally useless. Some people
put surname first, some others given name -- same confusion as without
the comma.)
I should have
Hi Javeed,
On 07/25/19 20:23, Javeed, Ashraf wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
> The following two PCI Capability Structure registers are updated as per
> the PCI Base Specification Revision 4:-
> (1) The PCI Device capability register
Liming
> ; Ni, Ray ; Wu, Hao A
>
> Subject: [edk2-devel] [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> standard registers
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
> The PCIe Device capability register #2 (PCI_REG_PCIE_DEVICE_CAPABILITY2)
> needs to
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
The following two PCI Capability Structure registers are updated as per
the PCI Base Specification Revision 4:-
(1) The PCI Device capability register 2(PCI_REG_PCIE_DEVICE_CAPABILITY2)
needs to be upgraded for the PCI features like -
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
The PCIe Device capability register #2 (PCI_REG_PCIE_DEVICE_CAPABILITY2)
needs to be upgraded for the PCI features like - LN system CLS, 10b Tag
completer/requester register fields, emergency power reduction support
and initialization
y, Michael D ; Gao, Liming
> ; Ni, Ray ; Wu, Hao A
>
> Subject: [edk2-devel] [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> standard registers
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
> The following two PCI Capability Structure registers are updated
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
The following two PCI Capability Structure registers are updated as per
the PCI Base Specification Revision 4:-
(1) The PCI Device capability register 2(PCI_REG_PCIE_DEVICE_CAPABILITY2)
needs to be upgraded for the PCI features like -
Yes. I mean highlight those changes bases on PCI Express Base Specification
Revision 4.0.
Otherwise, I don't know where are they from.
Thanks
Liming
> -Original Message-
> From: Javeed, Ashraf
> Sent: Friday, July 26, 2019 12:05 AM
> To: Gao, Liming ; devel@edk2.groups.io
> Cc: Kinney,
Liming,
The following are the 2 points summarizing the changes as per spec 4, and it is
already part of commit message...
> > > > > The PCIe Device capability register #2
> > > > > (PCI_REG_PCIE_DEVICE_CAPABILITY2) needs to be upgraded for
> > > > > the PCI features like - LN system CLS, 10b
That make sense. In the commit message, can you update the message to describe
which change bases on PCI Express Base Specification Revision 4.0?
Thanks
Liming
> -Original Message-
> From: Javeed, Ashraf
> Sent: Thursday, July 25, 2019 11:30 PM
> To: Gao, Liming ; devel@edk2.groups.io
>
These new macros definitions define PCI attributes which exist in the PCI
Express Base Specification Revision 2.1; hence placing this in the
PciExpress21.h align with the specification revision.
Thanks
Ashraf
> -Original Message-
> From: Gao, Liming
> Sent: Thursday, July 25, 2019 8:05
I agree the structure update in PciExpress21.h. I also see some new macro
definitions. Can they be added to PciExpress40.h, for example:
#define PCIE_MAX_PAYLOAD_SIZE_128B 0
#define PCIE_MAX_PAYLOAD_SIZE_256B 1
#define PCIE_MAX_PAYLOAD_SIZE_512B 2
#define PCIE_MAX_PAYLOAD_SIZE_1024B 3
Liming,
The existing structure are extended in PCI Express Base Specification Revision
4; hence I have made the change in PciExpress21.h.
Thanks
Ashraf
> -Original Message-
> From: Gao, Liming
> Sent: Thursday, July 25, 2019 7:35 PM
> To: Javeed, Ashraf ; devel@edk2.groups.io
> Cc:
Ashraf:
So, those update base on PCI Express Base Specification Revision 4.0. If new
definitions are in version 4.0, they can be added into PciExpress40.h. If the
existing structure is extended, they can be kept in PciExpress21.h.
Thanks
Liming
> -Original Message-
> From: Javeed,
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
The PCIe Device capability register #2 (PCI_REG_PCIE_DEVICE_CAPABILITY2)
needs to be upgraded for the PCI features like - LN system CLS, 10b Tag
completer/requester register fields, emergency power reduction support
and initialization
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