[edk2-devel] [PATCH 02/15] [platforms/devel-riscv]: Silicon/SiFive: Add library module of SiFive RISC-V cores

From: Gilbert Chen Initial version of SiFive RISC-V core libraries. Library of each core creates processor core SMBIOS data hob for building SMBIOS records in DXE phase. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gilbert Chen ---

[edk2-devel] [PATCH 02/15] [platforms/devel-riscv]: Silicon/SiFive: Add library module of SiFive RISC-V cores

Initial version of SiFive RISC-V core libraries. Library of each core creates processor core SMBIOS data hob for building SMBIOS records in DXE phase. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gilbert Chen --- .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c|

[edk2-devel] [PATCH 02/15] [platforms/devel-riscv]: Silicon/SiFive: Add library module of SiFive RISC-V cores

Initial version of SiFive RISC-V core libraries. Library of each core creates processor core SMBIOS data hob for building SMBIOS records in DXE phase. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gilbert Chen --- .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c|