Re: [edk2-devel] [PATCH 3/8] AlderlakeSiliconPkg/Pch: Add include headers

2023-07-24 Thread Chaganty, Rangasai V 
Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Thursday, June 15, 2023 10:53 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Oram, Isaac W ; 
Chuang, Rosen 
Subject: [PATCH 3/8] AlderlakeSiliconPkg/Pch: Add include headers

Adds the following header files:
* Pch/Include

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Isaac Oram 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Include/ConfigBlock/PchGeneralConfig.h|  86 
 .../Pch/Include/Library/PchCycleDecodingLib.h |  59 ++
 .../Pch/Include/Library/PchInfoDefs.h |  19 ++
 .../Pch/Include/Library/PchInfoLib.h  | 108 ++
 .../Pch/Include/Library/PchPciBdfLib.h| 187 ++
 .../Pch/Include/PchPolicyCommon.h |  30 +++
 .../Pch/Include/PchPreMemPolicyCommon.h   |  53 +
 .../Pch/Include/PchResetPlatformSpecific.h|  21 ++
 .../Pch/Include/Protocol/PchAcpiSmiDispatch.h | 134 +  
.../Pch/Include/Protocol/PchPcieSmiDispatch.h | 166 
 .../Pch/Include/Protocol/PchSmiDispatch.h | 132 +
 .../Include/Protocol/PchSmmIoTrapControl.h|  65 ++
 .../Protocol/PchSmmPeriodicTimerControl.h |  65 ++
 .../Pch/Include/Protocol/PchTcoSmiDispatch.h  | 150 ++
 .../Pch/Include/Protocol/SmmSmbus.h   |  13 ++
 .../Pch/Include/Register/PchRegs.h|  45 +
 16 files changed, 1333 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchInfoDefs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchPolicyCommon.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Register/PchRegs.h

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h
new file mode 100644
index 00..4501537fe2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGener
+++ alConfig.h
@@ -0,0 +1,86 @@
+/** @file
+  PCH General policy
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef 
+_PCH_GENERAL_CONFIG_H_ #define _PCH_GENERAL_CONFIG_H_
+
+
+extern EFI_GUID gPchGeneralConfigGuid;
+extern EFI_GUID gPchGeneralPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+enum PCH_RESERVED_PAGE_ROUTE {
+  PchReservedPageToLpc,   ///< Port 80h cycles are sent to LPC.
+  PchReservedPageToPcie   ///< Port 80h cycles are sent to 
PCIe.
+};
+
+/**
+  PCH General Configuration
+  Revision 1:  - Initial version.
+  Revision 2:  - Added AcpiL6dPmeHandling **/ typedef struct {
+  CONFIG_BLOCK_HEADER   Header;   ///< Config Block Header
+  /**
+This member describes whether or not the Compatibility Revision ID (CRID) 
feature
+of PCH should be enabled. 0: Disable; 1: Enable
+  **/
+  UINT32Crid:  1;
+  /**
+Set to enable low latency of legacy IO.
+Some systems require lower IO latency irrespective of power.
+This is a tradeoff between power and IO latency.
+@note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent
+and ITSS Clock Gating are forced to disabled.
+0: Disable, 1: Enable
+  **/
+  UINT32LegacyIoLowLatency  :  1;
+  /**
+  Enables _L6D ACPI handler.
+  PME GPE is shared by multiple devices So BIOS must verify the same in 
+the ASL handler by reading offset for PMEENABLE and PMESTATUS bit
+  0: Disable, 1: Enable
+  **/
+  UINT32AcpiL6dPmeHandling  :  1;
+  UINT32RsvdBits0   : 29;   ///< Reserved bits
+} PCH_GENERAL_CONFIG;
+
+/**
+  PCH General

[edk2-devel] [PATCH 3/8] AlderlakeSiliconPkg/Pch: Add include headers

2023-06-15 Thread Saloni Kasbekar 
Adds the following header files:
* Pch/Include

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Isaac Oram 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Include/ConfigBlock/PchGeneralConfig.h|  86 
 .../Pch/Include/Library/PchCycleDecodingLib.h |  59 ++
 .../Pch/Include/Library/PchInfoDefs.h |  19 ++
 .../Pch/Include/Library/PchInfoLib.h  | 108 ++
 .../Pch/Include/Library/PchPciBdfLib.h| 187 ++
 .../Pch/Include/PchPolicyCommon.h |  30 +++
 .../Pch/Include/PchPreMemPolicyCommon.h   |  53 +
 .../Pch/Include/PchResetPlatformSpecific.h|  21 ++
 .../Pch/Include/Protocol/PchAcpiSmiDispatch.h | 134 +
 .../Pch/Include/Protocol/PchPcieSmiDispatch.h | 166 
 .../Pch/Include/Protocol/PchSmiDispatch.h | 132 +
 .../Include/Protocol/PchSmmIoTrapControl.h|  65 ++
 .../Protocol/PchSmmPeriodicTimerControl.h |  65 ++
 .../Pch/Include/Protocol/PchTcoSmiDispatch.h  | 150 ++
 .../Pch/Include/Protocol/SmmSmbus.h   |  13 ++
 .../Pch/Include/Register/PchRegs.h|  45 +
 16 files changed, 1333 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchInfoDefs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchPolicyCommon.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Register/PchRegs.h

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h
new file mode 100644
index 00..4501537fe2
--- /dev/null
+++ 
b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h
@@ -0,0 +1,86 @@
+/** @file
+  PCH General policy
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_GENERAL_CONFIG_H_
+#define _PCH_GENERAL_CONFIG_H_
+
+
+extern EFI_GUID gPchGeneralConfigGuid;
+extern EFI_GUID gPchGeneralPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+enum PCH_RESERVED_PAGE_ROUTE {
+  PchReservedPageToLpc,   ///< Port 80h cycles are sent to LPC.
+  PchReservedPageToPcie   ///< Port 80h cycles are sent to 
PCIe.
+};
+
+/**
+  PCH General Configuration
+  Revision 1:  - Initial version.
+  Revision 2:  - Added AcpiL6dPmeHandling
+**/
+typedef struct {
+  CONFIG_BLOCK_HEADER   Header;   ///< Config Block Header
+  /**
+This member describes whether or not the Compatibility Revision ID (CRID) 
feature
+of PCH should be enabled. 0: Disable; 1: Enable
+  **/
+  UINT32Crid:  1;
+  /**
+Set to enable low latency of legacy IO.
+Some systems require lower IO latency irrespective of power.
+This is a tradeoff between power and IO latency.
+@note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent
+and ITSS Clock Gating are forced to disabled.
+0: Disable, 1: Enable
+  **/
+  UINT32LegacyIoLowLatency  :  1;
+  /**
+  Enables _L6D ACPI handler.
+  PME GPE is shared by multiple devices So BIOS must verify the same in the 
ASL handler by reading offset for PMEENABLE and PMESTATUS bit
+  0: Disable, 1: Enable
+  **/
+  UINT32AcpiL6dPmeHandling  :  1;
+  UINT32RsvdBits0   : 29;   ///< Reserved bits
+} PCH_GENERAL_CONFIG;
+
+/**
+  PCH General Pre-Memory Configuration
+  Revision 1:  - Initial version.
+  Revision 2:  - Added GpioOverride.
+  Revision 3:  - Added IoeDebugEn, PmodeClkEn
+**/
+typedef struct {
+  CONFIG_BLOCK_HEADER   Header;   ///< Config Block Header
+  /**
+Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
+  **/