Re: [edk2-devel] [PATCH 8/8] AlderlakeSiliconPkg/SystemAgent: Add library and driver modules
Reviewed-by: Sai Chaganty
-Original Message-
From: Kasbekar, Saloni
Sent: Thursday, June 15, 2023 10:53 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V
; Desimone, Nathaniel L
; Oram, Isaac W ;
Chuang, Rosen
Subject: [PATCH 8/8] AlderlakeSiliconPkg/SystemAgent: Add library and driver
modules
Adds the following modules:
- Library/DxeSaPolicyLib
- SaInit
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Isaac Oram
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../Library/DxeSaPolicyLib/DxeSaPolicyLib.c | 225 ++
.../Library/DxeSaPolicyLib/DxeSaPolicyLib.inf | 46
.../DxeSaPolicyLib/DxeSaPolicyLibrary.h | 30 +++
.../SystemAgent/SaInit/Dxe/SaAcpi.c | 193 +++
.../SystemAgent/SaInit/Dxe/SaInit.c | 97
.../SystemAgent/SaInit/Dxe/SaInit.h | 42
.../SystemAgent/SaInit/Dxe/SaInitDxe.c| 90 +++
.../SystemAgent/SaInit/Dxe/SaInitDxe.h| 119 +
.../SystemAgent/SaInit/Dxe/SaInitDxe.inf | 98
9 files changed, 940 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLibrary.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
new file mode 100644
index 00..d812f300c1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyL
+++ ib/DxeSaPolicyLib.c
@@ -0,0 +1,225 @@
+/** @file
+ This file provide services for DXE phase policy default
+initialization
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include "DxeSaPolicyLibrary.h"
+#include #include
+ #include "MemoryConfig.h"
+
+extern EFI_GUID gMemoryDxeConfigGuid;
+
+/**
+ This function prints the SA DXE phase policy.
+
+ @param[in] SaPolicy - SA DXE Policy protocol **/ VOID
+SaPrintPolicyProtocol (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ UINT8 ControllerIndex;
+ UINT8 ChannelIndex;
+ EFI_STATUS Status;
+ MEMORY_DXE_CONFIG *MemoryDxeConfig;
+
+ Status = GetConfigBlock ((VOID *) SaPolicy, ,
+ (VOID *)); ASSERT_EFI_ERROR (Status);
+
+
+ DEBUG_CODE_BEGIN ();
+ INTN i;
+
+ DEBUG ((DEBUG_INFO, "\n SA Policy (DXE) print
+ BEGIN -\n")); DEBUG ((DEBUG_INFO, "Revision : %x\n",
+ SaPolicy->TableHeader.Header.Revision));
+ ASSERT (SaPolicy->TableHeader.Header.Revision ==
+ SA_POLICY_PROTOCOL_REVISION);
+
+ DEBUG ((DEBUG_INFO, " SA_MEMORY_CONFIGURATION
+ -\n"));
+
+ DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", 4)); for (i = 0; i <
+ 4; i++) {
+DEBUG ((DEBUG_INFO, " %x", MemoryDxeConfig->SpdAddressTable[i]));
+ }
+ DEBUG ((DEBUG_INFO, "\n"));
+
+ for (ControllerIndex = 0; ControllerIndex < MEM_CFG_MAX_CONTROLLERS;
ControllerIndex++) {
+for (ChannelIndex = 0; ChannelIndex < MEM_CFG_MAX_CHANNELS;
ChannelIndex++) {
+ DEBUG ((DEBUG_INFO, " SlotMap[%d][%d] : 0x%x\n", ControllerIndex,
ChannelIndex, MemoryDxeConfig->SlotMap[ControllerIndex][ChannelIndex]));
+}
+ }
+ DEBUG ((DEBUG_INFO, " MrcTimeMeasure : %x\n",
MemoryDxeConfig->MrcTimeMeasure));
+ DEBUG ((DEBUG_INFO, " MrcFastBoot : %x\n",
MemoryDxeConfig->MrcFastBoot));
+
+ DEBUG ((DEBUG_INFO, " CPU_PCIE_CONFIGURATION
+ -\n")); DEBUG ((DEBUG_INFO, " PegAspm[%d] :",
+ SA_PEG_MAX_FUN)); DEBUG ((DEBUG_INFO, " PegRootPortHPE[%d] :",
+ SA_PEG_MAX_FUN)); DEBUG ((DEBUG_INFO, "\n"));
+
+
+ DEBUG ((DEBUG_INFO, "\n SA Policy (DXE) print
+ END -\n")); DEBUG_CODE_END ();
+
+ return;
+}
+
+/**
+ Load DXE Config block default
+
+ @param[in] ConfigBlockPointer Pointer to config block
+**/
+VOID
+LoadMemoryDxeDefault (
+ IN VOID*ConfigBlockPointer
+ )
+{
+ UINT8ControllerIndex;
+ UINT8ChannelIndex;
+ MEMORY_DXE_CONFIG*MemoryDxeConfig;
+
+ MemoryDxeConfig =
[edk2-devel] [PATCH 8/8] AlderlakeSiliconPkg/SystemAgent: Add library and driver modules
Adds the following modules:
- Library/DxeSaPolicyLib
- SaInit
Cc: Sai Chaganty
Cc: Nate DeSimone
Cc: Isaac Oram
Cc: Rosen Chuang
Signed-off-by: Saloni Kasbekar
---
.../Library/DxeSaPolicyLib/DxeSaPolicyLib.c | 225 ++
.../Library/DxeSaPolicyLib/DxeSaPolicyLib.inf | 46
.../DxeSaPolicyLib/DxeSaPolicyLibrary.h | 30 +++
.../SystemAgent/SaInit/Dxe/SaAcpi.c | 193 +++
.../SystemAgent/SaInit/Dxe/SaInit.c | 97
.../SystemAgent/SaInit/Dxe/SaInit.h | 42
.../SystemAgent/SaInit/Dxe/SaInitDxe.c| 90 +++
.../SystemAgent/SaInit/Dxe/SaInitDxe.h| 119 +
.../SystemAgent/SaInit/Dxe/SaInitDxe.inf | 98
9 files changed, 940 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.inf
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLibrary.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
new file mode 100644
index 00..d812f300c1
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
@@ -0,0 +1,225 @@
+/** @file
+ This file provide services for DXE phase policy default initialization
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "DxeSaPolicyLibrary.h"
+#include
+#include
+#include "MemoryConfig.h"
+
+extern EFI_GUID gMemoryDxeConfigGuid;
+
+/**
+ This function prints the SA DXE phase policy.
+
+ @param[in] SaPolicy - SA DXE Policy protocol
+**/
+VOID
+SaPrintPolicyProtocol (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ UINT8 ControllerIndex;
+ UINT8 ChannelIndex;
+ EFI_STATUS Status;
+ MEMORY_DXE_CONFIG *MemoryDxeConfig;
+
+ Status = GetConfigBlock ((VOID *) SaPolicy, , (VOID
*));
+ ASSERT_EFI_ERROR (Status);
+
+
+ DEBUG_CODE_BEGIN ();
+ INTN i;
+
+ DEBUG ((DEBUG_INFO, "\n SA Policy (DXE) print BEGIN
-\n"));
+ DEBUG ((DEBUG_INFO, "Revision : %x\n",
SaPolicy->TableHeader.Header.Revision));
+ ASSERT (SaPolicy->TableHeader.Header.Revision ==
SA_POLICY_PROTOCOL_REVISION);
+
+ DEBUG ((DEBUG_INFO, " SA_MEMORY_CONFIGURATION
-\n"));
+
+ DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", 4));
+ for (i = 0; i < 4; i++) {
+DEBUG ((DEBUG_INFO, " %x", MemoryDxeConfig->SpdAddressTable[i]));
+ }
+ DEBUG ((DEBUG_INFO, "\n"));
+
+ for (ControllerIndex = 0; ControllerIndex < MEM_CFG_MAX_CONTROLLERS;
ControllerIndex++) {
+for (ChannelIndex = 0; ChannelIndex < MEM_CFG_MAX_CHANNELS;
ChannelIndex++) {
+ DEBUG ((DEBUG_INFO, " SlotMap[%d][%d] : 0x%x\n", ControllerIndex,
ChannelIndex, MemoryDxeConfig->SlotMap[ControllerIndex][ChannelIndex]));
+}
+ }
+ DEBUG ((DEBUG_INFO, " MrcTimeMeasure : %x\n",
MemoryDxeConfig->MrcTimeMeasure));
+ DEBUG ((DEBUG_INFO, " MrcFastBoot : %x\n",
MemoryDxeConfig->MrcFastBoot));
+
+ DEBUG ((DEBUG_INFO, " CPU_PCIE_CONFIGURATION
-\n"));
+ DEBUG ((DEBUG_INFO, " PegAspm[%d] :", SA_PEG_MAX_FUN));
+ DEBUG ((DEBUG_INFO, " PegRootPortHPE[%d] :", SA_PEG_MAX_FUN));
+ DEBUG ((DEBUG_INFO, "\n"));
+
+
+ DEBUG ((DEBUG_INFO, "\n SA Policy (DXE) print END
-\n"));
+ DEBUG_CODE_END ();
+
+ return;
+}
+
+/**
+ Load DXE Config block default
+
+ @param[in] ConfigBlockPointer Pointer to config block
+**/
+VOID
+LoadMemoryDxeDefault (
+ IN VOID*ConfigBlockPointer
+ )
+{
+ UINT8ControllerIndex;
+ UINT8ChannelIndex;
+ MEMORY_DXE_CONFIG*MemoryDxeConfig;
+
+ MemoryDxeConfig = ConfigBlockPointer;
+ ///
+ /// Initialize the Memory Configuration
+ ///
+ ///
+ /// DIMM SMBus addresses info
+ /// Refer to the SpdAddressTable[] mapping rule in DxeSaPolicyLibrary.h
+ ///
+ MemoryDxeConfig->SpdAddressTable = AllocateZeroPool (sizeof (UINT8) * 4);
+ ASSERT (MemoryDxeConfig->SpdAddressTable != NULL);
+ if
