Re: [edk2-devel] [edk2-platforms: PATCH v2 04/10] Marvell/Cn9130Db: Introduce board support

2019-08-16 Thread Leif Lindholm 
On Thu, Aug 15, 2019 at 04:54:08AM +0200, Marcin Wojtas wrote:
> This patch introduces all necessary components required
> for building EDK2 firmware for CN9130-DB setup A.
> Because the board is modular and can be extended to support
> also CN9131 and CN9132 SoC variants, extract common part into
> .dsc.inc file, which will be included by them.
> 
> Signed-off-by: Marcin Wojtas 
> ---
>  Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc 
> | 107 +++
>  Platform/Marvell/Cn913xDb/Cn913xDbA.dsc 
> |  46 +++
>  Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf 
> |  29 
>  Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf 
> |  37 +
>  Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h   
> |  19 +++
>  Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c   
> | 126 +
>  Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c   
> | 144 
>  Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc 
> |  18 +++
>  8 files changed, 526 insertions(+)
>  create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
>  create mode 100644 Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
>  create mode 100644 
> Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
>  create mode 100644 
> Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
>  create mode 100644 
> Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
>  create mode 100644 
> Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c
>  create mode 100644 
> Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
>  create mode 100644 Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc
> 
> diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc 
> b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
> new file mode 100644
> index 000..33fb7cc
> --- /dev/null
> +++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
> @@ -0,0 +1,107 @@
> +## @file
> +#  Component description file for the CN9130 Development Board (variant A)
> +#
> +#  Copyright (c) 2019 Marvell International Ltd.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +
> +[PcdsFixedAtBuild.common]
> +  # CP115 count
> +  gMarvellTokenSpaceGuid.PcdMaxCpCount|1
> +
> +  # MPP
> +  gMarvellTokenSpaceGuid.PcdMppChipCount|2
> +
> +  # APN807 MPP
> +  gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
> +  gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
> +  gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
> +  gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 
> 0x1, 0x1, 0x1, 0x1 }
> +  gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 
> 0x0, 0x0, 0x0, 0x3 }
> +
> +  # CP115 #0 MPP
> +  gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
> +  gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF244
> +  gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
> +  gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 
> 0x3, 0x3, 0x3, 0x3 }
> +  gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 
> 0x3, 0x1, 0x1, 0x1 }
> +  gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 
> 0x1, 0x1, 0x3, 0x9 }
> +  gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 
> 0x2, 0x2, 0x2, 0x1 }
> +  gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 
> 0x1, 0x1, 0x1, 0x1 }
> +  gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 
> 0xE, 0xE, 0xE, 0xE }
> +  gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 
> 0x0, 0x0, 0x0, 0x0 }
> +
> +  # I2C
> +  gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 }
> +  gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }
> +  gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }
> +  gMarvellTokenSpaceGuid.PcdI2cClockFrequency|25000
> +  gMarvellTokenSpaceGuid.PcdI2cBaudRate|10
> +
> +  # SPI
> +  gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680
> +  gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|1000
> +  gMarvellTokenSpaceGuid.PcdSpiClockFrequency|2
> +
> +  gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
> +  gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
> +
> +  # ComPhy
> +  gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
> +  # ComPhy0
> +  # 0: PCIE0 5 Gbps
> +  # 1: PCIE0 5 Gbps
> +  # 2: PCIE0 5 Gbps
> +  # 3: PCIE0 5 Gbps
> +  # 4: SFI   10.31 Gbps
> +  # 5: SATA1 5 Gbps
> +  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), 
>

[edk2-devel] [edk2-platforms: PATCH v2 04/10] Marvell/Cn9130Db: Introduce board support

2019-08-14 Thread Marcin Wojtas 
This patch introduces all necessary components required
for building EDK2 firmware for CN9130-DB setup A.
Because the board is modular and can be extended to support
also CN9131 and CN9132 SoC variants, extract common part into
.dsc.inc file, which will be included by them.

Signed-off-by: Marcin Wojtas 
---
 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 
107 +++
 Platform/Marvell/Cn913xDb/Cn913xDbA.dsc |  
46 +++
 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf |  
29 
 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf |  
37 +
 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h   |  
19 +++
 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c   | 
126 +
 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c   | 
144 
 Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc |  
18 +++
 8 files changed, 526 insertions(+)
 create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
 create mode 100644 Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
 create mode 100644 
Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
 create mode 100644 
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
 create mode 100644 
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
 create mode 100644 
Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c
 create mode 100644 
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
 create mode 100644 Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc

diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc 
b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
new file mode 100644
index 000..33fb7cc
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
@@ -0,0 +1,107 @@
+## @file
+#  Component description file for the CN9130 Development Board (variant A)
+#
+#  Copyright (c) 2019 Marvell International Ltd.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+
+[PcdsFixedAtBuild.common]
+  # CP115 count
+  gMarvellTokenSpaceGuid.PcdMaxCpCount|1
+
+  # MPP
+  gMarvellTokenSpaceGuid.PcdMppChipCount|2
+
+  # APN807 MPP
+  gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+  gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+  gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
+  gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 
0x1, 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 
0x0, 0x0, 0x3 }
+
+  # CP115 #0 MPP
+  gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+  gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF244
+  gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
+  gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 
0x3, 0x3, 0x3 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0x3, 
0x1, 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 
0x1, 0x3, 0x9 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 0x2, 
0x2, 0x2, 0x1 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 
0x1, 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 
0xE, 0xE, 0xE }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 
0x0, 0x0, 0x0 }
+
+  # I2C
+  gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 }
+  gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }
+  gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }
+  gMarvellTokenSpaceGuid.PcdI2cClockFrequency|25000
+  gMarvellTokenSpaceGuid.PcdI2cBaudRate|10
+
+  # SPI
+  gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680
+  gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|1000
+  gMarvellTokenSpaceGuid.PcdSpiClockFrequency|2
+
+  gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
+  gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+
+  # ComPhy
+  gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
+  # ComPhy0
+  # 0: PCIE0 5 Gbps
+  # 1: PCIE0 5 Gbps
+  # 2: PCIE0 5 Gbps
+  # 3: PCIE0 5 Gbps
+  # 4: SFI   10.31 Gbps
+  # 5: SATA1 5 Gbps
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), 
$(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
+  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), 
$(CP_5G), $(CP_10_3125G), $(CP_5G) }
+
+  # UtmiPhy
+  gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0),