Re: [edk2-devel] [edk2-platforms][PATCH v1] PurleyOpenBoardPkg/BoardMtOlympus: Fix Build

2023-11-29 Thread Nate DeSimone 
Pushed as 0114e8b

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Nate DeSimone
Sent: Monday, November 27, 2023 5:04 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel 
Subject: [edk2-devel] [edk2-platforms][PATCH v1] 
PurleyOpenBoardPkg/BoardMtOlympus: Fix Build

Updates Microcode and Silicon FV sizes so they can accomodate the newest 
content.

Cc: Chasel Chiu 
Signed-off-by: Nate DeSimone 
---
 .../BoardMtOlympus/OpenBoardPkg.fdf   | 25 +++
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf 
b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
index 413d98a070..86d1673458 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
@@ -1,7 +1,7 @@
 ## @file
 #  FDF file for the MtOlympus board.
 #
-# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2018 - 2023, Intel Corporation. All rights 
+reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -43,11 +43,11 @@ FV = 
FvOsBoot  
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize
 FV = FvLateSiliconCompressed
 
-0x0090|0x0040
+0x0090|0x0030
 
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
 FV = FvUefiBoot
 
-0x00D0|0x0007C000
+0x00C0|0x0007C000
 
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
 #NV_VARIABLE_STORE
 DATA = {
@@ -86,10 +86,10 @@ DATA = {
   0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00  }
 
-0x00D7C000|0x2000
+0x00C7C000|0x2000
 #NV_EVENT_LOG
 
-0x00D7E000|0x2000
+0x00C7E000|0x2000
 
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
 #NV_FTW_WORKING
 DATA = {
@@ -103,28 +103,28 @@ DATA = {
   0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00  }
 
-0x00D8|0x0008
+0x00C8|0x0008
 
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
 #NV_FTW_SPARE
 
 
-0x00E0|0x0001
+0x00D0|0x0003
 
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
 FV = MICROCODE_FV
 
-0x00E1|0x0001
+0x00D3|0x0001
 
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
 FV = FvPostMemory
 
-0x00E2|0x0003
+0x00D4|0x0002
 
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
 FILE = 
$(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPostMemorySilicon.Fv
 
-0x00E5|0x0006
+0x00D6|0x0005
 
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
 FV = FvPreMemory
 
-0x00EB|0x0013
+0x00DB|0x0023
 
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
 FILE = 
$(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPreMemorySilicon.Fv
 
@@ -135,6 +135,9 @@ FILE = 
$(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvTempMemoryS
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase= 
gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + 
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize= 
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
 
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase   = 
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize   = 
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
+
 SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress= 
gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + 
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + 0x60
 SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = 
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60
 
--
2.39.2.windows.1








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Re: [edk2-devel] [edk2-platforms][PATCH v1] PurleyOpenBoardPkg/BoardMtOlympus: Fix Build

2023-11-27 Thread Chiu, Chasel 


Reviewed-by: Chasel Chiu 

Thanks,
Chasel


> -Original Message-
> From: Desimone, Nathaniel L 
> Sent: Monday, November 27, 2023 5:04 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel 
> Subject: [edk2-platforms][PATCH v1] PurleyOpenBoardPkg/BoardMtOlympus: Fix
> Build
> 
> Updates Microcode and Silicon FV sizes so they can accomodate the newest
> content.
> 
> Cc: Chasel Chiu 
> Signed-off-by: Nate DeSimone 
> ---
>  .../BoardMtOlympus/OpenBoardPkg.fdf   | 25 +++
>  1 file changed, 14 insertions(+), 11 deletions(-)
> 
> diff --git
> a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
> b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
> index 413d98a070..86d1673458 100644
> --- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
> +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
> @@ -1,7 +1,7 @@
>  ## @file
>  #  FDF file for the MtOlympus board.
>  #
> -# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
> +# Copyright (c) 2018 - 2023, Intel Corporation. All rights
> +reserved.
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -43,11 +43,11 @@ FV =
> FvOsBoot
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|gMinPlatformPkgTokenSp
> aceGuid.PcdFlashFvFspUSize
>  FV = FvLateSiliconCompressed
> 
> -0x0090|0x0040
> +0x0090|0x0030
> 
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgToke
> nSpaceGuid.PcdFlashFvUefiBootSize
>  FV = FvUefiBoot
> 
> -0x00D0|0x0007C000
> +0x00C0|0x0007C000
> 
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeMo
> dulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
>  #NV_VARIABLE_STORE
>  DATA = {
> @@ -86,10 +86,10 @@ DATA = {
>0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00  }
> 
> -0x00D7C000|0x2000
> +0x00C7C000|0x2000
>  #NV_EVENT_LOG
> 
> -0x00D7E000|0x2000
> +0x00C7E000|0x2000
> 
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMde
> ModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
>  #NV_FTW_WORKING
>  DATA = {
> @@ -103,28 +103,28 @@ DATA = {
>0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00  }
> 
> -0x00D8|0x0008
> +0x00C8|0x0008
> 
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeM
> odulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
>  #NV_FTW_SPARE
> 
> 
> -0x00E0|0x0001
> +0x00D0|0x0003
> 
> gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|gCpuUncoreTok
> enSpaceGuid.PcdFlashNvStorageMicrocodeSize
>  FV = MICROCODE_FV
> 
> -0x00E1|0x0001
> +0x00D3|0x0001
> 
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgT
> okenSpaceGuid.PcdFlashFvPostMemorySize
>  FV = FvPostMemory
> 
> -0x00E2|0x0003
> +0x00D4|0x0002
> 
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSp
> aceGuid.PcdFlashFvFspSSize
>  FILE =
> $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPostMe
> morySilicon.Fv
> 
> -0x00E5|0x0006
> +0x00D6|0x0005
> 
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgT
> okenSpaceGuid.PcdFlashFvPreMemorySize
>  FV = FvPreMemory
> 
> -0x00EB|0x0013
> +0x00DB|0x0023
> 
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSp
> aceGuid.PcdFlashFvFspMSize
>  FILE =
> $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPreMemo
> rySilicon.Fv
> 
> @@ -135,6 +135,9 @@ FILE =
> $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvTempM
> emoryS
>  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase=
> gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress +
> gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
>  SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize=
> gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
> 
> +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase   =
> gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
> +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize   =
> gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
> +
>  SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress=
> gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress +
> gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + 0x60
>  SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60
> 
> --
> 2.39.2.windows.1



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[edk2-devel] [edk2-platforms][PATCH v1] PurleyOpenBoardPkg/BoardMtOlympus: Fix Build

2023-11-27 Thread Nate DeSimone 
Updates Microcode and Silicon FV sizes so
they can accomodate the newest content.

Cc: Chasel Chiu 
Signed-off-by: Nate DeSimone 
---
 .../BoardMtOlympus/OpenBoardPkg.fdf   | 25 +++
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf 
b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
index 413d98a070..86d1673458 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
@@ -1,7 +1,7 @@
 ## @file
 #  FDF file for the MtOlympus board.
 #
-# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2018 - 2023, Intel Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -43,11 +43,11 @@ FV = FvOsBoot
 
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize
 FV = FvLateSiliconCompressed
 
-0x0090|0x0040
+0x0090|0x0030
 
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
 FV = FvUefiBoot
 
-0x00D0|0x0007C000
+0x00C0|0x0007C000
 
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
 #NV_VARIABLE_STORE
 DATA = {
@@ -86,10 +86,10 @@ DATA = {
   0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 }
 
-0x00D7C000|0x2000
+0x00C7C000|0x2000
 #NV_EVENT_LOG
 
-0x00D7E000|0x2000
+0x00C7E000|0x2000
 
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
 #NV_FTW_WORKING
 DATA = {
@@ -103,28 +103,28 @@ DATA = {
   0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 }
 
-0x00D8|0x0008
+0x00C8|0x0008
 
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
 #NV_FTW_SPARE
 
 
-0x00E0|0x0001
+0x00D0|0x0003
 
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
 FV = MICROCODE_FV
 
-0x00E1|0x0001
+0x00D3|0x0001
 
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
 FV = FvPostMemory
 
-0x00E2|0x0003
+0x00D4|0x0002
 
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
 FILE = 
$(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPostMemorySilicon.Fv
 
-0x00E5|0x0006
+0x00D6|0x0005
 
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
 FV = FvPreMemory
 
-0x00EB|0x0013
+0x00DB|0x0023
 
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
 FILE = 
$(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPreMemorySilicon.Fv
 
@@ -135,6 +135,9 @@ FILE = 
$(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvTempMemoryS
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase= 
gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + 
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize= 
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
 
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase   = 
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize   = 
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
+
 SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress= 
gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + 
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + 0x60
 SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = 
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60
 
-- 
2.39.2.windows.1



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