2011/9/27 Mitch Bradley :
> On 9/26/2011 4:40 PM, Andrei E. Warkentin wrote:
>>
>> 2011/9/26 Andrei E. Warkentin:
>>>
>>> 2011/9/26 Mitch Bradley:
If you write 0x400 to APB_VIRT_BASE + 0x1d008, it will assert interrupt
56 .
You can then clear it by writing 0x400 to APB_VIRT
2011/9/26 Andrei E. Warkentin :
> 2011/9/26 Mitch Bradley :
>>
>> If you write 0x400 to APB_VIRT_BASE + 0x1d008, it will assert interrupt 56 .
>>
>> You can then clear it by writing 0x400 to APB_VIRT_BASE + 0x1d40c.
>>
>> This uses an inter-processor communication unit. Presumably the FIG handler
2011/9/26 Mitch Bradley :
>
> If you write 0x400 to APB_VIRT_BASE + 0x1d008, it will assert interrupt 56 .
>
> You can then clear it by writing 0x400 to APB_VIRT_BASE + 0x1d40c.
>
> This uses an inter-processor communication unit. Presumably the FIG handler
> would assert the interrupt and the IRQ
Hi Chris, Mitch,
2011/9/26 Chris Ball :
> Here's a transcription of an explanation Mitch just gave:
>
> It's certainly possible to route any given interrupt to either FIQ or
> IRQ on either core. It is possible for an instruction to cause an
> interrupt/exception; that's how OFW does breakpoints.
Hi Andrei,
On Mon, Sep 26 2011, Andrei E. Warkentin wrote:
> I have a question about the ICU controller in the XO 1.75. I was
> looking into porting over and extending the FIQ debugger onto the XO (which
> allows debugging wedged/deadlocked kernels), and was wondering if it
> was possible to force
Hi,
I have a question about the ICU controller in the XO 1.75. I was
looking into porting over and extending the FIQ debugger onto the XO (which
allows debugging wedged/deadlocked kernels), and was wondering if it
was possible to force triggering a particular IRQ (not FIQ).
It's a feature common
