On 12/09/2013 04:26 AM, Robert Jördens wrote:
> the second demonstrates what I think is a bug in the signed Signals and
> comparison code. But I could not identify the culprit.
Applied and fixed that bug. Came from the fact that -1'sd1 is 1 in
Verilog (if the context has more bits)...
Sébastien
Hello,
the first patch fixes a bug that prevented signed Array()s while the
second demonstrates what I think is a bug in the signed Signals and
comparison code. But I could not identify the culprit. Maybe someone
else is quicker than me.
Regards,
--
Robert Jordens.
From 84292c0440325d9a2aa239e2d
