On Wed, Mar 25, 2015 at 08:59:31PM +, Dave Goodell (dgoodell) wrote:
> On Mar 25, 2015, at 3:02 PM, git...@crest.iu.edu wrote:
>
> > +static inline int32_t opal_atomic_swap_32( volatile int32_t *addr,
> > + int32_t newval)
> > +{
> > +int32_t oldval;
>
Right, that's why I'm recommending adding a comment so we don't have someone
flag this a third time :)
-Dave
On Mar 25, 2015, at 4:43 PM, George Bosilca wrote:
> I had the same impression but them I went and read the Intel documentation
> and xchg is one of these
I had the same impression but them I went and read the Intel documentation
and xchg is one of these exceptions where the lock is implicit.
George.
On Wed, Mar 25, 2015 at 4:59 PM, Dave Goodell (dgoodell) wrote:
> On Mar 25, 2015, at 3:02 PM, git...@crest.iu.edu wrote:
>
On Mar 25, 2015, at 3:02 PM, git...@crest.iu.edu wrote:
> +static inline int32_t opal_atomic_swap_32( volatile int32_t *addr,
> +int32_t newval)
> +{
> +int32_t oldval;
> +
> +__asm__ __volatile__("xchg %1, %0" :
This code *looks* buggy because it