On Fri, Oct 4, 2019 at 12:34 AM Sebastian Huber
wrote:
>
> On 02/10/2019 19:44, Gedare Bloom wrote:
> > On Wed, Oct 2, 2019 at 1:28 AM Sebastian Huber
> > wrote:
> >>
> >> Hello,
> >>
> >> the interrupt extension API implementation is already quite complex and
> >> not covered by the test suite:
On Mon, Oct 7, 2019 at 6:45 PM Chris Johns wrote:
>
> On 7/10/19 7:00 pm, Sebastian Huber wrote:
> > On 05/10/2019 01:05, Chris Johns wrote:
> >> On 4/10/19 5:55 pm, Sebastian Huber wrote:
> >>> On 04/10/2019 09:20, Chris Johns wrote:
> On 4/10/19 4:21 pm, Sebastian Huber wrote:
> > On 03
It's OK. I just realized I need to double check the riscv fenv.
I can queue up my posix_devctl patch pending the tools updating also.
--joel
On Wed, Oct 9, 2019 at 1:25 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> Hello Joel,
>
> I wait for an integration of some patches fo
Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board.
Update #3785.
Signed-off-by: Pragnesh Patel
---
Changes in v4:
- Revert fdt32_t *val to const in riscv_clock_get_timebase_frequency()
- make RISCV_ENABLE_FRDME310ARTY_SUPPORT consistent all over the code
- Revert to the defa