Re: sifive risc-v hifive unleashed bsp (qemu)

On Fri, Feb 12, 2021, 8:47 PM Rohan kumar wrote: > I will look into this in more detail and get back to you but in mean time > I want to contribute to any issues so can you suggest any thats need to be > solved or how do I look for from my own. > Projects or just smaller issues? There is a tag

Re: sifive risc-v hifive unleashed bsp (qemu)

I will look into this in more detail and get back to you but in mean time I want to contribute to any issues so can you suggest any thats need to be solved or how do I look for from my own. Thanks Sanskar On Fri, Feb 12, 2021, 3:01 PM Hesham Almatary wrote: > On Fri, 12 Feb 2021 at 11:24,

[PATCH 3/3] powerpc/shared: Fix warnings

From: Chris Johns --- bsps/powerpc/shared/vme/bspVmeDmaList.c | 3 ++- bsps/powerpc/shared/vme/vmeTsi148.c | 15 +-- bsps/powerpc/shared/vme/vmeUniverse.c | 8 +--- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/bsps/powerpc/shared/vme/bspVmeDmaList.c

[PATCH 2/3] powerpc/motorola_powerpc: Fix tm27 warnings

From: Chris Johns --- bsps/powerpc/motorola_powerpc/include/tm27.h | 24 +--- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/bsps/powerpc/motorola_powerpc/include/tm27.h b/bsps/powerpc/motorola_powerpc/include/tm27.h index 4d616cb3ed..15e66f2a81 100644 ---

[PATCH 1/3] score: Fix warning in thread queue ops

From: Chris Johns --- cpukit/score/src/threadqops.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cpukit/score/src/threadqops.c b/cpukit/score/src/threadqops.c index ef20431178..d6ba9dad57 100644 --- a/cpukit/score/src/threadqops.c +++ b/cpukit/score/src/threadqops.c

Re: [PATCH v2] Update motorola_power to irq-generic interrupt management

On Fri, Feb 12, 2021 at 7:38 PM wrote: > From: Chris Johns > > - Add support to the BSP to enable irq-generic management > > - Update the powerpc shared irq code to support irq-generic. This > is an option in option for existing powerpc bsps. This change > Probably just an option. :) I'm

[PATCH v2] Update motorola_power to irq-generic interrupt management

From: Chris Johns - Add support to the BSP to enable irq-generic management - Update the powerpc shared irq code to support irq-generic. This is an option in option for existing powerpc bsps. This change should be simpler now - Fix a number of issues in ISA IRQ controller handling by

Re: [PATCH 0/3] bsps/zynq: Add cadence-SPI driver

On 13/2/21 10:18 am, Kinsey Moore wrote: > On 12/2/21 5:14 am, Chris Johns wrote: >> On 13/2/21 10:10 am, Joel Sherrill wrote: >>> On Fri, Feb 12, 2021 at 5:06 PM Chris Johns >> > wrote: >>> >>> On 13/2/21 12:25 am, Jan Sommer wrote: >>> > This patchset implements

RE: [PATCH 0/3] bsps/zynq: Add cadence-SPI driver

On 12/2/21 5:14 am, Chris Johns wrote: >On 13/2/21 10:10 am, Joel Sherrill wrote: >> On Fri, Feb 12, 2021 at 5:06 PM Chris Johns > > wrote: >> >> On 13/2/21 12:25 am, Jan Sommer wrote: >> > This patchset implements a driver for the cadence-spi >> > device of

Re: [PATCH 0/3] bsps/zynq: Add cadence-SPI driver

On 13/2/21 10:10 am, Joel Sherrill wrote: > On Fri, Feb 12, 2021 at 5:06 PM Chris Johns > wrote: > > On 13/2/21 12:25 am, Jan Sommer wrote: > > This patchset implements a driver for the cadence-spi > > device of the Xilinx Zynq-7000 based SoCs  using the

Re: [PATCH 0/3] bsps/zynq: Add cadence-SPI driver

On Fri, Feb 12, 2021 at 5:06 PM Chris Johns wrote: > On 13/2/21 12:25 am, Jan Sommer wrote: > > This patchset implements a driver for the cadence-spi > > device of the Xilinx Zynq-7000 based SoCs using the spidev API.s > > Thanks for the driver. > > A quick review of the differences between the

Re: [PATCH 0/3] bsps/zynq: Add cadence-SPI driver

On 13/2/21 12:25 am, Jan Sommer wrote: > This patchset implements a driver for the cadence-spi > device of the Xilinx Zynq-7000 based SoCs using the spidev API.s Thanks for the driver. A quick review of the differences between the Zynq and Ulttrascale in this document from Xilinx:

Re: [PATCH] Update motorola_power to irq-generic interrupt management

On 13/2/21 7:35 am, Gedare Bloom wrote: > On Fri, Feb 12, 2021 at 1:00 PM wrote: >> >> From: Chris Johns >> >> - Add support to the BSP to enable irq-generic management >> >> - Update the powerpc shared irq code to support irq-generic. This >> is an option in option for existing powerpc bsps.

Re: [PATCH] Update motorola_power to irq-generic interrupt management

On Fri, Feb 12, 2021 at 1:00 PM wrote: > > From: Chris Johns > > - Add support to the BSP to enable irq-generic management > > - Update the powerpc shared irq code to support irq-generic. This > is an option in option for existing powerpc bsps. This change > should be simpler now > > - Fix a

PowerPC Exception warnings

Hello, The mvme2703 BSP is producing warnings for these lines of code: https://git.rtems.org/rtems/tree/bsps/powerpc/shared/exceptions/ppc_exc.S#n132 https://git.rtems.org/rtems/tree/bsps/powerpc/shared/exceptions/ppc_exc.S#n135 The warnings is:

[PATCH] Update motorola_power to irq-generic interrupt management

From: Chris Johns - Add support to the BSP to enable irq-generic management - Update the powerpc shared irq code to support irq-generic. This is an option in option for existing powerpc bsps. This change should be simpler now - Fix a number of issues in ISA IRQ controller handling by

Re: [PATCH v2 1/3] assert.h: Add macros to assert status and use it

Hi Ryan, On Fri, Feb 12, 2021 at 8:11 AM Ryan Long wrote: > > These macros are to be used to check the status from calls that are flagged by > Coverity as 'Unchecked return value'. > > Fix file assert.h Thanks for these updates, it's almost there. Can you open a ticket related to this feature

[PATCH v2 3/3] rtems-debugger-target.c: Fix Coverity Dereference before null check

Fixes CID #1468682 where target is dereferenced before it has been checked as to whether it is null or not in the rtems_debugger_target_swbreak_control function. Fix file rtems-debugger-target.c --- cpukit/libdebugger/rtems-debugger-target.c | 6 -- 1 file changed, 4 insertions(+), 2

[PATCH v2 2/3] consolesimpletask.c: Fix Coverity Unchecked return value

Fixes CID #1437625 and #1472765 where the return value of rtems_task_create and rtems_task_start is discarded. Fix file consolesimpletask.c --- cpukit/libcsupport/src/consolesimpletask.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git

[PATCH v2 0/3] Fix for Coverity issues

Hi, Here are the patches with the suggested changes. The macros are now _Assert_Unused_variable equals and _Assert_Unused_variable_unequal. I made the corresponding change in consolesimpletask.c. In rtems-debugger-target.c, I moved the declaration of the swbreaks variable back to the top of the

[PATCH v2 1/3] assert.h: Add macros to assert status and use it

These macros are to be used to check the status from calls that are flagged by Coverity as 'Unchecked return value'. Fix file assert.h --- cpukit/include/rtems/score/assert.h | 30 ++ 1 file changed, 30 insertions(+) diff --git a/cpukit/include/rtems/score/assert.h

Re: [PATCH 0/4] RISC-V: NOEL-V BSP

Hi, Thanks all for your comments. The logs have been attached, I'm a bit unsure why the PSXKEY07 was reported as a failure from the log, we should probably double check that can get back to you. /Daniel On 2021-02-09 16:59, Sebastian Huber wrote: On 08/02/2021 20:44, Daniel

[PATCH 1/3] bsps/xilinx_zynq: Add SPI driver for cadence-spi

--- .../include/bsp/cadence-spi-regs.h| 84 .../arm/xilinx-zynq/include/bsp/cadence-spi.h | 48 ++ bsps/arm/xilinx-zynq/spi/cadence-spi.c| 437 ++ 3 files changed, 569 insertions(+) create mode 100644 bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h

[PATCH 3/3] bsps/xilinx_zynq: Add SPI driver to autotools build

--- bsps/arm/xilinx-zynq/headers.am | 2 ++ c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 3 +++ 2 files changed, 5 insertions(+) diff --git a/bsps/arm/xilinx-zynq/headers.am b/bsps/arm/xilinx-zynq/headers.am index 47738c62be..c70be4 100644 --- a/bsps/arm/xilinx-zynq/headers.am

[PATCH 2/3] bsps/xilinx_zynq: Add SPI driver to waf

--- spec/build/bsps/arm/xilinx-zynq/obj.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/spec/build/bsps/arm/xilinx-zynq/obj.yml b/spec/build/bsps/arm/xilinx-zynq/obj.yml index 6602b20a03..c41ba9af98 100644 --- a/spec/build/bsps/arm/xilinx-zynq/obj.yml +++

[PATCH 0/3] bsps/zynq: Add cadence-SPI driver

This patchset implements a driver for the cadence-spi device of the Xilinx Zynq-7000 based SoCs using the spidev API. Jan Sommer (3): bsps/xilinx_zynq: Add SPI driver for cadence-spi bsps/xilinx_zynq: Add SPI driver to waf bsps/xilinx_zynq: Add SPI driver to autotools build

Re: sifive risc-v hifive unleashed bsp (qemu)

On Fri, 12 Feb 2021 at 11:24, Sanskar Khandelwal wrote: > > Hello joel, > > 1. #4162 : sifive risc-v hifive unleashed bsp (qemu) > As you mentioned this a good project i thought to search more about this > project I learned a lot while doing so but I still don't understand what is > the goal of

sifive risc-v hifive unleashed bsp (qemu)

Hello joel, 1. #4162 : sifive risc-v hifive unleashed bsp (qemu) As you mentioned this a good project i thought to search more about this project I learned a lot while doing so but I still don't understand what is the goal of this project (the description on

Re: [PATCH 3/4 v2] bsp/riscv: work area size based on stack pointer

On Fri, 12 Feb 2021 at 10:50, Daniel Hellstrom wrote: > > From: Martin Aberg > > Remember the initial stack pointer in start.S. It can later be used to > determine top of RAM. > --- > bsps/riscv/include/bsp/start.h | 65 > ++ >

[PATCH 4/4 v2] bsp/riscv: Add NOEL-V BSP build specification

From: Martin Aberg --- spec/build/bsps/riscv/noel/abi.yml | 48 +++ spec/build/bsps/riscv/noel/bspnoel32im.yml | 19 + spec/build/bsps/riscv/noel/bspnoel32imafd.yml | 19 + spec/build/bsps/riscv/noel/bspnoel64imac.yml | 19 +

[PATCH 3/4 v2] bsp/riscv: work area size based on stack pointer

From: Martin Aberg Remember the initial stack pointer in start.S. It can later be used to determine top of RAM. --- bsps/riscv/include/bsp/start.h | 65 ++ bsps/riscv/shared/start/bspgetworkarea-fromstack.c | 53 ++

[PATCH] bsp/riscv: move riscv/riscv build spec one level up

From: Martin Aberg These build specifications can be useful for other BSPs aswell. --- spec/build/bsps/riscv/{riscv => }/objsmp.yml | 0 spec/build/bsps/riscv/{riscv => }/optextirqmax.yml | 0 spec/build/bsps/riscv/{riscv => }/optfdtcpyro.yml | 0 spec/build/bsps/riscv/{riscv =>