Re: [PATCH] c-user: Add "Cache Manager" chapter

On 10/09/2021 10:49, Sebastian Huber wrote: The Cache Manager directives are available via . Document most of them in the Classic API Guide. Not documented are the following directive since the API is not yet stable: * rtems_cache_coherent_allocate() * rtems_cache_coherent_free() *

Re: The compiler settings for Cortex-M4

Hello Andrei, I modified the flags, could you please check if this fixed the problem? -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht:

Re: [PATCH v4] improve the format of error reporting on i386

Gedare told me just to change the ID when I submitted the other I sent you in discord. Sorry for things bouncing back and forth. On Mon, 13 Sept 2021 at 23:44, Joel Sherrill wrote: > On Sun, Sep 12, 2021 at 7:02 PM zack leung > wrote: > > > > Thread id is now a Hex value. > > Updates #4203 > >

Re: RSB

On Mon, Sep 13, 2021 at 6:54 PM Chris Johns wrote: > > On 13/9/21 11:20 pm, Joel Sherrill wrote: > > Hi > > > > If building a bset tar file, does it matter if the installation prefix > > is writable? > > > > ../source-builder/sb-set-builder --bset-tar-file --log=l-i386.txt > >

Re: RSB

On 13/9/21 11:20 pm, Joel Sherrill wrote: > Hi > > If building a bset tar file, does it matter if the installation prefix > is writable? > > ../source-builder/sb-set-builder --bset-tar-file --log=l-i386.txt > --prefix=/rtems/tools 5/rtems-i386 > RTEMS Source Builder - Set Builder, 5

Re: [PATCH v4] improve the format of error reporting on i386

On Sun, Sep 12, 2021 at 7:02 PM zack leung wrote: > > Thread id is now a Hex value. > Updates #4203 > --- > cpukit/score/cpu/i386/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/cpukit/score/cpu/i386/cpu.c b/cpukit/score/cpu/i386/cpu.c > index 77b7a7161c..06af57418d

Re: [PATCH 1/1] v3: Implemention of Condclockwait and Test

On Wed, Aug 25, 2021 at 7:42 AM Matt Joyce wrote: > > Added implementation of the pthread_cond_clockwait() > method to cpukit/posix/src/condclockwait.c. Additional > logic added to condwaitsupp.c to implement the new > method. Pthread_cond_clockwait() has been added to the > Issue 8 POSIX

The compiler settings for Cortex-M4

Hello, I guess this is mostly a question for Sebastian. While you were away, a bunch of us figured out that gcc for CM4 is using the wrong instruction set for multilib (?). Can you take a look at issue #4504 please? (I’m pretty sure I didn’t express that correctly, but I have put all of

[PATCH v1] pxcdevctl: Adjust for standard (5 branch)

psxdevctl is supposed to return the value in errno. Before, it was returning -1 and setting errno. Changed the tests to reflect these changes. Added code from RRADE's posix_devctl.c. Closes #4505 --- cpukit/libcsupport/src/posix_devctl.c | 80 ++

[PATCH v1] pxcdevctl: Adjust for standard

psxdevctl is supposed to return the value in errno. Before, it was returning -1 and setting errno. Changed the tests to reflect these changes. Added code from RRADE's posix_devctl.c. Closes #4506 --- cpukit/libcsupport/src/posix_devctl.c | 80 ++

[PATCH RSB v1 2/2] rtems-gcc-head-newlib-head.cfg: Add newlib patch

Adds patch to add sanitation to the padding of bits and size_t types for AArch64 tools builds with newlib. These changes have been made in ARM, but newlib has yet to pull them. This can be removed once newlib has pulled the code. Updates #4510 ---

[PATCH RSB v1 0/2] Update newlib for ILP32

Hi, These patches add some of the code that we are waiting for newlib to pull. Thanks, Ryan Ryan Long (2): rtems-gcc-10-newlib-head.cfg: Add newlib patch rtems-gcc-head-newlib-head.cfg: Add newlib patch rtems/config/tools/rtems-gcc-10-newlib-head.cfg | 3 +++

[PATCH RSB v1 1/2] rtems-gcc-10-newlib-head.cfg: Add newlib patch

Adds patch to add sanitation to the padding of bits and size_t types for AArch64 tools builds with newlib. These changes have been made in ARM, but newlib has yet to pull them. This can be removed once newlib has pulled the code. Updates #4510 --- rtems/config/tools/rtems-gcc-10-newlib-head.cfg

RSB

Hi If building a bset tar file, does it matter if the installation prefix is writable? ../source-builder/sb-set-builder --bset-tar-file --log=l-i386.txt --prefix=/rtems/tools 5/rtems-i386 RTEMS Source Builder - Set Builder, 5 (c7870f6e6199) error: prefix is not writable: /rtems/tools It does if

Re: [PATCH] eng: Add register block specification types

On 13/09/2021 10:43, Chris Johns wrote: On 13/9/21 4:38 pm, Sebastian Huber wrote: This approach is not limited to memory mapped register blocks. I think it is. I would like to understand how bus types other than "memory" are specified for a generic device driver that needs to handle bus

Re: [PATCH] eng: Add register block specification types

On 13/9/21 4:38 pm, Sebastian Huber wrote: > This approach is not limited to memory mapped register blocks. I think it is. I would like to understand how bus types other than "memory" are specified for a generic device driver that needs to handle bus variability. I am concerned this is bespoke

Re: [PATCH] eng: Add register block specification types

On 12/09/2021 03:32, Chris Johns wrote: On 11/9/21 12:41 am, Sebastian Huber wrote: A register block may be used to specify the memory-mapped interface to the hardware. Register blocks consist of register block members. Register block members are either instances of registers or instances of

Re: [PATCH] eng: Add register block specification types

On 11/09/2021 19:59, Joel Sherrill wrote: On Fri, Sep 10, 2021, 9:41 AM Sebastian Huber > wrote: A register block may be used to specify the memory-mapped interface to the hardware.  Register blocks consist of register block members.

Re: [PATCH] eng: Add register block specification types

On 11/09/2021 19:53, Gedare Bloom wrote: + start + The attribute value shall be an integer number. It shall be the start bit + of the bit field. + is it necessary to explain anywhere the convention that bit 0 is the last, least-significant bit of a register? I added a notice that