On 21/12/2022 21:54, Kinsey Moore wrote:
+includes:
+- bsps/include/xilinx_support/
+- bsps/include/xilinx_support/${XIL_SUPPORT_PATH}/
Is the xilinx_support a name from you or Xilinx? Maybe just name it
xilinx or xil to make the paths shorter.
Could you please add a notice to the commit
On 21.12.22 12:21, Hesham Almatary wrote:
Would it still be fine to
default all RV64 BSPs to medany (and remove medlow) so that we start
all of RISC-V BSPs at 0x8000? If so I'll submit modified patches
and edit the ticket accordingly.
Yes, this makes sense. It seems that the medlow model
On Mon, 19 Dec 2022 at 16:29, Sebastian Huber
wrote:
>
> Hello Hesham,
>
> On 18/12/2022 15:27, heshamelmat...@gmail.com wrote:
> > From: Hesham Almatary
> >
> > Currently generic RISC-V BSPs (riscv/riscv) that start with rv* and not
> > rv*_medany will start at 0x7000. This adds high
