From: Aaron Nyholm
---
rtemsbsd/rtems/rtems-bsd-rc-conf.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/rtemsbsd/rtems/rtems-bsd-rc-conf.c
b/rtemsbsd/rtems/rtems-bsd-rc-conf.c
index d559c256..f4cc987b 100644
--- a/rtemsbsd/rtems/rtems-bsd-rc-conf.c
+++ b/rtemsbsd/rtems/
From: Aaron Nyholm
---
rtemsbsd/rtems/rtems-bsd-rc-conf.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/rtemsbsd/rtems/rtems-bsd-rc-conf.c
b/rtemsbsd/rtems/rtems-bsd-rc-conf.c
index d559c256..f4cc987b 100644
--- a/rtemsbsd/rtems/rtems-bsd-rc-conf.c
+++ b/rtemsbsd/rtems/
On 16/3/2023 5:59 pm, Sebastian Huber wrote:
> In SMP configurations, check that we run on a configured processor. If not,
> then there is not much what can be done since we do not have a stack available
not much that can be done ?
No comment on the actual patch as I do not know RISCV
On 16/3/2023 6:13 pm, Sebastian Huber wrote:
> Hello Aaron,
>
> this API seems to be RTEMS-specific. Maybe we should simply pick up an
> existing
> solution which is in more wide spread use, for example:
>
> https://docs.zephyrproject.org/latest/hardware/peripherals/flash.html
That interface se
Hi Sebastian,
I applied these three patches after my patches and ran them on my K210
board and simulator. I have a set of 12 tests including benchmarks, SMP01,
SMP08, ticker, etc. Everything ran OK.
Is there anything in particular I can try to test them like setting the
maximum CPUs to 1? (K210 is
Hi
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This adds a helper function to read the ECC status for an ECC unit in
SPI-attached NOR memory.
---
bsps/include/dev/spi/xqspipsu-flash-helper.h | 29 +++
bsps/include/dev/spi/xqspipsu_flash_config.h | 1 +
bsps/shared/dev/spi/xqspipsu-flash-helper.c | 223 +++
3 files changed,
On 3/16/23 14:34, Sebastian Huber wrote:
On 16.03.23 14:28, Karel Gardas wrote:
+description: |
+ Default value of the ARM MPU CTRL register
+default:
+- enabled-by:
+ - arm/imxrt1052
+ - arm/stm32h7
+ - arm/nucleo-h743zi
+ - arm/stm32h7b3i-dk
+ - arm/stm32h747i-disco
+ - arm/stm32h757i-e
On 16.03.23 14:28, Karel Gardas wrote:
+description: |
+ Default value of the ARM MPU CTRL register
+default:
+- enabled-by:
+ - arm/imxrt1052
+ - arm/stm32h7
+ - arm/nucleo-h743zi
+ - arm/stm32h7b3i-dk
+ - arm/stm32h747i-disco
+ - arm/stm32h757i-eval
+ value: (ARMV7M_MPU_CTRL_ENABLE | AR
Due to API change, the patch also fixes affected BSPs and uses
value provided by MPU CTRL spec option there.
Sponsored-By: Precidata
---
bsps/arm/imxrt/start/bspstarthooks.c | 2 +-
.../stm32h7/boards/stm/nucleo-h743zi/stm32h7-bspstarthooks.c | 2 +-
.../stm32h7/boar
The patch also enables usage of the option on imxrt and stm32h7 based BSPs.
Sponsored-By: Precidata
---
spec/build/bsps/arm/imxrt/bspimxrt.yml | 2 ++
spec/build/bsps/arm/optmpuctrl.yml | 25 +
spec/build/bsps/arm/stm32h7/grp.yml| 2 ++
3 files changed, 29 inse
---
cpukit/doxygen/top-level-groups.h | 9 +
cpukit/include/machine/_kernel_cpuset.h | 2 ++
cpukit/include/machine/_kernel_in.h | 2 ++
cpukit/include/machine/_kernel_in6.h| 2 ++
cpukit/include/machine/_kernel_mman.h | 2 ++
cpukit/include/machine/_kernel_param.h | 2 ++
On 16.03.23 10:37, Karel Gardas wrote:
On 3/16/23 10:19, Sebastian Huber wrote:
On 16.03.23 10:14, Karel Gardas wrote:
This patch makes MPU setup more generic by adding capability to set
also control register. This way BSPs are allowed to enable MPU
also for hard faults by simply not setting
On 3/16/23 10:19, Sebastian Huber wrote:
On 16.03.23 10:14, Karel Gardas wrote:
This patch makes MPU setup more generic by adding capability to set
also control register. This way BSPs are allowed to enable MPU
also for hard faults by simply not setting PRIVDEFENA attribute
to control register.
On 16.03.23 10:14, Karel Gardas wrote:
This patch makes MPU setup more generic by adding capability to set
also control register. This way BSPs are allowed to enable MPU
also for hard faults by simply not setting PRIVDEFENA attribute
to control register. Compatibility with previous behavior and A
This patch makes MPU setup more generic by adding capability to set
also control register. This way BSPs are allowed to enable MPU
also for hard faults by simply not setting PRIVDEFENA attribute
to control register. Compatibility with previous behavior and API
is preserved.
Sponsored-By: Precida
Hello Aaron,
this API seems to be RTEMS-specific. Maybe we should simply pick up an
existing solution which is in more wide spread use, for example:
https://docs.zephyrproject.org/latest/hardware/peripherals/flash.html
--
embedded brains GmbH
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
In SMP configurations, check that we run on a configured processor. If not,
then there is not much what can be done since we do not have a stack available
for this processor. Just loop forever in this case. Do this in assemlby to
ensure that no stack memory is used.
---
bsps/riscv/riscv/start/b
Use the mtimecmp from the PLIC/CLINT initialization in the clock driver. This
register is defined by the device tree and does not assume a fixed mapping.
---
bsps/riscv/riscv/clock/clockdrv.c | 41 +++
1 file changed, 15 insertions(+), 26 deletions(-)
diff --git a/bsp
Take a non-zero RISCV_BOOT_HARTID into account.
---
bsps/riscv/riscv/start/bspsmp.c | 2 +-
bsps/riscv/riscv/start/bspstart.c | 10 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/bsps/riscv/riscv/start/bspsmp.c b/bsps/riscv/riscv/start/bspsmp.c
index ce5792f5b8..3479
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