Yes, sorry about that. I apparently haven't added the subject tweak to this
repo yet.
Thanks,
Kinsey
On Thu, Sep 21, 2023 at 7:02 PM Chris Johns wrote:
> I assume this is in the network services repo?
>
> OK and thanks
>
> Chris
>
> On 22/9/2023 4:38 am, Kinsey Moor
Expose a function to read the NOR flash chip ID information beyond the
minimum 3 bytes for the lookup table.
---
bsps/include/dev/spi/xqspipsu-flash-helper.h | 15 +++
bsps/shared/dev/spi/xqspipsu-flash-helper.c | 45 +---
2 files changed, 44 insertions(+), 16 deletions(-)
di
This adds a function to allow reading of the SFDP configuration space
that describes attributes of NOR flash chips.
---
bsps/include/dev/spi/xqspipsu-flash-helper.h | 20
bsps/include/dev/spi/xqspipsu_flash_config.h | 1 +
bsps/shared/dev/spi/xqspipsu-flash-helper.c | 48 +++
lwIP includes more than the bare address structures in its accounting of
the total addrinfo struct size. Ensure that lwIP gets the correct
address size.
---
bsd/freebsd/contrib/ntp/ntpq/ntpq.c | 8
1 file changed, 8 insertions(+)
diff --git a/bsd/freebsd/contrib/ntp/ntpq/ntpq.c
b/bsd/fr
On Thu, Sep 21, 2023 at 10:23 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> On 21.09.23 17:06, Kinsey Moore wrote:
> > On Thu, Sep 21, 2023 at 10:01 AM Sebastian Huber
> > > <mailto:sebastian.hu...@embedded-brains.de>> wrote:
> >
> &
On Thu, Sep 21, 2023 at 10:01 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> On 21.09.23 16:52, Kinsey Moore wrote:
> > On Thu, Sep 21, 2023 at 9:47 AM Sebastian Huber
> > > <mailto:sebastian.hu...@embedded-brains.de>> wrote:
> >
> &
On Thu, Sep 21, 2023 at 9:56 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> Hello Kinsey,
>
> I added a test case for
>
> https://devel.rtems.org/ticket/4955
>
> which started as a sparc-specific bug. The test case should also work on
> aarch64. In uniprocessor configurations, i
On Thu, Sep 21, 2023 at 9:47 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> On 20.09.23 20:35, Kinsey Moore wrote:
> [...]
> > @@ -1306,8 +1307,22 @@ static void process_delayed_work(void)
> > while (!rtems_chain_is_tail(&
The code here was developed under RTEMS_DEBUG=true which automatically
sets nodes off-chain upon extraction. Extraction does not set nodes
off-chain when not running under RTEMS_DEBUG=true. This code relies on
this behavior, so set nodes off-chain as needed.
Updates #4956
---
cpukit/libfs/src/jff
Use unprotected chain calls for delayed write workqueues since these
calls are either protected by locks or only operate on local chains and
are never accessed from interrupt context.
Updates #4956
---
cpukit/libfs/src/jffs2/src/fs-rtems.c | 10 +-
1 file changed, 5 insertions(+), 5 delet
Note that this patch only applies to the 6-freebsd-12 branch because the
code it affects does not exist in the master branch.
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
The documentation for this function suggests that it can handle invalid
descriptors safely. This change allows negative descriptors to be
handled without a crash.
---
rtemsbsd/include/machine/rtems-bsd-libio.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/rtemsbsd/inclu
When a buffer is modified by both hardware components such as DMA and by
software components, the buffer cache state must be kept in sync so that
data is not accidentally thrown away during future invalidations.
---
bsps/shared/dev/nand/xnandpsu.c | 6 ++
1 file changed, 6 insertions(+)
diff
When polling hardware registers in high performance situations, don't
rely on usleep or other standard sleep functions since they will
necessarily rely on kernel ticks to be woken up. This can easily cause
an immense reduction in throughput.
---
bsps/shared/dev/nand/xnandpsu.c | 15 +++
On Mon, Sep 11, 2023 at 11:00 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> Hello Kinsey,
>
> since this patch fixes a bug, there should be a ticket. There should be
> also a test case which demonstrates the problem and shows that the patch
> fixes the issue.
>
> I'll open an i
On Tue, Sep 19, 2023 at 7:25 AM emanuel stiebler wrote:
> Anybody using CAN on the xilinx MPSoC? Does CON-FD work too?
>
Hi Emanuel,
Those drivers haven't been ported in from the embeddedsw repository yet
since I haven't had a need for them. If you want to try porting them into
RTEMS, the framew
The internal JFFS2 locking does not guarantee that delayed writes will
not step on other reads and writes to the device. This adds locking to
prevent that in the JFFS2 NAND interworking layer.
---
bsps/aarch64/xilinx-zynqmp/jffs2_xnandpsu.c | 30 ++---
1 file changed, 26 insertions
This moves delayed work to a temporary chain to prevent a locking
inversion between the delayed work lock and the alloc_sem lock. Delayed
work is now processed after the delayed work lock is released. Locking
order is any JFFS2 locks before the delayed work lock.
---
cpukit/libfs/src/jffs2/src/fs-
The changes here ensure correct cache maintenance around DMA operations.
One cache flush was missing and two cache invalidations occurred before
the corresponding read that would make them necessary.
---
bsps/shared/dev/nand/xnandpsu.c | 21 +
1 file changed, 21 insertions(+)
(cross posted from discord) I did some digging and it looks like the right
macros/defines to gate on are CPU_SOFTWARE_FP and CPU_HARDWARE_FP. The FP
code in the loadable module should only be present if at least one of those
is available and the definition in the host binary should only be present
On Thu, Aug 17, 2023 at 7:25 PM Chris Johns wrote:
> On 17/8/2023 10:43 pm, Kinsey Moore wrote:
> > On Wed, Aug 16, 2023 at 9:47 PM Chris Johns > <mailto:chr...@rtems.org>> wrote:
> >
> > On 17/8/2023 7:36 am, Kinsey Moore wrote:
> > > B
On Thu, Aug 17, 2023 at 7:11 AM Kinsey Moore
wrote:
> On Wed, Aug 16, 2023 at 9:42 PM Chris Johns wrote:
>
>> On 17/8/2023 6:30 am, Kinsey Moore wrote:
>> > The current ARM support in libdebugger does not cover Cortex-M series
>> > cores since it requires su
On Wed, Aug 16, 2023 at 9:47 PM Chris Johns wrote:
> On 17/8/2023 7:36 am, Kinsey Moore wrote:
> > Before the fatal-error test result type was introduced, minimum.exe was
> > classified as an invalid test since it lacked a proper test header and
> > trailer. This applies t
On Wed, Aug 16, 2023 at 9:42 PM Chris Johns wrote:
> On 17/8/2023 6:30 am, Kinsey Moore wrote:
> > The current ARM support in libdebugger does not cover Cortex-M series
> > cores since it requires support for CP14 system register accessor
> > instructions. Cortex-M serie
Before the fatal-error test result type was introduced, minimum.exe was
classified as an invalid test since it lacked a proper test header and
trailer. This applies the test exclusions to all test states to avoid
this happening again in the future.
---
tester/rt/report.py | 15 +++
1 f
The current ARM support in libdebugger does not cover Cortex-M series
cores since it requires support for CP14 system register accessor
instructions. Cortex-M series cores support debug monitor mode, but its
configuration is accessed by memory mapped registers instead of using
CP14. This omits buil
The MAIR index currently assigned (1) for uncached memory segments is
not configured properly for this purpose. Instead, this switches
uncached memory segment flags to MAIR index 2 which is properly
configured for uncached inner and outer shareable domains.
---
cpukit/score/cpu/aarch64/include/lib
This looks good to me.
Thanks,
Kinsey
On Sat, Aug 12, 2023 at 1:37 AM wrote:
> From: Chris Johns
>
> Closes #4943
> ---
> cpukit/libdl/rtl-mdreloc-aarch64.c | 17 +
> spec/build/cpukit/objdlaarch64.yml | 1 -
> 2 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a
rmatting changes
> - Macro renamings
>
> Regards,
> Utkarsh
>
> On Mon, Aug 7, 2023 at 8:49 PM Kinsey Moore
> wrote:
>
>> I would say that the content here is easily worth several patches. You've
>> got header rearrangements and other formatting changes mixed in w
I would say that the content here is easily worth several patches. You've
got header rearrangements and other formatting changes mixed in with macro
renamings, build system changes, and other things. One comment below on the
.gitignore. You've also got inconsistencies in usage of (C) vs (c).
On Su
On Fri, Jul 21, 2023 at 9:31 AM Karel Gardas
wrote:
>
>Folks,
>
> I'd like to propose and perform STM32 H7 HAL code update. Currently this
> HAL code is part of RTEMS source tree located inside bsps/arm/stm32h7
> subdirectory.
>
> As the patches are too big to be sent to the mailing list, I'm
This adds an option to allow operation of the CPU at its maximum
temperature range of 125F by reducing the CPU clock to 400MHz instead of
the 105F limit imposed by the default 480MHz CPU clock. This tradeoff is
detailed in table 122 in section 7.3.1 of the STM32H743VI datasheet. The
default remains
have to keep the BSP
changes private and upstream what I can.
Thanks,
Kinsey
On Tue, Jul 25, 2023 at 8:27 AM Karel Gardas
wrote:
> On 7/24/23 23:17, Kinsey Moore wrote:
>
> [...]
>
> > There is no other UART1 connector provided on the board. So I do not
> > see
>
On Mon, Jul 24, 2023 at 3:30 PM Karel Gardas
wrote:
>
> Hello Kinsey,
>
> honestly I don't know what to do about this patch. Let me explain a bit
> history behind STM32h7. It was originally submitted by embedded brains
> guys (Sebastian main, Christian added few things later) supporting the
> o
pported by RTEMS due to missing MCU support in old HAL
> code. I submitted new HAL patches last week but they are not in yet. So
> if this is not company secrete let me ask, what board you are using with
> UART7 connection?
>
> Thanks,
> Karel
>
> On 7/24/23 20:28, Kinsey Moore w
This change allows for the pins assigned to UART7 to be reconfigured via
config.ini.
---
bsps/arm/stm32h7/console/console-uart7-cfg.c| 4 ++--
spec/build/bsps/arm/stm32h7/grp.yml | 4
.../build/bsps/arm/stm32h7/optuart7gpiopins.yml | 17 +
.../build/bsps/arm/
This change allows configuration of all enabled UART clocks without
direct modificaton of the exiting BSP.
---
.../stm/stm32h743i-eval/stm32h7-config-per.c | 41 +--
1 file changed, 38 insertions(+), 3 deletions(-)
diff --git a/bsps/arm/stm32h7/boards/stm/stm32h743i-eval/stm32h7-
ned and fix also all SDRAM_1 occurances in linker
scripts and replace those with SDRAM_2_REMAP.
Or that at least how I understand it...
Thanks,
Karel
On 7/12/23 18:00, Kinsey Moore wrote:
According to the documentation in STM reference manuals RM0399 and
RM0433, the standard memory space
This adds support for the STM32H750B-DK discovery kit. This kit includes
a built-in STLINKv3 debugger which provides a USB serial bridge for
USART3. USART1 is routed to the Arduino header and USART2 is routed to
the STMOD connector. This BSP reuses what would otherwise be duplicated
files from the
According to the documentation in STM reference manuals RM0399 and
RM0433, the standard memory space for SDRAM bank 1 is 0xc000 to
0xcfff.
---
spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/spec/build/bsps/arm/stm32h7/link
On 7/11/2023 4:58 PM, Karel Gardas wrote:
On 7/11/23 23:26, Kinsey Moore wrote:
I'm not sure that anything I've done for testing would have verified
that the SDRAM is operating properly. I'll have to pull it back out
and give it a shot.
If you write just few char or i
On Tue, Jul 11, 2023 at 4:04 PM Karel Gardas
wrote:
> On 7/11/23 15:50, Kinsey Moore wrote:
> > This adds support for the STM32H750B-DK discovery kit. This kit includes
> > a built-in STLINKv3 debugger which provides a USB serial bridge for
> > USART3. USART1 is routed to t
This adds support for the STM32H750B-DK discovery kit. This kit includes
a built-in STLINKv3 debugger which provides a USB serial bridge for
USART3. USART1 is routed to the Arduino header and USART2 is routed to
the STMOD connector. This BSP reuses what would otherwise be duplicated
files from the
On Fri, Jul 7, 2023 at 12:04 PM Gedare Bloom wrote:
> On Thu, Jul 6, 2023 at 12:48 PM Kinsey Moore
> wrote:
> >
> > QEMU is known to fail certain tests intermittently due to clock tick
> > delivery issues. This defines those tests as intermittent for BSPs
> >
QEMU is known to fail certain tests intermittently due to clock tick
delivery issues. This defines those tests as intermittent for BSPs
intended to run on QEMU alone.
Updates #4922
Updates #4072
---
spec/build/bsps/aarch64/a53/tsta53.yml| 33 +
spec/build/bsps/aarch64/a72/tsta72.y
rtems_task_wake_after takes a parameter in terms of a count of clock
ticks and not a measure in a subunit of seconds. This updates
documentation to reflect that. This also makes obvious the caveat about
the first tick wait not being a whole tick and points the user at a
replacement for better accur
On Fri, Jun 30, 2023 at 11:58 AM Joel Sherrill wrote:
>
>
> On Fri, Jun 30, 2023 at 1:26 AM Sebastian Huber <
> sebastian.hu...@embedded-brains.de> wrote:
>
>> Hello,
>>
>> it seems the RTEMS 6.1 release is getting closer. We should think about
>> the tool versions for the release.
>>
>> For GCC,
Thanks, v2 coming shortly.
Kinsey
On Wed, Jun 28, 2023 at 1:28 PM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> On 28.06.23 20:22, Kinsey Moore wrote:
> > rtems_task_wake_after takes a parameter in terms of a count of clock
> > ticks and not a measure in
rtems_task_wake_after takes a parameter in terms of a count of clock
ticks and not a measure in a subunit of seconds. This updates
documentation to reflect that and recommends clock_nanosleep() for
applications requiring sleep for a time-based duration instead of a
count of clock ticks.
Updates #4
rtems_task_wake_after takes a parameter in terms of a count of clock
ticks and not a measure in a subunit of seconds. This updates
documentation to reflect that.
Updates #4772
---
c-user/scheduling-concepts/background.rst | 8
c-user/task/operations.rst| 6 +++---
2 files
rtems_task_wake_after takes a parameter in terms of a count of clock
ticks and not a measure in a subunit of seconds. This updates
documentation to reflect that and recommends clock_nanosleep() for
applications requiring sleep for a time-based duration instead of a
count of clock ticks.
Updates #4
On Tue, Jun 27, 2023 at 4:05 PM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> On 27.06.23 22:18, Kinsey Moore wrote:
> > diff --git a/c-user/task/directives.rst b/c-user/task/directives.rst
> > index c082b51..3334679 100644
> > --- a/c-user/task/dire
rtems_task_wake_after takes a parameter in terms of ticks and not any
time base. This updates documentation to reflect that and refers any
applications needing a time base to nanosleep or clock_nanosleep.
Closes #4772
---
c-user/scheduling-concepts/background.rst | 6 +++---
c-user/task/directiv
This commit breaks up the uLan directory and removes its ORIGIN and
COPYING metadata in favor of this repository being the authoritative
source of these sources as per the wishes of the originator of these
files. More information can be found here:
https://lists.rtems.org/pipermail/devel/2023-March
Note that this patch is for 6-freebsd-12 and its removal reduces the burden
to make the master branch match functionality.
On Tue, Jun 27, 2023 at 10:28 AM Kinsey Moore
wrote:
> This removes the workaround applied on the fly for QEMU that disables
> priority queueing. The priority
This removes the workaround applied on the fly for QEMU that disables
priority queueing. The priority queue interrupt was not previously
hooked up properly in QEMU and RSB now has the patches to allow it to
work.
---
freebsd/sys/dev/cadence/if_cgem.c | 26 +++---
1 file changed
The original version of this patch had a conflict between the two
interrupts where the program-viewable interrupt state could be
deasserted when it should have been asserted. The new version of this
patch resolves that conflict.
---
source-builder/config/qemu-5-1.cfg | 4 ++--
1 file changed, 2 in
Swap the zynqmp management console to interrupt-driven operation to
avoid losing data in under-polled situations.
---
bsps/aarch64/xilinx-zynqmp/console/console.c | 2 +-
bsps/aarch64/xilinx-zynqmp/include/bsp.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/bsps/aarch64
The NOR driver was not written with SMP systems and caching in mind.
This makes the IsBusy flag volatile for updates across cores and
introduces cache flushing and invalidation where necessary for data
manipulated by the DMA engine in the QSPI peripheral.
---
bsps/include/dev/spi/xqspipsu.h
This temporarily adds a patch to fix badly behaving CGEM peripherals
under QEMU. The referenced patch has been submitted for inclusion in
the upstream QEMU repository.
Updates #4919
---
source-builder/config/qemu-5-1.cfg | 4
1 file changed, 4 insertions(+)
diff --git a/source-builder/confi
Overall, this looks like great work! Thanks for contributing!
Just a couple of addons to Joel's comments below.
On Wed, Jun 14, 2023 at 8:49 AM Joel Sherrill wrote:
>
> On Wed, Jun 14, 2023 at 3:08 AM Philip Kirkpatrick <
> p.kirkpatr...@reflexaerospace.com> wrote:
>
> diff --git a/bsps/arm/xil
The page size ioctl requires an int pointer to retrieve the page size.
The test currently uses a size_t which mostly works fine for systems
where size_t and int are the same size, but can leave junk data in the
upper bits when they differ in size causing an assert in the test to
fail in some cases.
Looks good to me.
On Thu, Jun 8, 2023 at 4:33 AM wrote:
> From: Chris Johns
>
> ---
> rtems/config/net/net-services-1.cfg | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/rtems/config/net/net-services-1.cfg
> b/rtems/config/net/net-services-1.cfg
> index c342547..bf
This change causes NOR writes to be broken according to page boundaries.
Writes across page boundaries cause the writes beyond the boundary to
fail silently. This also introduces a new function that will explicitly
write pages.
---
bsps/include/dev/spi/xqspipsu-flash-helper.h | 25 ++-
bsp
When given the exact bounds of a sector, the current algorithm
calculates that 3 sectors need to be erased. This corrects the
calculation such that only 1 sector needs to be erased for erasures that
exactly match sector boundaries.
---
bsps/shared/dev/spi/xqspipsu-flash-helper.c | 19 +++--
Instead of statically defining the device parameters, use the device
information available via the NOR device layer's Flash Configuration
Table.
---
bsps/aarch64/xilinx-zynqmp/jffs2_xqspipsu.c | 12 +-
bsps/include/dev/spi/xqspipsu-flash-helper.h | 24
bsps/shared/dev
The definition for the s25fl512s flash chip is incorrect. This updates
the sector size and page size values to match the datasheet.
---
bsps/include/dev/spi/xqspipsu_flash_config.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/bsps/include/dev/spi/xqspipsu_flash_config.h
C) 2020 On-Line Applications Research Corporation (OAR)
> > - * Written by Kinsey Moore
> > + * Copyright (C) 2012, 2013 Deng Hengyi
>
> Is this change correct?
>
The file has absolutely trivial contents, so whether or not it matters I'm
willing to approve of the change if i
On Tue, May 23, 2023 at 2:26 AM Christian MAUDERER <
christian.maude...@embedded-brains.de> wrote:
> Hello,
>
> I recently updated the HAL in the i.MXRT BSP. I used the same approach
> that we use for a lot of similar cases: Import the sources into RTEMS
> and adapt them slightly so that they work
---
cpukit/libdl/rtl-mdreloc-aarch64.c | 4
1 file changed, 4 insertions(+)
diff --git a/cpukit/libdl/rtl-mdreloc-aarch64.c
b/cpukit/libdl/rtl-mdreloc-aarch64.c
index 25057ce9d7..46f87e9178 100644
--- a/cpukit/libdl/rtl-mdreloc-aarch64.c
+++ b/cpukit/libdl/rtl-mdreloc-aarch64.c
@@ -329,6 +3
This change looks good. Thanks!
On Mon, May 15, 2023 at 10:32 PM wrote:
> From: Tian Ye
>
> ---
> cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
> b/cpuki
This reverts commit 6ee31ae968323c71c478b2f52ec5a5cbff8c8f5d.
A fix has been committed to RTEMS pkgcfg and Makefile generation to
handle this issue and having this in place with the fix in RTEMS causes
a failure to build.
---
waf_libbsd.py | 29 -
1 file changed, 8 ins
I think we've been moving away from in-file comments in the YAML and toward
actual labels in the data, anyway. If it's important information, it should
be kept properly.
Kinsey
On Mon, Apr 24, 2023 at 8:55 AM Sam Price wrote:
> Yaml files can have comments, json files can’t. So you would lose
m>>
wrote:
Yes, it is purely informational. It just returns the 3-byte JEDEC ID.
Regards,
Aaron.
--- Original Message ---
On Monday, April 24th, 2023 at 12:35 PM, Kinsey Moore
wrote:
I noticed that there is provision here to pass through the JEDEC ID from the
physical dev
I noticed that there is provision here to pass through the JEDEC ID from
the physical device (obtained by a JEDEC parameter page read, ONFI
parameter page read, or other mechanism).
Is this intended to be purely informational?
Kinsey
On Thu, Apr 20, 2023 at 2:23 AM wrote:
> From: Aaron Nyholm
The MMU must be enabled during mapping changes and TLB invalidations.
When this is not the case, TLB updates do not occur correctly in all
cases. This is especially apparent when changing a block entry to a
table entry when remapping small memory ranges in an otherwise
contiguous block.
---
bsps/a
The MMU must be enabled during mapping changes and TLB invalidations.
When this is not the case, TLB updates do not occur correctly in all
cases. This is especially apparent when changing a block entry to a
table entry when remapping small memory ranges in an otherwise
contiguous block.
---
bsps/a
Resolve warnings about mismatched pointer and integer sizes in AArch64
libdl when building with the ILP32 ABI.
---
cpukit/libdl/rtl-elf.c | 4 ++--
cpukit/libdl/rtl-mdreloc-aarch64.c | 31 +++---
cpukit/libdl/rtl-rap.c | 4 ++--
3 files changed, 20
Do not warn about excessive shifts in imported Xilinx driver code when
building with the ILP32 ABI. The two instances of this warning produce
the desired effect of setting the upper address bits to 0.
---
spec/build/bsps/objnandpsu.yml | 3 ++-
spec/build/bsps/objqspipsu.yml | 3 ++-
2 files chang
On Mon, Apr 3, 2023 at 8:00 PM Chris Johns wrote:
> On 31/3/2023 8:13 am, Kinsey Moore wrote:
> > Xilinx wrote their A53 HAL with the assumption that the CPU did not
> > support cache invalidation without a flush, so the flush and
> > invalidation functions were c
Xilinx wrote their A53 HAL with the assumption that the CPU did not
support cache invalidation without a flush, so the flush and
invalidation functions were combined and all range invalidations are
promoted to flush/invalidate. The implementation written for lwIP was
written to the original intent
Do not try to alter IRQ server handlers while executing in the IRQ
server thread context. This change avoids a deadlock in CGEM error
condition handling that causes a reinitialization of the driver which
attempts to reinstall the IRQ handler from within the IRQ handler. This
deadlocks inside the IR
e/legacy_lwipopts.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2023 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+
This change moves the use of items configured in config.ini from using
-D to set defines on the command line to using a header built by waf.
This also resolves an issue where configuration parameters were bleeding
between BSPs when multiple BSPs were configured.
---
rtemslwip/include/lwipopts.h |
This patch and the mail subject look good. Thanks, Rick! I'll send this
over to Joel for commit tomorrow.
Kinsey
On Mon, Mar 27, 2023 at 7:31 PM wrote:
> From: Rick VanderWal
>
> This fixes an issue where the card present signal doesn't stabilize
> quickly and indicates present when no card i
On Mon, Mar 27, 2023 at 7:46 PM Chris Johns wrote:
> On 28/3/2023 2:28 am, Kinsey Moore wrote:
> > This change moves the use of items configured in config.ini from using
> > -D to set defines on the command line to using a header built by waf.
> > This also resolves an issu
---
c-user/symmetric_multiprocessing_services.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/c-user/symmetric_multiprocessing_services.rst
b/c-user/symmetric_multiprocessing_services.rst
index 89dc48c..9167ae9 100644
--- a/c-user/symmetric_multiprocessing_services.rst
+++
This change moves the use of items configured in config.ini from using
-D to set defines on the command line to using a header built by waf.
This also resolves an issue where configuration parameters were bleeding
between BSPs when multiple BSPs were configured.
---
rtemslwip/beaglebone/lwipopts.h
This removes directory scanning from rtems-lwip for a more robust build
system.
Closes #4889
---
defs/bsps/aarch64/xilinx_zynqmp_base.json | 6 +++---
.../aarch64/xilinx_zynqmp_hardware_base.json| 8
defs/bsps/aarch64/xilinx_zynqmp_ilp32_qemu.json | 9 ++---
.../bsps/aar
On Thu, Mar 23, 2023 at 7:19 PM Rick VanderWal
wrote:
>
> On 3/23/23 10:26, Kinsey Moore wrote:
>
> On Wed, Mar 22, 2023 at 7:02 PM wrote:
>
>>
>> + if (!(RD4(sc, SDHCI_PRESENT_STATE) & SDHCI_CARD_STABLE))
>> + {
>> + device
Some consumers of getifaddrs() depend on the loopback flag being set
appropriately to filter interfaces. Make sure that requirement is
satisfied.
---
rtemslwip/bsd_compat/ifaddrs.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/rtemslwip/bsd_compat/ifaddrs.c b/rtemslwip/bsd_compat/ifadd
Hey Rick,
This looks good for the most part and thanks for the contribution.
For future patches, please make sure you specify the repository in your
subject line if the patch isn't for the RTEMS repository. This can be
configured to occur automatically in your local per-repo git configuration
usin
This was added with the writebuffer work and should have been protected
by the error check.
---
cpukit/libfs/src/jffs2/src/fs-rtems.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/cpukit/libfs/src/jffs2/src/fs-rtems.c
b/cpukit/libfs/src/jffs2/src/fs-rtems.c
index bff7d
On Wed, Mar 22, 2023 at 4:00 PM Gedare Bloom wrote:
> On Mon, Mar 20, 2023 at 6:56 AM Joel Sherrill wrote:
> >
> > New issue from Coveriry.
> >
> > I vaguely recall that JFFS2 uses dynamic checks for things that static
> would work and Coveriry spots the dead code
> >
> > -- Forwarded me
On Tue, Mar 21, 2023 at 9:20 PM Chris Johns wrote:
> On 22/3/2023 1:18 pm, Kinsey Moore wrote:
> > On Tue, Mar 21, 2023 at 7:39 PM Chris Johns > <mailto:chr...@rtems.org>> wrote:
> >
> > On 22/3/2023 7:00 am, Kinsey Moore wrote:
> > > ---
>
On Tue, Mar 21, 2023 at 7:39 PM Chris Johns wrote:
> On 22/3/2023 7:00 am, Kinsey Moore wrote:
> > ---
> > user/bsps/aarch64/xilinx-zynqmp.rst | 9 +
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/user/bsps/aarch64/xilinx-zynqmp.rst
> b
---
user/bsps/aarch64/xilinx-zynqmp.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/user/bsps/aarch64/xilinx-zynqmp.rst
b/user/bsps/aarch64/xilinx-zynqmp.rst
index 1fef7a4..4de0115 100644
--- a/user/bsps/aarch64/xilinx-zynqmp.rst
+++ b/user/bsps/aarch64/xilinx-zynqmp.rst
@
---
user/bsps/aarch64/xilinx-zynqmp.rst | 9 +
1 file changed, 9 insertions(+)
diff --git a/user/bsps/aarch64/xilinx-zynqmp.rst
b/user/bsps/aarch64/xilinx-zynqmp.rst
index 4de0115..e30c3f6 100644
--- a/user/bsps/aarch64/xilinx-zynqmp.rst
+++ b/user/bsps/aarch64/xilinx-zynqmp.rst
@@ -250,
Joel,
This is fine for fixing the warnings for the time being. We still need to
address the AArch64 break due to binutils >= 2.40 (2.39 does not have the
bad patch).
Kinsey
On Tue, Mar 21, 2023 at 10:17 AM Joel Sherrill wrote:
> I'm ok with this if Kinsey confirms it
>
> On Tue, Mar 21, 2023, 4
This adds a helper function to read the ECC status for an ECC unit in
SPI-attached NOR memory.
---
bsps/include/dev/spi/xqspipsu-flash-helper.h | 29 +++
bsps/include/dev/spi/xqspipsu_flash_config.h | 1 +
bsps/shared/dev/spi/xqspipsu-flash-helper.c | 223 +++
3 files changed,
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