On Fri, Jul 20, 2018 at 11:46 AM, Sebastian Huber
wrote:
> - Am 20. Jul 2018 um 16:28 schrieb Gedare Bloom ged...@rtems.org:
>
>> I want to reiterate my comment that some ISAs have valid instructions
>> with an encoding of all zeroes. Off the top of my head, MIPS32 of all
>> 0s is the
- Am 20. Jul 2018 um 16:28 schrieb Gedare Bloom ged...@rtems.org:
> I want to reiterate my comment that some ISAs have valid instructions
> with an encoding of all zeroes. Off the top of my head, MIPS32 of all
> 0s is the encoding for sll $0, $0, 0, which is a nop.
Yes, I added some special
I want to reiterate my comment that some ISAs have valid instructions
with an encoding of all zeroes. Off the top of my head, MIPS32 of all
0s is the encoding for sll $0, $0, 0, which is a nop.
I am not too sure about the purpose of the test anymore, as if an
illegal instruction exception occurs,
On some architectures/simulators it is difficult to provoke an
exception with misaligned or illegal data loads. Use an illegal
instruction instead.
Update #3433.
---
cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h | 5 +
cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h | 5
