Update #4982. --- bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+)
diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h index d5583a1cca..1ca2bff685 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h @@ -355,6 +355,11 @@ typedef struct{ /* field: ROS - Reset on PLL Slip */ #define TMS570_SYS1_PLLCTL1_ROS BSP_BIT32(31) +/* field: BPOS - Bypass of PLL Slip */ +#define TMS570_SYS1_PLLCTL1_BPOS(val) BSP_FLD32(val,29, 30) +#define TMS570_SYS1_PLLCTL1_BPOS_GET(reg) BSP_FLD32GET(reg,29, 30) +#define TMS570_SYS1_PLLCTL1_BPOS_SET(reg,val) BSP_FLD32SET(reg, val,29, 30) + /* field: MASK_SLIP - Mask detection of PLL slip */ #define TMS570_SYS1_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30) #define TMS570_SYS1_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30) @@ -404,6 +409,28 @@ typedef struct{ #define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) +/*--------------------TMS570_SYS1_PLLCTL3--------------------*/ +/* field: ODPLL2 - Internal PLL Output Divider. */ +#define TMS570_SYS1_PLLCTL3_ODPLL2(val) BSP_FLD32(val, 29, 31) +#define TMS570_SYS1_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg, 29, 31) +#define TMS570_SYS1_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val, 29, 31) + +/* field: PLLDIV2 - PLL2 Output Clock Divider. */ +#define TMS570_SYS1_PLLCTL3_PLLDIV2(val) BSP_FLD32(val, 24, 28) +#define TMS570_SYS1_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg, 24, 28) +#define TMS570_SYS1_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val, 24, 28) + +/* field: REFCLKDIV2 - Reference Clock Divider. */ +#define TMS570_SYS1_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val, 16, 21) +#define TMS570_SYS1_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg, 16, 21) +#define TMS570_SYS1_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val, 16, 21) + +/* field: PLLMUL2 - PLL2 Multiplication Factor. */ +#define TMS570_SYS1_PLLCTL3_PLLMUL2(val) BSP_FLD32(val, 0, 15) +#define TMS570_SYS1_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define TMS570_SYS1_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val, 0, 15) + + /*--------------------TMS570_SYS1_SYSPC10--------------------*/ /* field: ECPCLK_SLEW - ECPCLK slew control. This bit controls between the fast or slow slew mode. */ #define TMS570_SYS1_SYSPC10_ECPCLK_SLEW BSP_BIT32(0) -- 2.35.3 _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel