On 12/07/2022 08:25, Chris Johns wrote:
On 11/7/2022 7:16 pm, Sebastian Huber wrote:
Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers. This fixes the build for the AArch32 target.
Add BSP options which define the initial values of CPU Interface reg
On 11/7/2022 7:16 pm, Sebastian Huber wrote:
> Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
> enable registers. This fixes the build for the AArch32 target.
>
> Add BSP options which define the initial values of CPU Interface registers.
> ---
> v3:
>
> * Fix vari
Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers. This fixes the build for the AArch32 target.
Add BSP options which define the initial values of CPU Interface registers.
---
v3:
* Fix variant-specific default values.
* Add BSP options for ICC_BPR0,
