--- bsps/arm/stm32f4/gpio/gpio.c | 555 ++++++++++++++++++ bsps/arm/stm32f4/include/bsp.h | 4 - bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 37 ++ bsps/arm/stm32f4/include/bsp/stm32f4_hal.h | 17 + bsps/arm/stm32f4/start/bspstart.c | 7 +- bsps/arm/stm32f4/start/bspstarthook.c | 8 + spec/build/bsps/arm/stm32f4/grp.yml | 6 +- spec/build/bsps/arm/stm32f4/obj.yml | 1 + spec/build/bsps/arm/stm32f4/optengpio.yml | 16 + .../build/bsps/arm/stm32f4/optnumgpioctrl.yml | 16 + 10 files changed, 658 insertions(+), 9 deletions(-) create mode 100644 bsps/arm/stm32f4/gpio/gpio.c create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_hal.h create mode 100644 spec/build/bsps/arm/stm32f4/optengpio.yml create mode 100644 spec/build/bsps/arm/stm32f4/optnumgpioctrl.yml
diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c new file mode 100644 index 0000000000..d7cac7fd58 --- /dev/null +++ b/bsps/arm/stm32f4/gpio/gpio.c @@ -0,0 +1,555 @@ +/** + * @file + * + * @ingroup rtems_bsp/arm/stm32f4 + * + * @brief RTEMS GPIO new API implementation for STM32F4. + * + * @note RTEMS_GPIO_PINMODE_BSP_SPECIFIC is Alternate mode for STM32F4 BSP + */ + +/* + * Copyright (c) 2022 Duc Doan <dtbpkmte at gmail.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <bsp.h> +#include <rtems.h> +#include <bsp/stm32f4_gpio.h> +#include <stdlib.h> + +/*********** Helpers *****************/ +/** + * @brief Macro to get stm32f4_gpio object from a base rtems_gpio + * object. + * + * This is a wrapper of RTEMS_CONTAINER_OF macro + * + * @param base The pointer to a rtems_gpio object + * @retval The pointer to the stm32f4_gpio object owning + * the specified rtems_gpio object + */ +#define get_gpio_from_base(base) \ + RTEMS_CONTAINER_OF(base, stm32f4_gpio, base) + +/*********** GPIO API ***************/ +static rtems_status_code stm32f4_gpio_get( + uint32_t interm_pin, + rtems_gpio **out +); + +static rtems_status_code stm32f4_gpio_destroy( + rtems_gpio *base +); + +static rtems_status_code stm32f4_gpio_init( + rtems_gpio *base +); + +static rtems_status_code stm32f4_gpio_deinit( + rtems_gpio *base +); + +static rtems_status_code stm32f4_gpio_set_pin_mode( + rtems_gpio *base, + rtems_gpio_pin_mode mode +); + +static rtems_status_code stm32f4_gpio_set_pull( + rtems_gpio *base, + rtems_gpio_pull pull +); + +static rtems_status_code stm32f4_gpio_configure_interrupt( + rtems_gpio *base, + rtems_gpio_isr isr, + void *arg, + rtems_gpio_interrupt_trig trig, + rtems_gpio_pull pull +); + +static rtems_status_code stm32f4_gpio_remove_interrupt( + rtems_gpio *base +); + +static rtems_status_code stm32f4_gpio_enable_interrupt( + rtems_gpio *base +); + +static rtems_status_code stm32f4_gpio_disable_interrupt( + rtems_gpio *base +); + +static rtems_status_code stm32f4_gpio_read( + rtems_gpio *base, + rtems_gpio_pin_state *value +); + +static rtems_status_code stm32f4_gpio_write( + rtems_gpio *base, + rtems_gpio_pin_state value +); + +static rtems_status_code stm32f4_gpio_toggle( + rtems_gpio *base +); + +/*********************************************************/ + +/** + * @brief STM32F4 GPIO handlers + */ +static const rtems_gpio_handlers stm32f4_gpio_handlers = { + .init = stm32f4_gpio_init, + .deinit = stm32f4_gpio_deinit, + .set_pin_mode = stm32f4_gpio_set_pin_mode, + .set_pull = stm32f4_gpio_set_pull, + .configure_interrupt = stm32f4_gpio_configure_interrupt, + .remove_interrupt = stm32f4_gpio_remove_interrupt, + .enable_interrupt = stm32f4_gpio_enable_interrupt, + .disable_interrupt = stm32f4_gpio_disable_interrupt, + .read = stm32f4_gpio_read, + .write = stm32f4_gpio_write, + .toggle = stm32f4_gpio_toggle +}; + +static GPIO_TypeDef * const GPIOx[] = { + GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, + GPIOF, GPIOG, GPIOH, GPIOI, +#ifdef STM32F429X + GPIOJ, GPIOK +#endif /* STM32F429X */ +}; + +static unsigned int const EXTIx_IRQn[] = { + EXTI0_IRQn, + EXTI1_IRQn, + EXTI2_IRQn, + EXTI3_IRQn, + EXTI4_IRQn, + EXTI9_5_IRQn, + EXTI9_5_IRQn, + EXTI9_5_IRQn, + EXTI9_5_IRQn, + EXTI9_5_IRQn, + EXTI15_10_IRQn, + EXTI15_10_IRQn, + EXTI15_10_IRQn, + EXTI15_10_IRQn, + EXTI15_10_IRQn, + EXTI15_10_IRQn +}; + +/** + * @brief Converts intermediate pin number to port pointer. + * + * Intermediate pin number is a way of numerically labeling + * pins. Pins are labeled incrementally across all ports. + * Pins 0-15 from port A are 0-15. Pins 0-15 from port B are + * 16-31. And so on. + * + * @param interm_pin is the intermediate pin number + */ +#define STM32F4_GET_PORT(interm_pin) (GPIOx[ ( interm_pin ) / 16 ]) + +/** + * @brief Converts intermediate pin number to 0-15. + * + * Intermediate pin number is a way of numerically labeling + * pins. Pins are labeled incrementally across all ports. + * Pins 0-15 from port A are 0-15. Pins 0-15 from port B are + * 16-31. And so on. + * + * @param interm_pin is the intermediate pin number + */ +#define STM32F4_GET_PIN_0_15(interm_pin) (( interm_pin ) % 16) + +/** + * @brief Converts pin number from 0-15 to HAL pin mask. + * @param pin is the pin number from 0-15 + */ +#define STM32F4_GET_HAL_GPIO_PIN(pin) ((uint16_t) (1 << ( pin ))) + +/** + * @brief Get EXTI Line from pin number 0-15 + * @param pin is the pin number from 0-15 + */ +#define STM32F4_GET_LL_EXTI_LINE(pin) (0x1UL << ( pin )) + +/** + * @brief Get EXTI IRQ number from pin 0-15 + * @param pin is the pin number from 0-15 + */ +#define STM32F4_GET_EXTI_IRQn(pin) (EXTIx_IRQn[( pin )]) + +/************** Interrupt manager *****************/ +typedef struct { + void *arg; + stm32f4_gpio *gpio; +} stm32f4_interrupt_arg; + +typedef struct { + stm32f4_interrupt_arg arg; + rtems_gpio_isr isr; +} stm32f4_interrupt; + +static stm32f4_interrupt isr_table[16]; + +void exti_handler(void *arg); + + +/********** STM32F4 GPIO API functions ************/ + +rtems_status_code bsp_gpio_register_controllers( + void +) +{ + return rtems_gpio_register( + stm32f4_gpio_get, + stm32f4_gpio_destroy, + sizeof(GPIOx)/sizeof(GPIOx[0])*16 + ); +} + +rtems_status_code stm32f4_gpio_get( + uint32_t interm_pin, + rtems_gpio **out +) +{ + stm32f4_gpio *tmp = malloc(sizeof(stm32f4_gpio)); + if (tmp == NULL) { + return RTEMS_NO_MEMORY; + } + tmp->base = (rtems_gpio) { .handlers = &stm32f4_gpio_handlers }; + tmp->pin = STM32F4_GET_PIN_0_15(interm_pin); + tmp->port = STM32F4_GET_PORT(interm_pin); + + *out = (rtems_gpio *) tmp; + return RTEMS_SUCCESSFUL; +} + +rtems_status_code stm32f4_gpio_destroy( + rtems_gpio *base +) +{ + stm32f4_gpio *gpio = get_gpio_from_base(base); + free(gpio); + return RTEMS_SUCCESSFUL; +} + +rtems_status_code stm32f4_gpio_init(rtems_gpio *base) { + stm32f4_gpio *gpio = get_gpio_from_base(base); + + switch ((uintptr_t) gpio->port) { + case (uintptr_t) GPIOA: + __HAL_RCC_GPIOA_CLK_ENABLE(); + break; + case (uintptr_t) GPIOB: + __HAL_RCC_GPIOB_CLK_ENABLE(); + break; + case (uintptr_t) GPIOC: + __HAL_RCC_GPIOC_CLK_ENABLE(); + break; + case (uintptr_t) GPIOD: + __HAL_RCC_GPIOD_CLK_ENABLE(); + break; + case (uintptr_t) GPIOE: + __HAL_RCC_GPIOE_CLK_ENABLE(); + break; + case (uintptr_t) GPIOF: + __HAL_RCC_GPIOF_CLK_ENABLE(); + break; + case (uintptr_t) GPIOG: + __HAL_RCC_GPIOG_CLK_ENABLE(); + break; + case (uintptr_t) GPIOH: + __HAL_RCC_GPIOH_CLK_ENABLE(); + break; + case (uintptr_t) GPIOI: + __HAL_RCC_GPIOI_CLK_ENABLE(); + break; +#ifdef STM32F429X + case (uintptr_t) GPIOJ: + __HAL_RCC_GPIOJ_CLK_ENABLE(); + break; + case (uintptr_t) GPIOK: + __HAL_RCC_GPIOK_CLK_ENABLE(); + break; +#endif /* STM32F429X */ + default: + return RTEMS_UNSATISFIED; + } + return RTEMS_SUCCESSFUL; +} + +rtems_status_code stm32f4_gpio_deinit(rtems_gpio *base) { +/* + stm32f4_gpio *gpio = get_gpio_from_base(base); + + switch ((uintptr_t) gpio->port) { + case (uintptr_t) GPIOA: + __HAL_RCC_GPIOA_CLK_DISABLE(); + break; + case (uintptr_t) GPIOB: + __HAL_RCC_GPIOB_CLK_DISABLE(); + break; + case (uintptr_t) GPIOC: + __HAL_RCC_GPIOC_CLK_DISABLE(); + break; + case (uintptr_t) GPIOD: + __HAL_RCC_GPIOD_CLK_DISABLE(); + break; + case (uintptr_t) GPIOE: + __HAL_RCC_GPIOE_CLK_DISABLE(); + break; + case (uintptr_t) GPIOF: + __HAL_RCC_GPIOF_CLK_DISABLE(); + break; + case (uintptr_t) GPIOG: + __HAL_RCC_GPIOG_CLK_DISABLE(); + break; + case (uintptr_t) GPIOH: + __HAL_RCC_GPIOH_CLK_DISABLE(); + break; + case (uintptr_t) GPIOI: + __HAL_RCC_GPIOI_CLK_DISABLE(); + break; +#ifdef STM32F429X + case (uintptr_t) GPIOJ: + __HAL_RCC_GPIOJ_CLK_DISABLE(); + break; + case (uintptr_t) GPIOK: + __HAL_RCC_GPIOK_CLK_DISABLE(); + break; +#endif + default: + return RTEMS_UNSATISFIED; + } + return RTEMS_SUCCESSFUL; +*/ + return RTEMS_NOT_IMPLEMENTED; +} + +rtems_status_code stm32f4_gpio_set_pin_mode( + rtems_gpio *base, + rtems_gpio_pin_mode mode +) +{ + stm32f4_gpio *gpio = get_gpio_from_base(base); + uint32_t pin_mask = STM32F4_GET_HAL_GPIO_PIN(gpio->pin); + + uint32_t stm32f4_mode, stm32f4_output_type; + switch (mode) { + case RTEMS_GPIO_PINMODE_OUTPUT_PP: + stm32f4_mode = LL_GPIO_MODE_OUTPUT; + stm32f4_output_type = LL_GPIO_OUTPUT_PUSHPULL; + break; + case RTEMS_GPIO_PINMODE_OUTPUT_OD: + stm32f4_mode = LL_GPIO_MODE_OUTPUT; + stm32f4_output_type = LL_GPIO_OUTPUT_OPENDRAIN; + break; + case RTEMS_GPIO_PINMODE_INPUT: + stm32f4_mode = LL_GPIO_MODE_INPUT; + break; + case RTEMS_GPIO_PINMODE_ANALOG: + stm32f4_mode = LL_GPIO_MODE_ANALOG; + break; + case RTEMS_GPIO_PINMODE_BSP_SPECIFIC: + stm32f4_mode = LL_GPIO_MODE_ALTERNATE; + break; + default: + /* illegal argument */ + return RTEMS_UNSATISFIED; + } + LL_GPIO_SetPinMode(gpio->port, pin_mask, stm32f4_mode); + if (stm32f4_mode == LL_GPIO_MODE_OUTPUT) { + LL_GPIO_SetPinOutputType(gpio->port, pin_mask, stm32f4_output_type); + } + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code stm32f4_gpio_set_pull( + rtems_gpio *base, + rtems_gpio_pull pull +) +{ + stm32f4_gpio *gpio = get_gpio_from_base(base); + uint32_t pin_mask = STM32F4_GET_HAL_GPIO_PIN(gpio->pin); + uint32_t stm32f4_pull; + + switch (pull) { + case RTEMS_GPIO_NOPULL: + stm32f4_pull = LL_GPIO_PULL_NO; + break; + case RTEMS_GPIO_PULLUP: + stm32f4_pull = LL_GPIO_PULL_UP; + break; + case RTEMS_GPIO_PULLDOWN: + stm32f4_pull = LL_GPIO_PULL_DOWN; + break; + default: + /* Illegal argument */ + return RTEMS_UNSATISFIED; + } + LL_GPIO_SetPinPull(gpio->port, pin_mask, stm32f4_pull); + return RTEMS_SUCCESSFUL; +} + +rtems_status_code stm32f4_gpio_configure_interrupt( + rtems_gpio *base, + rtems_gpio_isr isr, + void *arg, + rtems_gpio_interrupt_trig trig, + rtems_gpio_pull pull +) +{ + // configure pin + stm32f4_gpio *gpio = get_gpio_from_base(base); + uint32_t pin_mask = STM32F4_GET_HAL_GPIO_PIN(gpio->pin); + GPIO_InitTypeDef hal_conf; + + switch (trig) { + case RTEMS_GPIO_INT_TRIG_NONE: + return RTEMS_SUCCESSFUL; + case RTEMS_GPIO_INT_TRIG_FALLING: + hal_conf.Mode = GPIO_MODE_IT_FALLING; + break; + case RTEMS_GPIO_INT_TRIG_RISING: + hal_conf.Mode = GPIO_MODE_IT_RISING; + break; + case RTEMS_GPIO_INT_TRIG_BOTH_EDGES: + hal_conf.Mode = GPIO_MODE_IT_RISING_FALLING; + break; + default: + /* Invalid argument */ + return RTEMS_UNSATISFIED; + } + switch (pull) { + case RTEMS_GPIO_NOPULL: + hal_conf.Pull = GPIO_NOPULL; + break; + case RTEMS_GPIO_PULLUP: + hal_conf.Pull = GPIO_PULLUP; + break; + case RTEMS_GPIO_PULLDOWN: + hal_conf.Pull = GPIO_PULLDOWN; + break; + default: + /* Illegal argument */ + return RTEMS_UNSATISFIED; + } + hal_conf.Pin = pin_mask; + HAL_GPIO_Init(gpio->port, &hal_conf); + + // RTEMS interrupt config + isr_table[gpio->pin] = (stm32f4_interrupt){ + .arg = { + .arg = arg, + .gpio = gpio + }, + .isr = isr + }; + rtems_option opt = gpio->pin < 5 ? + RTEMS_INTERRUPT_UNIQUE : + RTEMS_INTERRUPT_SHARED; + rtems_status_code sc = rtems_interrupt_handler_install( + STM32F4_GET_EXTI_IRQn(gpio->pin), + NULL, + opt, + exti_handler, + &isr_table[gpio->pin].arg + ); + + return sc; +} + +rtems_status_code stm32f4_gpio_remove_interrupt( + rtems_gpio *base +) +{ + stm32f4_gpio *gpio = get_gpio_from_base(base); + rtems_status_code sc = rtems_interrupt_handler_remove( + STM32F4_GET_EXTI_IRQn(gpio->pin), + exti_handler, + &isr_table[gpio->pin].arg + ); + if (sc == RTEMS_SUCCESSFUL) { + isr_table[gpio->pin] = (stm32f4_interrupt){0}; + } + return sc; +} + +rtems_status_code stm32f4_gpio_enable_interrupt( + rtems_gpio *base +) +{ + stm32f4_gpio *gpio = get_gpio_from_base(base); + LL_EXTI_EnableIT_0_31(STM32F4_GET_LL_EXTI_LINE(gpio->pin)); + return RTEMS_SUCCESSFUL; +} + +rtems_status_code stm32f4_gpio_disable_interrupt( + rtems_gpio *base +) +{ + stm32f4_gpio *gpio = get_gpio_from_base(base); + LL_EXTI_DisableIT_0_31(STM32F4_GET_LL_EXTI_LINE(gpio->pin)); + return RTEMS_SUCCESSFUL; +} + +rtems_status_code stm32f4_gpio_write( + rtems_gpio *base, + rtems_gpio_pin_state value +) +{ + stm32f4_gpio *gpio = get_gpio_from_base(base); + + if (value) + LL_GPIO_SetOutputPin(gpio->port, STM32F4_GET_HAL_GPIO_PIN(gpio->pin)); + else + LL_GPIO_ResetOutputPin(gpio->port, STM32F4_GET_HAL_GPIO_PIN(gpio->pin)); + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code stm32f4_gpio_read( + rtems_gpio *base, + rtems_gpio_pin_state *value +) +{ + stm32f4_gpio *gpio = get_gpio_from_base(base); + + *value = LL_GPIO_IsInputPinSet( + gpio->port, + STM32F4_GET_HAL_GPIO_PIN(gpio->pin) + ); + return RTEMS_SUCCESSFUL; +} + +rtems_status_code stm32f4_gpio_toggle( + rtems_gpio *base +) +{ + stm32f4_gpio *gpio = get_gpio_from_base(base); + + LL_GPIO_TogglePin( + gpio->port, + STM32F4_GET_HAL_GPIO_PIN(gpio->pin) + ); + return RTEMS_SUCCESSFUL; +} + +void exti_handler(void *arg) { + stm32f4_interrupt_arg *stm32_arg = (stm32f4_interrupt_arg *) arg; + uint32_t pin_mask = STM32F4_GET_HAL_GPIO_PIN(stm32_arg->gpio->pin); + if(__HAL_GPIO_EXTI_GET_IT(pin_mask) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(pin_mask); + (*isr_table[stm32_arg->gpio->pin].isr)(stm32_arg->arg); + } +} + diff --git a/bsps/arm/stm32f4/include/bsp.h b/bsps/arm/stm32f4/include/bsp.h index 42a74e109d..968545cd5a 100644 --- a/bsps/arm/stm32f4/include/bsp.h +++ b/bsps/arm/stm32f4/include/bsp.h @@ -42,10 +42,6 @@ extern "C" { #define BSP_ARMV7M_SYSTICK_FREQUENCY STM32F4_HCLK -#ifdef __rtems__ -void Error_Handler(void); -#endif /* __rtems__ */ - #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h b/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h new file mode 100644 index 0000000000..8f21539709 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2022 Duc Doan <dtbpkmte at gmail.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_BSP_GPIO +#define LIBBSP_ARM_STM32F4_BSP_GPIO + +#include <stdbool.h> +#include <stm32f4xx.h> +#include <stm32f4xx_ll_gpio.h> +#include <stm32f4xx_ll_exti.h> +#include <bsp/gpio2.h> + +/** + * @brief STM32F4 BSP GPIO structure + * + */ +typedef struct { + /** + * @brief This member is a rtems_gpio object. + */ + rtems_gpio base; + /** + *@brief This member is the pin number from 0 to 15. + */ + uint32_t pin; + /** + * @brief This member is HAL GPIOx pointer. + */ + GPIO_TypeDef *port; +} stm32f4_gpio; + +#endif /* LIBBSP_ARM_STM32F4_BSP_GPIO */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4_hal.h b/bsps/arm/stm32f4/include/bsp/stm32f4_hal.h new file mode 100644 index 0000000000..9e88b39067 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4_hal.h @@ -0,0 +1,17 @@ +#ifndef LIBBSP_ARM_STM32F4_BSP_STM32F4HAL_H +#define LIBBSP_ARM_STM32F4_BSP_STM32F4HAL_H + +#include <stm32f4xx_hal.h> + +#ifdef __cplusplus +extern "C" { +#endif + +void stm32f4_clk_enable(); +void stm32f4_clk_disable(); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/arm/stm32f4/start/bspstart.c b/bsps/arm/stm32f4/start/bspstart.c index 8589c6486c..84e8ee7c94 100644 --- a/bsps/arm/stm32f4/start/bspstart.c +++ b/bsps/arm/stm32f4/start/bspstart.c @@ -19,6 +19,7 @@ #endif /* __rtems__ */ #ifdef __rtems__ #include <stm32f4xx.h> +#include <bsp/gpio2.h> #endif /* __rtems__ */ #ifdef STM32F4_FAMILY_F4XXXX @@ -46,7 +47,7 @@ uint32_t HAL_GetTick(void) * @brief This function is executed in case of error occurrence. * @retval None */ -void Error_Handler(void) +static void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ @@ -166,7 +167,6 @@ static rtems_status_code SystemClock_Config(void) HAL_StatusTypeDef status = HAL_RCC_OscConfig(&RCC_OscInitStruct); if (status != HAL_OK) { -// Error_Handler(); return RTEMS_UNSATISFIED; } @@ -181,7 +181,6 @@ static rtems_status_code SystemClock_Config(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency) != HAL_OK) { -// Error_Handler(); return RTEMS_UNSATISFIED; } @@ -465,7 +464,7 @@ void bsp_start( void ) { init_main_osc(); -#ifdef __rtems__ +#ifndef __rtems__ stm32f4_gpio_set_config_array( &stm32f4_start_config_gpio[ 0 ] ); #endif /* __rtems__ */ diff --git a/bsps/arm/stm32f4/start/bspstarthook.c b/bsps/arm/stm32f4/start/bspstarthook.c index bbfaed615e..7f5f85c67a 100644 --- a/bsps/arm/stm32f4/start/bspstarthook.c +++ b/bsps/arm/stm32f4/start/bspstarthook.c @@ -20,4 +20,12 @@ void BSP_START_TEXT_SECTION bsp_start_hook_1(void) bsp_start_clear_bss(); /* At this point we can use objects outside the .start section */ + +#ifdef __rtems__ + +#if STM32F4_ENABLE_GENERIC_GPIO == 1 + bsp_gpio_register_controllers(); +#endif /* STM32F4_ENABLE_GENERIC_GPIO */ + +#endif /* __rtems__ */ } diff --git a/spec/build/bsps/arm/stm32f4/grp.yml b/spec/build/bsps/arm/stm32f4/grp.yml index 99a78e1890..99b3a10527 100644 --- a/spec/build/bsps/arm/stm32f4/grp.yml +++ b/spec/build/bsps/arm/stm32f4/grp.yml @@ -17,9 +17,11 @@ links: - role: build-dependency uid: abi - role: build-dependency - uid: obj + uid: optnumgpioctrl - role: build-dependency uid: optenhal +- role: build-dependency + uid: optengpio - role: build-dependency uid: optvariant - role: build-dependency @@ -66,6 +68,8 @@ links: uid: ../../objirq - role: build-dependency uid: ../../objmem +- role: build-dependency + uid: obj - role: build-dependency uid: ../../bspopts type: build diff --git a/spec/build/bsps/arm/stm32f4/obj.yml b/spec/build/bsps/arm/stm32f4/obj.yml index 7afe000024..172643b700 100644 --- a/spec/build/bsps/arm/stm32f4/obj.yml +++ b/spec/build/bsps/arm/stm32f4/obj.yml @@ -261,6 +261,7 @@ source: - bsps/arm/stm32f4/hal/stm32f4xx_ll_usb.c - bsps/arm/stm32f4/hal/stm32f4xx_ll_utils.c - bsps/arm/stm32f4/hal/system_stm32f4xx.c +- bsps/arm/stm32f4/gpio/gpio.c - bsps/arm/shared/irq/irq-armv7m.c - bsps/arm/shared/irq/irq-dispatch-armv7m.c - bsps/arm/shared/start/bsp-start-memcpy.S diff --git a/spec/build/bsps/arm/stm32f4/optengpio.yml b/spec/build/bsps/arm/stm32f4/optengpio.yml new file mode 100644 index 0000000000..8b15bce9a9 --- /dev/null +++ b/spec/build/bsps/arm/stm32f4/optengpio.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com) +default: true +default-by-variant: [] +description: | + This option enables the BSP to use RTEMS GPIO API. +enabled-by: true +format: '{}' +links: [] +name: STM32F4_ENABLE_GENERIC_GPIO +type: build diff --git a/spec/build/bsps/arm/stm32f4/optnumgpioctrl.yml b/spec/build/bsps/arm/stm32f4/optnumgpioctrl.yml new file mode 100644 index 0000000000..da21d9c62c --- /dev/null +++ b/spec/build/bsps/arm/stm32f4/optnumgpioctrl.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com) +default: 1 +default-by-variant: [] +description: | + Number of GPIO controllers of this BSP. +enabled-by: true +format: '{}' +links: [] +name: BSP_GPIO_NUM_CONTROLLERS +type: build -- 2.36.1 _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel