Re: [PATCH v1 7/7] spec/aarch64: Force strict alignment for ZynqMP

2021-03-08 Thread Chris Johns
On 9/3/21 1:24 pm, Kinsey Moore wrote: > I was working under the impression that I didn't need it since RTEMS uses a > flat > memory model. I'll be spending some time tomorrow seeing what it will take to > enable usage of the "normal" memory model via a configured MMU. Most architectures with

RE: [PATCH v1 7/7] spec/aarch64: Force strict alignment for ZynqMP

2021-03-08 Thread Kinsey Moore
day, March 8, 2021 20:08 To: Kinsey Moore Cc: devel@rtems.org Subject: Re: [PATCH v1 7/7] spec/aarch64: Force strict alignment for ZynqMP On 9/3/21 10:40 am, Kinsey Moore wrote: > So after a little more diving into this, I have found why --strict-align is > required. > If the MMU is d

Re: [PATCH v1 7/7] spec/aarch64: Force strict alignment for ZynqMP

2021-03-08 Thread Chris Johns
On 9/3/21 10:40 am, Kinsey Moore wrote: > So after a little more diving into this, I have found why --strict-align is > required. > If the MMU is disabled, all memory is treated as device memory which requires > strictly aligned accesses. I think I have missed something or not understanding the

RE: [PATCH v1 7/7] spec/aarch64: Force strict alignment for ZynqMP

2021-03-08 Thread Kinsey Moore
:12 To: Sebastian Huber ; devel@rtems.org Subject: RE: [PATCH v1 7/7] spec/aarch64: Force strict alignment for ZynqMP Hi Sebastian, For AArch64, that would be SCTLR_EL1.A (bit 1). Even with that alignment checking disabled, I still see data aborts on misaligned accesses. The MMU is disabled during

RE: [PATCH v1 7/7] spec/aarch64: Force strict alignment for ZynqMP

2021-03-05 Thread Kinsey Moore
- From: Sebastian Huber Sent: Thursday, March 4, 2021 23:54 To: Kinsey Moore ; devel@rtems.org Subject: Re: [PATCH v1 7/7] spec/aarch64: Force strict alignment for ZynqMP On 04/03/2021 23:15, Kinsey Moore wrote: > Real hardware running AArch64 does not appreciate accesses misalig

Re: [PATCH v1 7/7] spec/aarch64: Force strict alignment for ZynqMP

2021-03-04 Thread Sebastian Huber
On 04/03/2021 23:15, Kinsey Moore wrote: Real hardware running AArch64 does not appreciate accesses misaligned relative to the data size. This prevents generation of misaligned writes which would throw exceptions. The patch set is fine independent of the following comment. To me this problem