Re: [PATCH 1/3] Docs: RISC-V Update rv64* BSPs to medany and 0x80000000 start address

On 05/01/2023 18:04, Hesham Almatary wrote: Ping (as this was sent over holidays). Looks good. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht:

Re: [PATCH 1/3] Docs: RISC-V Update rv64* BSPs to medany and 0x80000000 start address

Ping (as this was sent over holidays). On Fri, 23 Dec 2022 at 09:48, wrote: > > From: Hesham Almatary > > Closes #4775 > --- > user/bsps/bsps-riscv.rst | 27 --- > 1 file changed, 12 insertions(+), 15 deletions(-) > > diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsp

[PATCH 1/3] Docs: RISC-V Update rv64* BSPs to medany and 0x80000000 start address

From: Hesham Almatary Closes #4775 --- user/bsps/bsps-riscv.rst | 27 --- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst index 2ef8327..5269462 100644 --- a/user/bsps/bsps-riscv.rst +++ b/user/bsps/bsps-

[PATCH 3/3] RISC-V: Update docs on running on QEMU and Spike

From: Hesham Almatary --- user/bsps/bsps-riscv.rst | 26 +++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst index 28682f6..6604d1f 100644 --- a/user/bsps/bsps-riscv.rst +++ b/user/bsps/bsps-riscv.rst @@ -1

[PATCH] Docs: RISC-V Update BSPs to medany and 0x80000000 start address

From: Hesham Almatary Closes #4775 --- user/bsps/bsps-riscv.rst | 24 +--- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst index 2ef8327..c9813e5 100644 --- a/user/bsps/bsps-riscv.rst +++ b/user/bsps/bsps-risc

RISC-V Update (3)

Hello, I am now done with my work to add SMP support to the RISC-V port. The RISC-V port is on par with the ARM, PowerPC and SPARC ports. A big thanks to Hesham for the ground work from my side. In the driver area there is a lot to do. The device tree support in RTEMS is quite poor and more

Re: RISC-V Update (2)

On 25/07/18 12:21, Sebastian Huber wrote: To run the BSP on Qemu some patches are necessary: https://github.com/riscv/riscv-qemu/pull/155 I got a very detailed feedback to my patches. The patches are wrong/unnecessary. I fixed the RTEMS port accordingly. Now, the BSP runs with a Qemu of this

Re: RISC-V Update (2)

Hi Sebastian, Great work! thanks for the update. Best, Hesham On Wed, Jul 25, 2018 at 11:21 AM, Sebastian Huber wrote: > Hello, > > I checked in a couple of patches today aiming to improve the RISC-V support. > The Platform-Level Interrupt Controller (PLIC) and inter-processor > interrupts are

Re: RISC-V Update (2)

On 25/07/18 12:21, Sebastian Huber wrote: https://lists.rtems.org/pipermail/build/2018-July/000771.html Sorry, wrong link: https://lists.rtems.org/pipermail/build/2018-July/000896.html -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 8

RISC-V Update (2)

Hello, I checked in a couple of patches today aiming to improve the RISC-V support. The Platform-Level Interrupt Controller (PLIC) and inter-processor interrupts are now supported. To run the BSP on Qemu some patches are necessary: https://github.com/riscv/riscv-qemu/pull/155 There is a gen

RISC-V update

Hello, I checked in a couple of patches today aiming to improve the RISC-V support. I was able to run the test suite on Qemu with some success: https://lists.rtems.org/pipermail/build/2018-June/000768.html The next step is to get it running on the Qemu "virt" machine with more than one proce