Great news on the Pi 2 cache configuration!
I am looking forward to a patch to try.
Alan
On Sun, Jun 21, 2015 at 3:27 PM, Rohini Kulkarni krohini1...@gmail.com
wrote:
:)
There is very little code that had to be added.
I need to clean the code and add conditional call for Pi 2. Then I would
Hello,
Are these the relevant functions from
~/rtems/cpukit/score/cpu/arm/rtems/score/cpu.h?
_CPU_SMP_Get_current_processor()
_CPU_SMP_Send_interrupt()
_CPU_SMP_Processor_event_broadcast()
_CPU_SMP_Processor_event_receive()
I am unable to understand how
On Sun, Jun 21, 2015 at 3:04 PM, Rohini Kulkarni krohini1...@gmail.com wrote:
I missed mentioning the number of dhrystones in the previous mail.
Originally it was 1 million.
The new number of dhrystones I executed is 100 million.
The next thing to do is to figure out what changes are
Hi all,
I have managed to get a significant performance improvement with some
changes in configurations.
The measured time was for dhrystones reduced from 12 to too small to be
measured
For dhrystones the time was 0.4.
The number of dhrystones per second increased from approximately 8 to
:)
There is very little code that had to be added.
I need to clean the code and add conditional call for Pi 2. Then I would be
ready to submit a patch.
On 22 Jun 2015 00:52, Gedare Bloom ged...@gwu.edu wrote:
On Sun, Jun 21, 2015 at 3:04 PM, Rohini Kulkarni krohini1...@gmail.com
wrote:
I
I missed mentioning the number of dhrystones in the previous mail.
Originally it was 1 million.
The new number of dhrystones I executed is 100 million.
On Mon, Jun 22, 2015 at 12:29 AM, Rohini Kulkarni krohini1...@gmail.com
wrote:
Hi all,
I have managed to get a significant performance
Hello Rohini,
the CPU functions relevant for SMP are documented in the no_cpu/cpu.h file.
- Am 20. Jun 2015 um 22:02 schrieb Rohini Kulkarni krohini1...@gmail.com:
Hi,
I have added an SMP related post to my blog to define where exactly in the
code
I need to work. Some feedback to
Hi,
I have added an SMP related post to my blog to define where exactly in the
code I need to work. Some feedback to indicate if I am identifying the work
area correctly would be very helpful!
Thanks!
On 18 Jun 2015 03:37, Rohini Kulkarni krohini1...@gmail.com wrote:
Hi all,
I have updated
Hi all,
I have updated my blog to reflect my understanding and attempts for cache
performance issue.
Lately I have been trying around memory attributes for the mm_config_table.
One set of configurations for cacheable memory (inner and outer
levels)ended up reducing performance further ( which I
Hi,
Some of the code examples may give you some clues. Like this one:
https://github.com/mrvn/test/blob/master/smp.cc
Or this:
https://github.com/PeterLemon/RaspberryPi/tree/master/SMP/SMPINIT
If you still can't figure it out, you can always join the raspberrypi.org
forums and ask on this
But, I can't say cache configurations have a role here.
I'll push my code to my github project soon.
P.S. The Pi2 board I possess seems to have broken down. It just isn't
turning on. Unable to test further. Will order one immediately.
On 3 Jun 2015 09:03, Rohini Kulkarni krohini1...@gmail.com
On Wed, Jun 3, 2015 at 2:39 AM, Rohini Kulkarni krohini1...@gmail.com wrote:
But, I can't say cache configurations have a role here.
I'll push my code to my github project soon.
P.S. The Pi2 board I possess seems to have broken down. It just isn't
turning on. Unable to test further. Will
On Tue, Jun 2, 2015 at 9:42 PM, Alan Cudmore alan.cudm...@gmail.com wrote:
The caches are being enabled on the RPI 1 BSP. The same code is being
executed by the RPI 2 BSP, but obviously it’s not sufficient for the cache
setup.
I have been reading through this long thread, and it is very
Hi,
Alan, your suggestion has resulted in much improvement
arm_control=0x1000
This has simply worked! Looks like the other cores were taking up plenty of
time.
I was aware from references that the other cores run a WFI, but ya, did not
get its impact.
Time for each dhrystone has reduced to 7
From what I saw, they have to be enabled separately. Cache/mmu are disabled
upon reset.
On 2 Jun 2015 16:59, Hesham ALMatary heshamelmat...@gmail.com wrote:
Hi,
Aren't the MMU/Caches enabled by default for RPi [1]?
[1]
On June 2, 2015 7:29:52 AM EDT, Hesham ALMatary heshamelmat...@gmail.com
wrote:
Hi,
Aren't the MMU/Caches enabled by default for RPi [1]?
Yes but I recall that the setup is different on the Pi2 and Alan disabled the
code to to work at all.
[1]
HI,
I tried running the dhrystone benchmark with some changes for cache/mmu set
up.
However, the output shows a reduction in performance.
The time to run through the dhrystone has increased from 12 to 13 and
dhrystones run per second decreased.
According to this result, things were better with
On Tue, Jun 2, 2015 at 12:41 PM, Rohini Kulkarni krohini1...@gmail.com wrote:
From what I saw, they have to be enabled separately. Cache/mmu are disabled
upon reset.
For the existing Raspberry BSP [1] there's a code for MMU/Cache init,
however I don't know about Pi2 and where its code is.
[1]
On June 2, 2015 5:58:33 AM EDT, Rohini Kulkarni krohini1...@gmail.com wrote:
HI,
I tried running the dhrystone benchmark with some changes for cache/mmu
set up.
However, the output shows a reduction in performance.
The time to run through the dhrystone has increased from 12 to 13 and
On Thu, May 28, 2015 at 10:11 AM, Rohini Kulkarni krohini1...@gmail.com wrote:
Hi All,
I have to implement the cache coherency support for Cortex A7. But for A7
MPCore, unlike for A9, I am not able to find any register description for
the Snoop Control Unit from the TRM.
I need help here on
Hi All,
I have to implement the cache coherency support for Cortex A7. But for A7
MPCore, unlike for A9, I am not able to find any register description for
the Snoop Control Unit from the TRM.
I need help here on how to proceed.
Additionally for A9 there is a single bit for A9 in the Auxiliary
On 5/5/2015 11:11 AM, Rohini Kulkarni wrote:
Hi,
I am working with the code for bsp hooks. I am referring to existing
ARM multicore bsp codes, zync mainly.
1. There are existing hooks for the raspberry pi. Where should the
code for the Pi2 hooks be added?
The Pi and Pi2 are remarkably
On Fri, May 1, 2015 at 3:15 AM, Rohini Kulkarni krohini1...@gmail.com wrote:
Hi,
Excited to be a part of this edition of GSoC! Thanks to everybody for
helping me get here and congratulations to all the participating students!
So, now getting to work, firstly I wish to know, specifically
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