Hello Deval,
On Thursday 02 of June 2016 10:49:34 Deval Shah wrote:
> Hello Pavel,
>
> I would like to work on this problem. Can I get some more details and some
> literature to go through ?
it would be great. I think that I have complete knowledge to
do that in somethink like one or two days but when I have
time is in the sky. So there is my short info from my git
#
# modified: hw/arm/bcm2835_peripherals.c
# modified: hw/timer/Makefile.objs
#
# Untracked files:
# (use "git add <file>..." to include in what will be committed)
#
# hw/timer/bcm2835_timer.c
# include/hw/timer/bcm2835_timer.h
The bcm2835 is significantly modified ARM PrimeCell SP804.
QEMU support for this HW is in file hw/timer/arm_timer.c .
In the long term integration to that source with some
extension to represent these BCM specifics.
But I expect that it is much easier to start with separate
bcm2835_timer.c and not ask maintainer to accept significant
changes to the code that has to be stable for many other targets.
I am attaching hw/timer/arm_timer.c changed to rough skeleton
of hw/timer/bcm2835_timer.c. Not in shape, but I do not get
to continue in next two or more weeks. So you can look at it
New peripheral has to be included
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -97,6 +97,9 @@ static void bcm2835_peripherals_init(Object *obj)
object_property_add_const_link(OBJECT(&s->dma), "dma-mr",
OBJECT(&s->gpu_bus_mr), &error_abort);
+
+ sysbus_create_simple("sp804", 0x10011000, pic[4]);
+
}
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
But sysbus_create_simple is how sp804 is included in other boards.
I think that BCM used style for other for BCM peripherals integration
should be used.
Best wishes,
Pavel
> On Fri, May 27, 2016 at 1:59 AM, Pavel Pisa <ppisa4li...@pikron.com> wrote:
> > Hello all,
> >
> > it seems that Raspberry Pi QEMU emulation cannot work
> > with current RTEMS BSP because it uses BCM2835_TIMER_
> >
> > as the main clock source, see
> >
> > rtems/c/src/lib/libbsp/arm/raspberrypi/clock/clockdrv.c
> >
> > which is mapped to
> >
> > #define RPI_PERIPHERAL_BASE 0x3F000000
> > #define BCM2835_TIMER_BASE (RPI_PERIPHERAL_BASE + 0xB400)
> >
> > but when I invoke "info mtree" in QEMU monitor console,
> > it reports
> >
> > address-space: memory
> > 0000000000000000-ffffffffffffffff (prio 0, RW): system
> > 0000000000000000-000000003fffffff (prio 0, RW): ram
> > 000000003f000000-000000003fffffff (prio 1, RW): bcm2835-peripherals
> > 000000003f007000-000000003f007fff (prio 0, RW): bcm2835-dma
> > 000000003f00b200-000000003f00b3ff (prio 0, RW): bcm2835-ic
> > 000000003f00b800-000000003f00bbff (prio 0, RW): bcm2835-mbox
> > 000000003f201000-000000003f201fff (prio 0, RW): pl011
> > 000000003f215000-000000003f2150ff (prio 0, RW): bcm2835-aux
> > 000000003f300000-000000003f3000ff (prio 0, RW): sdhci
> > 000000003fe05000-000000003fe050ff (prio 0, RW): bcm2835-dma-chan15
> > 0000000040000000-00000000400000ff (prio 0, RW): bcm2836-control
> >
> > which means that area 000000003f00b400-000000003f00b7ff is unmapped.
> > Linux and Windows use local Cortex-A CPU timers most probably on RPi2,
> > so actual RTEMS BSP is not compatible with QEMU RPi2 support.
> >
> > It is not so hared to extend RPi2 QEMU support but it requires
> > time.
> >
> > Best wishes,
> >
> > Pavel
> > _______________________________________________
> > devel mailing list
> > devel@rtems.org
> > http://lists.rtems.org/mailman/listinfo/devel
/*
* BCM2835 Timer modules
*
* Hardware is based on ARM PrimeCell SP804 but with
* significant modifications so arm_timer.c is not used there
*
* Based on code by
* Copyright (c) 2005-2006 CodeSourcery.
* Written by Paul Brook
*
* BCM2835 specific code by Pavel Pisa 2016
*
* This code is licensed under the GPL.
*/
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "qemu/bcm2835_timer.h"
#include "qemu-common.h"
#include "hw/qdev.h"
#include "hw/ptimer.h"
#include "qemu/main-loop.h"
/* Common timer implementation. */
#define TIMER_CTRL_ONESHOT (1 << 0)
#define TIMER_CTRL_32BIT (1 << 1)
#define TIMER_CTRL_DIV1 (0 << 2)
#define TIMER_CTRL_DIV16 (1 << 2)
#define TIMER_CTRL_DIV256 (2 << 2)
#define TIMER_CTRL_IE (1 << 5)
#define TIMER_CTRL_PERIODIC (1 << 6)
#define TIMER_CTRL_ENABLE (1 << 7)
typedef struct {
ptimer_state *timer;
uint32_t control;
uint32_t limit;
int freq;
int int_level;
qemu_irq irq;
} bcm2835_timer_state;
/* Check all active timers, and schedule the next timer interrupt. */
static void bcm2835_timer_update(bcm2835_timer_state *s)
{
/* Update interrupts. */
if (s->int_level && (s->control & TIMER_CTRL_IE)) {
qemu_irq_raise(s->irq);
} else {
qemu_irq_lower(s->irq);
}
}
static uint32_t bcm2835_timer_read(void *opaque, hwaddr offset)
{
bcm2835_timer_state *s = (bcm2835_timer_state *)opaque;
switch (offset >> 2) {
case 0: /* TimerLoad */
case 6: /* TimerBGLoad */
return s->limit;
case 1: /* TimerValue */
return ptimer_get_count(s->timer);
case 2: /* TimerControl */
return s->control;
case 4: /* TimerRIS */
return s->int_level;
case 5: /* TimerMIS */
if ((s->control & TIMER_CTRL_IE) == 0)
return 0;
return s->int_level;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset %x\n", __func__, (int)offset);
return 0;
}
}
/* Reset the timer limit after settings have changed. */
static void bcm2835_timer_recalibrate(bcm2835_timer_state *s, int reload)
{
uint32_t limit;
if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) {
/* Free running. */
if (s->control & TIMER_CTRL_32BIT)
limit = 0xffffffff;
else
limit = 0xffff;
} else {
/* Periodic. */
limit = s->limit;
}
ptimer_set_limit(s->timer, limit, reload);
}
static void bcm2835_timer_write(void *opaque, hwaddr offset,
uint32_t value)
{
bcm2835_timer_state *s = (bcm2835_timer_state *)opaque;
int freq;
switch (offset >> 2) {
case 0: /* TimerLoad */
s->limit = value;
bcm2835_timer_recalibrate(s, 1);
break;
case 1: /* TimerValue */
/* ??? Linux seems to want to write to this readonly register.
Ignore it. */
break;
case 2: /* TimerControl */
if (s->control & TIMER_CTRL_ENABLE) {
/* Pause the timer if it is running. This may cause some
inaccuracy dure to rounding, but avoids a whole lot of other
messyness. */
ptimer_stop(s->timer);
}
s->control = value;
freq = s->freq;
/* ??? Need to recalculate expiry time after changing divisor. */
switch ((value >> 2) & 3) {
case 1: freq >>= 4; break;
case 2: freq >>= 8; break;
}
bcm2835_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
ptimer_set_freq(s->timer, freq);
if (s->control & TIMER_CTRL_ENABLE) {
/* Restart the timer if still enabled. */
ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
}
break;
case 3: /* TimerIntClr */
s->int_level = 0;
break;
case 6: /* TimerBGLoad */
s->limit = value;
bcm2835_timer_recalibrate(s, 0);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset %x\n", __func__, (int)offset);
}
bcm2835_timer_update(s);
}
static void bcm2835_timer_tick(void *opaque)
{
bcm2835_timer_state *s = (bcm2835_timer_state *)opaque;
s->int_level = 1;
bcm2835_timer_update(s);
}
static const VMStateDescription vmstate_bcm2835_timer = {
.name = "bcm2835_timer",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(control, bcm2835_timer_state),
VMSTATE_UINT32(limit, bcm2835_timer_state),
VMSTATE_INT32(int_level, bcm2835_timer_state),
VMSTATE_PTIMER(timer, bcm2835_timer_state),
VMSTATE_END_OF_LIST()
}
};
static bcm2835_timer_state *bcm2835_timer_init(uint32_t freq)
{
bcm2835_timer_state *s;
QEMUBH *bh;
s = (bcm2835_timer_state *)g_malloc0(sizeof(bcm2835_timer_state));
s->freq = freq;
s->control = TIMER_CTRL_IE;
bh = qemu_bh_new(bcm2835_timer_tick, s);
s->timer = ptimer_init(bh);
vmstate_register(NULL, -1, &vmstate_bcm2835_timer, s);
return s;
}
/* ARM PrimeCell SP804 dual timer module.
* Docs at
* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html
*/
#define TYPE_SP804 "sp804"
#define SP804(obj) OBJECT_CHECK(SP804State, (obj), TYPE_SP804)
typedef struct SP804State {
SysBusDevice parent_obj;
MemoryRegion iomem;
bcm2835_timer_state *timer[2];
uint32_t freq0, freq1;
int level[2];
qemu_irq irq;
} SP804State;
static const uint8_t sp804_ids[] = {
/* Timer ID */
0x04, 0x18, 0x14, 0,
/* PrimeCell ID */
0xd, 0xf0, 0x05, 0xb1
};
/* Merge the IRQs from the two component devices. */
static void sp804_set_irq(void *opaque, int irq, int level)
{
SP804State *s = (SP804State *)opaque;
s->level[irq] = level;
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}
static uint64_t sp804_read(void *opaque, hwaddr offset,
unsigned size)
{
SP804State *s = (SP804State *)opaque;
if (offset < 0x20) {
return bcm2835_timer_read(s->timer[0], offset);
}
if (offset < 0x40) {
return bcm2835_timer_read(s->timer[1], offset - 0x20);
}
/* TimerPeriphID */
if (offset >= 0xfe0 && offset <= 0xffc) {
return sp804_ids[(offset - 0xfe0) >> 2];
}
switch (offset) {
/* Integration Test control registers, which we won't support */
case 0xf00: /* TimerITCR */
case 0xf04: /* TimerITOP (strictly write only but..) */
qemu_log_mask(LOG_UNIMP,
"%s: integration test registers unimplemented\n",
__func__);
return 0;
}
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset %x\n", __func__, (int)offset);
return 0;
}
static void sp804_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
SP804State *s = (SP804State *)opaque;
if (offset < 0x20) {
bcm2835_timer_write(s->timer[0], offset, value);
return;
}
if (offset < 0x40) {
bcm2835_timer_write(s->timer[1], offset - 0x20, value);
return;
}
/* Technically we could be writing to the Test Registers, but not likely */
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n",
__func__, (int)offset);
}
static const MemoryRegionOps sp804_ops = {
.read = sp804_read,
.write = sp804_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_sp804 = {
.name = "sp804",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_INT32_ARRAY(level, SP804State, 2),
VMSTATE_END_OF_LIST()
}
};
static void sp804_init(Object *obj)
{
SP804State *s = SP804(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
sysbus_init_irq(sbd, &s->irq);
memory_region_init_io(&s->iomem, obj, &sp804_ops, s,
"sp804", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
}
static void sp804_realize(DeviceState *dev, Error **errp)
{
SP804State *s = SP804(dev);
s->timer[0] = bcm2835_timer_init(s->freq0);
s->timer[1] = bcm2835_timer_init(s->freq1);
s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0);
s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1);
}
static Property sp804_properties[] = {
DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000),
DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000),
DEFINE_PROP_END_OF_LIST(),
};
static void sp804_class_init(ObjectClass *klass, void *data)
{
DeviceClass *k = DEVICE_CLASS(klass);
k->realize = sp804_realize;
k->props = sp804_properties;
k->vmsd = &vmstate_sp804;
}
static const TypeInfo sp804_info = {
.name = TYPE_SP804,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SP804State),
.instance_init = sp804_init,
.class_init = sp804_class_init,
};
static void bcm2835_timer_register_types(void)
{
type_register_static(&sp804_info);
}
type_init(bcm2835_timer_register_types)
/*
* Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
* Written by Andrew Baumann
*
* This code is licensed under the GNU GPLv2 and later.
*/
#ifndef BCM2835_TIMER_H
#define BCM2835_TIMER_H
#include "hw/sysbus.h"
#include "sysemu/char.h"
#define TYPE_BCM2835_TIMER "bcm2835-timer"
#define BCM2835_TIMER(obj) OBJECT_CHECK(BCM2835TimerState, (obj), TYPE_BCM2835_TIMER)
typedef struct {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
CharDriverState *chr;
qemu_irq irq;
} BCM2835TimerState;
#endif
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