Re: [PATCH] Add support for OpenRISC architecture.
On Mon, Aug 11, 2014 at 8:33 PM, Joel Sherrill
joel.sherr...@oarcorp.com wrote:
On 8/11/2014 1:16 PM, Gedare Bloom wrote:
On Mon, Aug 11, 2014 at 8:03 AM, Hesham ALMatary
heshamelmat...@gmail.com wrote:
This work is based on the old or32 port (that has been removed back in 2005)
authored by Chris Ziomkowski. The patch includes the basic functions every
port should implement like: context switch, exception handling,
OpenRISC ABI and machine definitions and configurations.
---
cpukit/configure.ac|1 +
cpukit/score/cpu/Makefile.am |1 +
cpukit/score/cpu/or1k/Makefile.am | 36 +
cpukit/score/cpu/or1k/asm.h| 104 ++
cpukit/score/cpu/or1k/cpu.c| 120 +++
cpukit/score/cpu/or1k/or1k-context-initialize.c| 43 +
cpukit/score/cpu/or1k/or1k-context-switch.S| 115 +++
cpukit/score/cpu/or1k/or1k-exception-default.c | 24 +
cpukit/score/cpu/or1k/or1k-exception-frame-print.c | 22 +
cpukit/score/cpu/or1k/or1k-exception-handler-low.S | 285 ++
cpukit/score/cpu/or1k/rtems/asm.h | 99 ++
cpukit/score/cpu/or1k/rtems/score/cpu.h| 1049
cpukit/score/cpu/or1k/rtems/score/cpu_asm.h| 74 ++
cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 334 +++
cpukit/score/cpu/or1k/rtems/score/or1k.h | 49 +
cpukit/score/cpu/or1k/rtems/score/types.h | 51 +
16 files changed, 2407 insertions(+)
create mode 100644 cpukit/score/cpu/or1k/Makefile.am
create mode 100644 cpukit/score/cpu/or1k/asm.h
create mode 100644 cpukit/score/cpu/or1k/cpu.c
create mode 100644 cpukit/score/cpu/or1k/or1k-context-initialize.c
create mode 100644 cpukit/score/cpu/or1k/or1k-context-switch.S
create mode 100644 cpukit/score/cpu/or1k/or1k-exception-default.c
create mode 100644 cpukit/score/cpu/or1k/or1k-exception-frame-print.c
create mode 100644 cpukit/score/cpu/or1k/or1k-exception-handler-low.S
create mode 100644 cpukit/score/cpu/or1k/rtems/asm.h
You have two of these asm.h files. You should only have this one.
create mode 100644 cpukit/score/cpu/or1k/rtems/score/cpu.h
create mode 100644 cpukit/score/cpu/or1k/rtems/score/cpu_asm.h
create mode 100644 cpukit/score/cpu/or1k/rtems/score/or1k-utility.h
create mode 100644 cpukit/score/cpu/or1k/rtems/score/or1k.h
create mode 100644 cpukit/score/cpu/or1k/rtems/score/types.h
[...]
diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c
new file mode 100644
index 000..05e4cd9
--- /dev/null
+++ b/cpukit/score/cpu/or1k/cpu.c
@@ -0,0 +1,120 @@
+/*
+ * Opencore OR1K CPU Dependent Source
+ *
+ * COPYRIGHT (c) 2014 Hesham ALMatary heshamelmat...@gmail.com
+ * COPYRIGHT (c) 1989-1999.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ */
+
+#include rtems/system.h
+#include rtems/score/isr.h
+#include rtems/score/wkspace.h
+#include bsp/linker-symbols.h
+
+/**
+ * @brief Performs processor dependent initialization.
+ */
+void _CPU_Initialize(void)
+{
+ /* Do nothing */
+}
+
+/**
+ * @brief Sets the hardware interrupt level by the level value.
+ *
+ * @param[in] level for or1k can only range over two values:
+ * 0 (enable interrupts) and 1 (disable interrupts). In future
+ * implementations if fast context switch is implemented, the level
+ * can range from 0 to 15. @see OpenRISC architecture manual.
+ *
+ */
+inline void _CPU_ISR_Set_level(uint32_t level)
+{
+ uint32_t sr = 0;
+ level = (level 0)? 1 : 0;
+
+ /* map level bit to or1k interrupt enable/disable bit in sr register */
+ level = CPU_OR1K_SPR_SR_SHAMT_IEE;
+
+ sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
+
+ if (level == 0) /* Enable all interrupts */
+ {
+sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
+ }
+ else
+ {
+sr = CPU_OR1K_ISR_STATUS_MASK_I_DIS;
+ }
Put braces on same line as if/else, e.g.:
if ( level == 0 ) {
...
} else {
...
}
+
+ _OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
+ }
+
+uint32_t _CPU_ISR_Get_level( void )
+{
+ uint32_t sr = 0;
+
+ sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
+
+ return (sr CPU_OR1K_SPR_SR_IEE)? 0 : 1;
+}
+
Why aren't these static inlines?
+void _CPU_ISR_install_raw_handler(
+ uint32_t vector,
+ proc_ptrnew_handler,
+ proc_ptr *old_handler
+)
+{
+
+}
+
+void _CPU_ISR_install_vector(
+ uint32_tvector,
+ proc_ptrnew_handler,
+ proc_ptr *old_handler
+)
+{
+ volatile proc_ptr *table =
+ (proc_ptr *) bsp_start_vector_table_begin;
Why is this volatile?
Likely history.
+ proc_ptr current_handler;
+
+ ISR_Level level;
+
+ _ISR_Disable( level );
+
+ current_handler = table [vector];
+
+ /* The current
Re: [PATCH] Add support for OpenRISC architecture.
On Mon, Aug 11, 2014 at 8:16 PM, Gedare Bloom ged...@rtems.org wrote:
On Mon, Aug 11, 2014 at 8:03 AM, Hesham ALMatary
heshamelmat...@gmail.com wrote:
This work is based on the old or32 port (that has been removed back in 2005)
authored by Chris Ziomkowski. The patch includes the basic functions every
port should implement like: context switch, exception handling,
OpenRISC ABI and machine definitions and configurations.
---
cpukit/configure.ac|1 +
cpukit/score/cpu/Makefile.am |1 +
cpukit/score/cpu/or1k/Makefile.am | 36 +
cpukit/score/cpu/or1k/asm.h| 104 ++
cpukit/score/cpu/or1k/cpu.c| 120 +++
cpukit/score/cpu/or1k/or1k-context-initialize.c| 43 +
cpukit/score/cpu/or1k/or1k-context-switch.S| 115 +++
cpukit/score/cpu/or1k/or1k-exception-default.c | 24 +
cpukit/score/cpu/or1k/or1k-exception-frame-print.c | 22 +
cpukit/score/cpu/or1k/or1k-exception-handler-low.S | 285 ++
cpukit/score/cpu/or1k/rtems/asm.h | 99 ++
cpukit/score/cpu/or1k/rtems/score/cpu.h| 1049
cpukit/score/cpu/or1k/rtems/score/cpu_asm.h| 74 ++
cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 334 +++
cpukit/score/cpu/or1k/rtems/score/or1k.h | 49 +
cpukit/score/cpu/or1k/rtems/score/types.h | 51 +
16 files changed, 2407 insertions(+)
create mode 100644 cpukit/score/cpu/or1k/Makefile.am
create mode 100644 cpukit/score/cpu/or1k/asm.h
create mode 100644 cpukit/score/cpu/or1k/cpu.c
create mode 100644 cpukit/score/cpu/or1k/or1k-context-initialize.c
create mode 100644 cpukit/score/cpu/or1k/or1k-context-switch.S
create mode 100644 cpukit/score/cpu/or1k/or1k-exception-default.c
create mode 100644 cpukit/score/cpu/or1k/or1k-exception-frame-print.c
create mode 100644 cpukit/score/cpu/or1k/or1k-exception-handler-low.S
create mode 100644 cpukit/score/cpu/or1k/rtems/asm.h
You have two of these asm.h files. You should only have this one.
create mode 100644 cpukit/score/cpu/or1k/rtems/score/cpu.h
create mode 100644 cpukit/score/cpu/or1k/rtems/score/cpu_asm.h
create mode 100644 cpukit/score/cpu/or1k/rtems/score/or1k-utility.h
create mode 100644 cpukit/score/cpu/or1k/rtems/score/or1k.h
create mode 100644 cpukit/score/cpu/or1k/rtems/score/types.h
[...]
diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c
new file mode 100644
index 000..05e4cd9
--- /dev/null
+++ b/cpukit/score/cpu/or1k/cpu.c
@@ -0,0 +1,120 @@
+/*
+ * Opencore OR1K CPU Dependent Source
+ *
+ * COPYRIGHT (c) 2014 Hesham ALMatary heshamelmat...@gmail.com
+ * COPYRIGHT (c) 1989-1999.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ */
+
+#include rtems/system.h
+#include rtems/score/isr.h
+#include rtems/score/wkspace.h
+#include bsp/linker-symbols.h
+
+/**
+ * @brief Performs processor dependent initialization.
+ */
+void _CPU_Initialize(void)
+{
+ /* Do nothing */
+}
+
+/**
+ * @brief Sets the hardware interrupt level by the level value.
+ *
+ * @param[in] level for or1k can only range over two values:
+ * 0 (enable interrupts) and 1 (disable interrupts). In future
+ * implementations if fast context switch is implemented, the level
+ * can range from 0 to 15. @see OpenRISC architecture manual.
+ *
+ */
+inline void _CPU_ISR_Set_level(uint32_t level)
+{
+ uint32_t sr = 0;
+ level = (level 0)? 1 : 0;
+
+ /* map level bit to or1k interrupt enable/disable bit in sr register */
+ level = CPU_OR1K_SPR_SR_SHAMT_IEE;
+
+ sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
+
+ if (level == 0) /* Enable all interrupts */
+ {
+sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
+ }
+ else
+ {
+sr = CPU_OR1K_ISR_STATUS_MASK_I_DIS;
+ }
Put braces on same line as if/else, e.g.:
if ( level == 0 ) {
...
} else {
...
}
+
+ _OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
+ }
+
+uint32_t _CPU_ISR_Get_level( void )
+{
+ uint32_t sr = 0;
+
+ sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
+
+ return (sr CPU_OR1K_SPR_SR_IEE)? 0 : 1;
+}
+
+void _CPU_ISR_install_raw_handler(
+ uint32_t vector,
+ proc_ptrnew_handler,
+ proc_ptr *old_handler
+)
+{
+
+}
+
+void _CPU_ISR_install_vector(
+ uint32_tvector,
+ proc_ptrnew_handler,
+ proc_ptr *old_handler
+)
+{
+ volatile proc_ptr *table =
+ (proc_ptr *) bsp_start_vector_table_begin;
Why is this volatile?
+ proc_ptr current_handler;
+
+ ISR_Level level;
+
+ _ISR_Disable( level );
+
+ current_handler = table [vector];
+
+ /* The current handler is now the old one */
+ if (old_handler != NULL) {
+*old_handler = (proc_ptr) current_handler;
Re: [PATCH] Add support for OpenRISC architecture.
On Mon, Aug 11, 2014 at 8:33 PM, Joel Sherrill
joel.sherr...@oarcorp.com wrote:
On 8/11/2014 1:16 PM, Gedare Bloom wrote:
On Mon, Aug 11, 2014 at 8:03 AM, Hesham ALMatary
heshamelmat...@gmail.com wrote:
This work is based on the old or32 port (that has been removed back in 2005)
authored by Chris Ziomkowski. The patch includes the basic functions every
port should implement like: context switch, exception handling,
OpenRISC ABI and machine definitions and configurations.
---
cpukit/configure.ac|1 +
cpukit/score/cpu/Makefile.am |1 +
cpukit/score/cpu/or1k/Makefile.am | 36 +
cpukit/score/cpu/or1k/asm.h| 104 ++
cpukit/score/cpu/or1k/cpu.c| 120 +++
cpukit/score/cpu/or1k/or1k-context-initialize.c| 43 +
cpukit/score/cpu/or1k/or1k-context-switch.S| 115 +++
cpukit/score/cpu/or1k/or1k-exception-default.c | 24 +
cpukit/score/cpu/or1k/or1k-exception-frame-print.c | 22 +
cpukit/score/cpu/or1k/or1k-exception-handler-low.S | 285 ++
cpukit/score/cpu/or1k/rtems/asm.h | 99 ++
cpukit/score/cpu/or1k/rtems/score/cpu.h| 1049
cpukit/score/cpu/or1k/rtems/score/cpu_asm.h| 74 ++
cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 334 +++
cpukit/score/cpu/or1k/rtems/score/or1k.h | 49 +
cpukit/score/cpu/or1k/rtems/score/types.h | 51 +
16 files changed, 2407 insertions(+)
create mode 100644 cpukit/score/cpu/or1k/Makefile.am
create mode 100644 cpukit/score/cpu/or1k/asm.h
create mode 100644 cpukit/score/cpu/or1k/cpu.c
create mode 100644 cpukit/score/cpu/or1k/or1k-context-initialize.c
create mode 100644 cpukit/score/cpu/or1k/or1k-context-switch.S
create mode 100644 cpukit/score/cpu/or1k/or1k-exception-default.c
create mode 100644 cpukit/score/cpu/or1k/or1k-exception-frame-print.c
create mode 100644 cpukit/score/cpu/or1k/or1k-exception-handler-low.S
create mode 100644 cpukit/score/cpu/or1k/rtems/asm.h
You have two of these asm.h files. You should only have this one.
create mode 100644 cpukit/score/cpu/or1k/rtems/score/cpu.h
create mode 100644 cpukit/score/cpu/or1k/rtems/score/cpu_asm.h
create mode 100644 cpukit/score/cpu/or1k/rtems/score/or1k-utility.h
create mode 100644 cpukit/score/cpu/or1k/rtems/score/or1k.h
create mode 100644 cpukit/score/cpu/or1k/rtems/score/types.h
[...]
diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c
new file mode 100644
index 000..05e4cd9
--- /dev/null
+++ b/cpukit/score/cpu/or1k/cpu.c
@@ -0,0 +1,120 @@
+/*
+ * Opencore OR1K CPU Dependent Source
+ *
+ * COPYRIGHT (c) 2014 Hesham ALMatary heshamelmat...@gmail.com
+ * COPYRIGHT (c) 1989-1999.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ */
+
+#include rtems/system.h
+#include rtems/score/isr.h
+#include rtems/score/wkspace.h
+#include bsp/linker-symbols.h
+
+/**
+ * @brief Performs processor dependent initialization.
+ */
+void _CPU_Initialize(void)
+{
+ /* Do nothing */
+}
+
+/**
+ * @brief Sets the hardware interrupt level by the level value.
+ *
+ * @param[in] level for or1k can only range over two values:
+ * 0 (enable interrupts) and 1 (disable interrupts). In future
+ * implementations if fast context switch is implemented, the level
+ * can range from 0 to 15. @see OpenRISC architecture manual.
+ *
+ */
+inline void _CPU_ISR_Set_level(uint32_t level)
+{
+ uint32_t sr = 0;
+ level = (level 0)? 1 : 0;
+
+ /* map level bit to or1k interrupt enable/disable bit in sr register */
+ level = CPU_OR1K_SPR_SR_SHAMT_IEE;
+
+ sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
+
+ if (level == 0) /* Enable all interrupts */
+ {
+sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
+ }
+ else
+ {
+sr = CPU_OR1K_ISR_STATUS_MASK_I_DIS;
+ }
Put braces on same line as if/else, e.g.:
if ( level == 0 ) {
...
} else {
...
}
+
+ _OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
+ }
+
+uint32_t _CPU_ISR_Get_level( void )
+{
+ uint32_t sr = 0;
+
+ sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
+
+ return (sr CPU_OR1K_SPR_SR_IEE)? 0 : 1;
+}
+
Why aren't these static inlines?
+void _CPU_ISR_install_raw_handler(
+ uint32_t vector,
+ proc_ptrnew_handler,
+ proc_ptr *old_handler
+)
+{
+
+}
+
+void _CPU_ISR_install_vector(
+ uint32_tvector,
+ proc_ptrnew_handler,
+ proc_ptr *old_handler
+)
+{
+ volatile proc_ptr *table =
+ (proc_ptr *) bsp_start_vector_table_begin;
Why is this volatile?
Likely history.
+ proc_ptr current_handler;
+
+ ISR_Level level;
+
+ _ISR_Disable( level );
+
+ current_handler = table [vector];
+
+ /* The current
Re: [PATCH 1/2] arm: Add support for FPv4-SP floating point unit
On Aug 11, 2014, at 17:02 , Gedare Bloom ged...@rtems.org wrote: +#ifdef ARM_MULTILIB_VFP + /* CPACR is located at address 0xe000ed88 */ + ldr.w r0, =0xe000ed88 Maybe the constant should be provided by a header file? The comments are nice though. And I didn't see anything else in the rest, although my arm asm is rusty. When used in a single place in a hardware specific C file I prefer a constant. When I'm suspicious I'm comparing definitions against the reference manuals looking for transcription errors and I'd rather avoid the indirection. Obviously it needs an appropriate constant (which Sebastian provides). Peter - Peter Dufault HD Associates, Inc. Software and System Engineering ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 1/2] arm: Add support for FPv4-SP floating point unit
On 08/11/2014 11:12 PM, Joel Sherrill wrote: Is there any tool patch missing? I may be thinking of nios and I think I committed that. No tool patch is missing. I use currently the latest GCC 4.9 without any patches. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] Add support for OpenRISC - Fixed issues
OK from me. On Tue, Aug 12, 2014 at 11:57 AM, Hesham ALMatary heshamelmat...@gmail.com wrote: This work is based on the old or32 port (that has been removed back in 2005) authored by Chris Ziomkowski. The patch includes the basic functions every port should implement like: context switch, exception handling, OpenRISC ABI and machine definitions and configurations. --- cpukit/configure.ac|1 + cpukit/score/cpu/Makefile.am |1 + cpukit/score/cpu/or1k/Makefile.am | 36 + cpukit/score/cpu/or1k/cpu.c| 112 +++ cpukit/score/cpu/or1k/or1k-context-initialize.c| 43 + cpukit/score/cpu/or1k/or1k-context-switch.S| 115 +++ cpukit/score/cpu/or1k/or1k-exception-default.c | 24 + cpukit/score/cpu/or1k/or1k-exception-frame-print.c | 22 + cpukit/score/cpu/or1k/or1k-exception-handler-low.S | 217 cpukit/score/cpu/or1k/rtems/asm.h | 99 ++ cpukit/score/cpu/or1k/rtems/score/cpu.h| 1051 cpukit/score/cpu/or1k/rtems/score/cpu_asm.h| 74 ++ cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 371 +++ cpukit/score/cpu/or1k/rtems/score/or1k.h | 49 + cpukit/score/cpu/or1k/rtems/score/types.h | 51 + 15 files changed, 2266 insertions(+) create mode 100644 cpukit/score/cpu/or1k/Makefile.am create mode 100644 cpukit/score/cpu/or1k/cpu.c create mode 100644 cpukit/score/cpu/or1k/or1k-context-initialize.c create mode 100644 cpukit/score/cpu/or1k/or1k-context-switch.S create mode 100644 cpukit/score/cpu/or1k/or1k-exception-default.c create mode 100644 cpukit/score/cpu/or1k/or1k-exception-frame-print.c create mode 100644 cpukit/score/cpu/or1k/or1k-exception-handler-low.S create mode 100644 cpukit/score/cpu/or1k/rtems/asm.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/cpu.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/cpu_asm.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/or1k-utility.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/or1k.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/types.h diff --git a/cpukit/configure.ac b/cpukit/configure.ac index 19e5b81..56815e2 100644 --- a/cpukit/configure.ac +++ b/cpukit/configure.ac @@ -382,6 +382,7 @@ score/cpu/m32r/Makefile score/cpu/mips/Makefile score/cpu/moxie/Makefile score/cpu/nios2/Makefile +score/cpu/or1k/Makefile score/cpu/powerpc/Makefile score/cpu/sh/Makefile score/cpu/sparc/Makefile diff --git a/cpukit/score/cpu/Makefile.am b/cpukit/score/cpu/Makefile.am index 8d28fc2..69abcd6 100644 --- a/cpukit/score/cpu/Makefile.am +++ b/cpukit/score/cpu/Makefile.am @@ -14,6 +14,7 @@ DIST_SUBDIRS += mips DIST_SUBDIRS += moxie DIST_SUBDIRS += nios2 DIST_SUBDIRS += no_cpu +DIST_SUBDIRS += or1k DIST_SUBDIRS += powerpc DIST_SUBDIRS += sh DIST_SUBDIRS += sparc diff --git a/cpukit/score/cpu/or1k/Makefile.am b/cpukit/score/cpu/or1k/Makefile.am new file mode 100644 index 000..b3a8ade --- /dev/null +++ b/cpukit/score/cpu/or1k/Makefile.am @@ -0,0 +1,36 @@ +include $(top_srcdir)/automake/compile.am + +CLEANFILES = +DISTCLEANFILES = + +include_rtemsdir = $(includedir)/rtems + +include_rtems_HEADERS = rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score + +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += rtems/score/cpu.h +include_rtems_score_HEADERS += rtems/score/cpu_asm.h +include_rtems_score_HEADERS += rtems/score/types.h +include_rtems_score_HEADERS += rtems/score/or1k.h +include_rtems_score_HEADERS += rtems/score/or1k-utility.h + + + +noinst_LIBRARIES = libscorecpu.a + +libscorecpu_a_SOURCES = +libscorecpu_a_SOURCES += cpu.c +libscorecpu_a_SOURCES += or1k-context-switch.S +libscorecpu_a_SOURCES += or1k-context-initialize.c +libscorecpu_a_SOURCES += or1k-exception-default.c +libscorecpu_a_SOURCES += or1k-exception-frame-print.c +libscorecpu_a_SOURCES += or1k-exception-handler-low.S + +libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) + +all-local: $(PREINSTALL_FILES) + +include $(srcdir)/preinstall.am +include $(top_srcdir)/automake/local.am diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c new file mode 100644 index 000..9ba49a5 --- /dev/null +++ b/cpukit/score/cpu/or1k/cpu.c @@ -0,0 +1,112 @@ +/* + * Opencore OR1K CPU Dependent Source + * + * COPYRIGHT (c) 2014 Hesham ALMatary heshamelmat...@gmail.com + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#include rtems/system.h +#include rtems/score/isr.h +#include rtems/score/wkspace.h +#include bsp/linker-symbols.h +#include rtems/score/cpu.h + +/** + * @brief Performs processor
Re: [PATCH] Add support for OpenRISC - Fixed issues
OK with me. It will be easier to address issues once merged anyway. I plan to commit, try to build, report, then Hesham can rebase and report. On August 12, 2014 12:49:10 PM CDT, Gedare Bloom ged...@rtems.org wrote: OK from me. On Tue, Aug 12, 2014 at 11:57 AM, Hesham ALMatary heshamelmat...@gmail.com wrote: This work is based on the old or32 port (that has been removed back in 2005) authored by Chris Ziomkowski. The patch includes the basic functions every port should implement like: context switch, exception handling, OpenRISC ABI and machine definitions and configurations. --- cpukit/configure.ac|1 + cpukit/score/cpu/Makefile.am |1 + cpukit/score/cpu/or1k/Makefile.am | 36 + cpukit/score/cpu/or1k/cpu.c| 112 +++ cpukit/score/cpu/or1k/or1k-context-initialize.c| 43 + cpukit/score/cpu/or1k/or1k-context-switch.S| 115 +++ cpukit/score/cpu/or1k/or1k-exception-default.c | 24 + cpukit/score/cpu/or1k/or1k-exception-frame-print.c | 22 + cpukit/score/cpu/or1k/or1k-exception-handler-low.S | 217 cpukit/score/cpu/or1k/rtems/asm.h | 99 ++ cpukit/score/cpu/or1k/rtems/score/cpu.h| 1051 cpukit/score/cpu/or1k/rtems/score/cpu_asm.h| 74 ++ cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 371 +++ cpukit/score/cpu/or1k/rtems/score/or1k.h | 49 + cpukit/score/cpu/or1k/rtems/score/types.h | 51 + 15 files changed, 2266 insertions(+) create mode 100644 cpukit/score/cpu/or1k/Makefile.am create mode 100644 cpukit/score/cpu/or1k/cpu.c create mode 100644 cpukit/score/cpu/or1k/or1k-context-initialize.c create mode 100644 cpukit/score/cpu/or1k/or1k-context-switch.S create mode 100644 cpukit/score/cpu/or1k/or1k-exception-default.c create mode 100644 cpukit/score/cpu/or1k/or1k-exception-frame-print.c create mode 100644 cpukit/score/cpu/or1k/or1k-exception-handler-low.S create mode 100644 cpukit/score/cpu/or1k/rtems/asm.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/cpu.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/cpu_asm.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/or1k-utility.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/or1k.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/types.h diff --git a/cpukit/configure.ac b/cpukit/configure.ac index 19e5b81..56815e2 100644 --- a/cpukit/configure.ac +++ b/cpukit/configure.ac @@ -382,6 +382,7 @@ score/cpu/m32r/Makefile score/cpu/mips/Makefile score/cpu/moxie/Makefile score/cpu/nios2/Makefile +score/cpu/or1k/Makefile score/cpu/powerpc/Makefile score/cpu/sh/Makefile score/cpu/sparc/Makefile diff --git a/cpukit/score/cpu/Makefile.am b/cpukit/score/cpu/Makefile.am index 8d28fc2..69abcd6 100644 --- a/cpukit/score/cpu/Makefile.am +++ b/cpukit/score/cpu/Makefile.am @@ -14,6 +14,7 @@ DIST_SUBDIRS += mips DIST_SUBDIRS += moxie DIST_SUBDIRS += nios2 DIST_SUBDIRS += no_cpu +DIST_SUBDIRS += or1k DIST_SUBDIRS += powerpc DIST_SUBDIRS += sh DIST_SUBDIRS += sparc diff --git a/cpukit/score/cpu/or1k/Makefile.am b/cpukit/score/cpu/or1k/Makefile.am new file mode 100644 index 000..b3a8ade --- /dev/null +++ b/cpukit/score/cpu/or1k/Makefile.am @@ -0,0 +1,36 @@ +include $(top_srcdir)/automake/compile.am + +CLEANFILES = +DISTCLEANFILES = + +include_rtemsdir = $(includedir)/rtems + +include_rtems_HEADERS = rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score + +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += rtems/score/cpu.h +include_rtems_score_HEADERS += rtems/score/cpu_asm.h +include_rtems_score_HEADERS += rtems/score/types.h +include_rtems_score_HEADERS += rtems/score/or1k.h +include_rtems_score_HEADERS += rtems/score/or1k-utility.h + + + +noinst_LIBRARIES = libscorecpu.a + +libscorecpu_a_SOURCES = +libscorecpu_a_SOURCES += cpu.c +libscorecpu_a_SOURCES += or1k-context-switch.S +libscorecpu_a_SOURCES += or1k-context-initialize.c +libscorecpu_a_SOURCES += or1k-exception-default.c +libscorecpu_a_SOURCES += or1k-exception-frame-print.c +libscorecpu_a_SOURCES += or1k-exception-handler-low.S + +libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) + +all-local: $(PREINSTALL_FILES) + +include $(srcdir)/preinstall.am +include $(top_srcdir)/automake/local.am diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c new file mode 100644 index 000..9ba49a5 --- /dev/null +++ b/cpukit/score/cpu/or1k/cpu.c @@ -0,0 +1,112 @@ +/* + * Opencore OR1K CPU Dependent Source + * + * COPYRIGHT (c) 2014 Hesham ALMatary heshamelmat...@gmail.com + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + *
Re: [PATCH 1/2] arm: Add support for FPv4-SP floating point unit
On 08/12/2014 04:08 PM, Gedare Bloom wrote: On Tue, Aug 12, 2014 at 7:32 AM, Peter Dufaultdufa...@hda.com wrote: On Aug 11, 2014, at 17:02 , Gedare Bloomged...@rtems.org wrote: +#ifdef ARM_MULTILIB_VFP + /* CPACR is located at address 0xe000ed88 */ + ldr.w r0, =0xe000ed88 Maybe the constant should be provided by a header file? The comments are nice though. And I didn't see anything else in the rest, although my arm asm is rusty. When used in a single place in a hardware specific C file I prefer a constant. When I'm suspicious I'm comparing definitions against the reference manuals looking for transcription errors and I'd rather avoid the indirection. Obviously it needs an appropriate constant (which Sebastian provides). True, and the comment is pretty clear. So, either way. I guess I am surprised the constant is only used in this one place. If there is only one place, then there is no real need for a define. I added improved exception support, so now we have two places and a define. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] Add support for OpenRISC - Fixed issues
Feedback after committing: 1) cpukit/score/cpu/or1k/prenstall.am was not in patch. I added and committed it. 2) Without a BSP to specify, nothing gets built. See how your tree works now that you can rebase. Then let's get the BSP reviewed and merged. --joel On 8/12/2014 12:49 PM, Gedare Bloom wrote: OK from me. On Tue, Aug 12, 2014 at 11:57 AM, Hesham ALMatary heshamelmat...@gmail.com wrote: This work is based on the old or32 port (that has been removed back in 2005) authored by Chris Ziomkowski. The patch includes the basic functions every port should implement like: context switch, exception handling, OpenRISC ABI and machine definitions and configurations. --- cpukit/configure.ac|1 + cpukit/score/cpu/Makefile.am |1 + cpukit/score/cpu/or1k/Makefile.am | 36 + cpukit/score/cpu/or1k/cpu.c| 112 +++ cpukit/score/cpu/or1k/or1k-context-initialize.c| 43 + cpukit/score/cpu/or1k/or1k-context-switch.S| 115 +++ cpukit/score/cpu/or1k/or1k-exception-default.c | 24 + cpukit/score/cpu/or1k/or1k-exception-frame-print.c | 22 + cpukit/score/cpu/or1k/or1k-exception-handler-low.S | 217 cpukit/score/cpu/or1k/rtems/asm.h | 99 ++ cpukit/score/cpu/or1k/rtems/score/cpu.h| 1051 cpukit/score/cpu/or1k/rtems/score/cpu_asm.h| 74 ++ cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 371 +++ cpukit/score/cpu/or1k/rtems/score/or1k.h | 49 + cpukit/score/cpu/or1k/rtems/score/types.h | 51 + 15 files changed, 2266 insertions(+) create mode 100644 cpukit/score/cpu/or1k/Makefile.am create mode 100644 cpukit/score/cpu/or1k/cpu.c create mode 100644 cpukit/score/cpu/or1k/or1k-context-initialize.c create mode 100644 cpukit/score/cpu/or1k/or1k-context-switch.S create mode 100644 cpukit/score/cpu/or1k/or1k-exception-default.c create mode 100644 cpukit/score/cpu/or1k/or1k-exception-frame-print.c create mode 100644 cpukit/score/cpu/or1k/or1k-exception-handler-low.S create mode 100644 cpukit/score/cpu/or1k/rtems/asm.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/cpu.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/cpu_asm.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/or1k-utility.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/or1k.h create mode 100644 cpukit/score/cpu/or1k/rtems/score/types.h diff --git a/cpukit/configure.ac b/cpukit/configure.ac index 19e5b81..56815e2 100644 --- a/cpukit/configure.ac +++ b/cpukit/configure.ac @@ -382,6 +382,7 @@ score/cpu/m32r/Makefile score/cpu/mips/Makefile score/cpu/moxie/Makefile score/cpu/nios2/Makefile +score/cpu/or1k/Makefile score/cpu/powerpc/Makefile score/cpu/sh/Makefile score/cpu/sparc/Makefile diff --git a/cpukit/score/cpu/Makefile.am b/cpukit/score/cpu/Makefile.am index 8d28fc2..69abcd6 100644 --- a/cpukit/score/cpu/Makefile.am +++ b/cpukit/score/cpu/Makefile.am @@ -14,6 +14,7 @@ DIST_SUBDIRS += mips DIST_SUBDIRS += moxie DIST_SUBDIRS += nios2 DIST_SUBDIRS += no_cpu +DIST_SUBDIRS += or1k DIST_SUBDIRS += powerpc DIST_SUBDIRS += sh DIST_SUBDIRS += sparc diff --git a/cpukit/score/cpu/or1k/Makefile.am b/cpukit/score/cpu/or1k/Makefile.am new file mode 100644 index 000..b3a8ade --- /dev/null +++ b/cpukit/score/cpu/or1k/Makefile.am @@ -0,0 +1,36 @@ +include $(top_srcdir)/automake/compile.am + +CLEANFILES = +DISTCLEANFILES = + +include_rtemsdir = $(includedir)/rtems + +include_rtems_HEADERS = rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score + +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += rtems/score/cpu.h +include_rtems_score_HEADERS += rtems/score/cpu_asm.h +include_rtems_score_HEADERS += rtems/score/types.h +include_rtems_score_HEADERS += rtems/score/or1k.h +include_rtems_score_HEADERS += rtems/score/or1k-utility.h + + + +noinst_LIBRARIES = libscorecpu.a + +libscorecpu_a_SOURCES = +libscorecpu_a_SOURCES += cpu.c +libscorecpu_a_SOURCES += or1k-context-switch.S +libscorecpu_a_SOURCES += or1k-context-initialize.c +libscorecpu_a_SOURCES += or1k-exception-default.c +libscorecpu_a_SOURCES += or1k-exception-frame-print.c +libscorecpu_a_SOURCES += or1k-exception-handler-low.S + +libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) + +all-local: $(PREINSTALL_FILES) + +include $(srcdir)/preinstall.am +include $(top_srcdir)/automake/local.am diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c new file mode 100644 index 000..9ba49a5 --- /dev/null +++ b/cpukit/score/cpu/or1k/cpu.c @@ -0,0 +1,112 @@ +/* + * Opencore OR1K CPU Dependent Source + * + * COPYRIGHT (c) 2014 Hesham ALMatary heshamelmat...@gmail.com + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be
