Re: How can I check if a function exists in waf?

On 1/2/19 8:19 pm, Sebastian Huber wrote: > > So, there is no standard compile and link test for functions? If I use this > >     conf.check_cc(fragment = 'int main(void) { strnlen("", 0); return 0; }', >   header_name="string.h", features = 'c', mandatory = False) > > waf

Re: RISC-V double float alignment

On Fri, Feb 1, 2019, 11:38 AM Hesham Almatary On Fri, 1 Feb 2019 at 15:08, Jiri Gaisler wrote: > > > > Hello, > > > > As far as I understand, RISC-V does not require any particular alignment > > of data structures in memory. Nevertheless, the compiler automatically > > aligns data structures on

Re: RISC-V double float alignment

On Fri, 1 Feb 2019 at 15:08, Jiri Gaisler wrote: > > Hello, > > As far as I understand, RISC-V does not require any particular alignment > of data structures in memory. Nevertheless, the compiler automatically > aligns data structures on their natural sizes, i.e. ints are aligned on > 4-byte and

Re: RISC-V double float alignment

On 2019-02-01 10:08, Jiri Gaisler wrote: > Hello, > > As far as I understand, RISC-V does not require any particular alignment > of data structures in memory. [ ... ] RISC-V explicitly states somewhere in the manuals, (?) that it supports unaligned access to memory, but it could be emulated in

RISC-V double float alignment

Hello, As far as I understand, RISC-V does not require any particular alignment of data structures in memory. Nevertheless, the compiler automatically aligns data structures on their natural sizes, i.e. ints are aligned on 4-byte and doubles on 8-bytes boundaries. sis-riscv with support for

Re: [PATCH] Coverage : Add coverage support for RISCV

On Fri, 1 Feb 2019 at 20:23, Vijay Kumar Banerjee wrote: > --- > tester/covoar/TargetFactory.cc | 2 + > tester/covoar/Target_riscv.cc| 82 > tester/covoar/Target_riscv.h | 98 > tester/covoar/wscript

[PATCH] Coverage : Add coverage support for RISCV

--- tester/covoar/TargetFactory.cc | 2 + tester/covoar/Target_riscv.cc| 82 tester/covoar/Target_riscv.h | 98 tester/covoar/wscript| 3 +- tester/rtems/testing/bsps/griscv-sis-cov.ini |

Re: BSP for Xilinx Zynq UltraScale+ MPSoC platform

On Fri, Feb 1, 2019, 7:04 AM Alan Cudmore I would like to see both R5 and A53 support. Having RTEMS on the R5 could > allow it to be used for OpenAMP communication with the A53. Normally the > OpenAMP port for the Xilinx board uses bare metal or FreeRTOS on the R5. > +1 > For the A53, is there

Re: BSP for Xilinx Zynq UltraScale+ MPSoC platform

On 01/02/2019 15:04, Alan Cudmore wrote: For the A53, is there a reason for choosing Aarch32 vs Aarch64 for the RTEMS port? The AArch64 is a new architecture. For the AArch32 we can hopefully use the existing stuff from the ARM port. -- Sebastian Huber, embedded brains GmbH Address :

Re: BSP for Xilinx Zynq UltraScale+ MPSoC platform

I would like to see both R5 and A53 support. Having RTEMS on the R5 could allow it to be used for OpenAMP communication with the A53. Normally the OpenAMP port for the Xilinx board uses bare metal or FreeRTOS on the R5. For the A53, is there a reason for choosing Aarch32 vs Aarch64 for the RTEMS

Re: coverage : not getting coverage for leon3-sis-cov

On Fri, 1 Feb 2019 at 14:04, Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > Hello, > > you need the tools from the latest RSB. > Thanks! It worked. :) > > However, the SIS crashed using an ERC32 test program: > > gdb --args sparc-rtems5-sis -nouartrx -r -cov spsysinit01.exe > GNU

[PATCH] Coverage: Add support for TSIM format

--- tester/rt/coverage.py | 28 - tester/rtems/testing/bsps/leon3-sis-cov.ini | 3 ++- 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/tester/rt/coverage.py b/tester/rt/coverage.py index 9fc9b64..859001a 100644 --- a/tester/rt/coverage.py

Re: coverage : not getting coverage for leon3-sis-cov

On 2/1/19 11:17 AM, Jiri Gaisler wrote: > On 2/1/19 9:34 AM, Sebastian Huber wrote: >> Hello, >> >> you need the tools from the latest RSB. >> >> However, the SIS crashed using an ERC32 test program: > > Yes, seems like I broke erc32 emulation. Leon2/3 still works fine - I will > investigate...

Re: coverage : not getting coverage for leon3-sis-cov

On 2/1/19 9:34 AM, Sebastian Huber wrote: > Hello, > > you need the tools from the latest RSB. > > However, the SIS crashed using an ERC32 test program: Yes, seems like I broke erc32 emulation. Leon2/3 still works fine - I will investigate... > > gdb --args sparc-rtems5-sis -nouartrx -r -cov

Test Framework Documentation to User Manual or Software Engineering?

Hello, should the documentation for the new test code framework go into the user manual or the software engineering guide? The user manual already has some stuff about testing, but I am not sure if the user manual is the right place for a test code framework description.

Re: How can I check if a function exists in waf?

On 01/02/2019 10:06, Vijay Kumar Banerjee wrote: On Fri, 1 Feb 2019 at 12:13, Sebastian Huber > wrote: Hello, how can I check if a function exists in waf (similar to AC_CHECK_FUNC)? Currently, we get this output from the RTEMS tools

Re: How can I check if a function exists in waf?

On Fri, 1 Feb 2019 at 12:13, Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > Hello, > > how can I check if a function exists in waf (similar to AC_CHECK_FUNC)? > Currently, we get this output from the RTEMS tools waf configure (please > note the "Invalid argument 'function_name' in

Re: [PATCH v2 00/10] Rework quick start in user manual

On 28/01/2019 13:27, Sebastian Huber wrote: This patch set reworks the quick start chapter in the user manual. You find a PDF with this patch set here: https://ftp.rtems.org/pub/rtems/people/sebh/user.pdf It duplicates some information with the "Installation" chapter. The "Installation"