[rtems-tools PATCH 1/2] rtemstoolkit: Update SimpleIni to latest

2023-11-21 Thread chrisj 
From: Chris Johns 

The resolves C++17 warnings.

Updates #4970
---
 rtemstoolkit/SimpleIni.h | 598 +++
 1 file changed, 419 insertions(+), 179 deletions(-)

diff --git a/rtemstoolkit/SimpleIni.h b/rtemstoolkit/SimpleIni.h
index fd37c4b..ec99abb 100644
--- a/rtemstoolkit/SimpleIni.h
+++ b/rtemstoolkit/SimpleIni.h
@@ -3,9 +3,9 @@
 
 Library SimpleIni
 FileSimpleIni.h
-Author  Brodie Thiesfield [code at jellycan dot com]
+Author  Brodie Thiesfield
 Source  https://github.com/brofield/simpleini
-Version 4.17
+Version 4.20
 
 
 Jump to the @link CSimpleIniTempl CSimpleIni @endlink interface 
documentation.
@@ -20,7 +20,7 @@
 @section features FEATURES
 
 - MIT Licence allows free use in all software (including GPL and 
commercial)
-- multi-platform (Windows 95/98/ME/NT/2K/XP/2003, Windows CE, Linux, Unix)
+- multi-platform (Windows CE/9x/NT..10/etc, Linux, MacOSX, Unix)
 - loading and saving of INI-style configuration files
 - configuration files can have any newline format on all platforms
 - liberal acceptance of file format
@@ -42,22 +42,31 @@
 - Windows/VC6 (warning level 3)
 - Windows/VC.NET 2003 (warning level 4)
 - Windows/VC 2005 (warning level 4)
+- Windows/VC 2019 (warning level 4)
 - Linux/gcc (-Wall)
 
 
 @section usage USAGE SUMMARY
 
+-#  Decide if you will be using utf8 or MBCS files, and working with the
+data in utf8, wchar_t or ICU chars. 
+-#  If you will only be using straight utf8 files and access the data via 
the 
+char interface, then you do not need any conversion library and could 
define 
+SI_NO_CONVERSION. Note that no conversion also means no validation of 
the data.
+If no converter is specified then the default converter is 
SI_CONVERT_GENERIC 
+on Mac/Linux and SI_CONVERT_WIN32 on Windows. If you need widechar 
support on 
+Mac/Linux then use either SI_CONVERT_GENERIC or SI_CONVERT_ICU. These 
are also
+supported on all platforms.
 -#  Define the appropriate symbol for the converter you wish to use and
-include the SimpleIni.h header file. If no specific converter is 
defined
-then the default converter is used. The default conversion mode uses
-SI_CONVERT_WIN32 on Windows and SI_CONVERT_GENERIC on all other
-platforms. If you are using ICU then SI_CONVERT_ICU is supported on all
-platforms.
--#  Declare an instance the appropriate class. Note that the following
+include the SimpleIni.h header file. 
+-#  Declare an instance of the appropriate class. Note that the following
 definitions are just shortcuts for commonly used types. Other types
 (PRUnichar, unsigned short, unsigned char) are also possible.
 
-Interface   Case-sensitive  Load UTF-8  Load 
MBCS   Typedef
+Interface   Case-sensitive  Load UTF-8  Load 
MBCS   Typedef
+SI_NO_CONVERSION
+charNo  Yes No 
 CSimpleIniA
+charYes Yes No 
 CSimpleIniCaseA
 SI_CONVERT_GENERIC
 charNo  Yes Yes #1 
 CSimpleIniA
 charYes Yes Yes
 CSimpleIniCaseA
@@ -88,6 +97,8 @@
 GetValueReturn a value for a section & key
 SetValueAdd or update a value for a section & 
key
 Delete  Remove a section, or a key from a 
section
+SectionExists   Does a section exist?
+KeyExists   Does a key exist?
 
 -# Call Save() or SaveFile() to save the INI configuration data
 
@@ -161,9 +172,10 @@
   SI_STRLESS class, or by sorting the strings external to this library.
 - Usage of the  header on Windows can be disabled by defining
   SI_NO_MBCS. This is defined automatically on Windows CE platforms.
+- Not thread-safe so manage your own locking
 
 @section contrib CONTRIBUTIONS
-
+
 - 2010/05/03: Tobias Gehrig: added GetDoubleValue()
 
 @section licence MIT LICENCE
@@ -213,11 +225,11 @@
 #endif
 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 
 #ifdef SI_SUPPORT_IOSTREAMS
@@ -233,16 +245,16 @@
 # define SI_ASSERT(x)
 #endif
 
-enum SI_Error {
-SI_OK   =  0,   //!< No error
-SI_UPDATED  =  1,   //!< An existing value was updated
-SI_INSERTED =  2,   //!< A new value was inserted
+using SI_Error = int;
 
-// note: test for any error with (retval < 0)
-SI_FAIL = -1,   //!< Generic failure
-SI_NOMEM= -2,   //!< Out of memory error
-SI_FILE = -3//!< File error (see errno for detail error)
-};
+constexpr int SI_OK = 0;//!< No error
+constexpr int SI_UPDATED = 1;   //!<

[rtems-tools PATCH 2/2] rtemstoolkit, linkers: Fix C++17 warnings

2023-11-21 Thread chrisj 
From: Chris Johns 

Closes #4970
---
 linkers/rtems-exeinfo.cpp |  3 +--
 rtemstoolkit/rld-elf.cpp  | 12 
 rtemstoolkit/rld-elf.h|  5 -
 rtemstoolkit/rld-rap.cpp  |  9 ++---
 rtemstoolkit/rld.cpp  | 14 --
 5 files changed, 11 insertions(+), 32 deletions(-)

diff --git a/linkers/rtems-exeinfo.cpp b/linkers/rtems-exeinfo.cpp
index 0900812..0b43403 100644
--- a/linkers/rtems-exeinfo.cpp
+++ b/linkers/rtems-exeinfo.cpp
@@ -223,8 +223,7 @@ namespace rld
  * Helper for for_each to filter and load the sections we wish to
  * dump.
  */
-class section_loader:
-  public std::unary_function < const files::section, void >
+class section_loader
 {
 public:
 
diff --git a/rtemstoolkit/rld-elf.cpp b/rtemstoolkit/rld-elf.cpp
index 68efdbe..8b55818 100644
--- a/rtemstoolkit/rld-elf.cpp
+++ b/rtemstoolkit/rld-elf.cpp
@@ -200,18 +200,6 @@ namespace rld
   << std::endl;
 }
 
-section::section (const section& orig)
-  : file_ (orig.file_),
-index_ (orig.index_),
-name_ (orig.name_),
-scn (orig.scn),
-shdr (orig.shdr),
-data_ (orig.data_),
-rela (orig.rela),
-relocs (orig.relocs)
-{
-}
-
 section::section ()
   : file_ (0),
 index_ (-1),
diff --git a/rtemstoolkit/rld-elf.h b/rtemstoolkit/rld-elf.h
index 4919135..d66eee5 100644
--- a/rtemstoolkit/rld-elf.h
+++ b/rtemstoolkit/rld-elf.h
@@ -174,11 +174,6 @@ namespace rld
*/
   section (file& file_, int index);
 
-  /**
-   * Copy constructor.
-   */
-  section (const section& orig);
-
   /**
* Default constructor.
*/
diff --git a/rtemstoolkit/rld-rap.cpp b/rtemstoolkit/rld-rap.cpp
index 93ffbdc..045536a 100644
--- a/rtemstoolkit/rld-rap.cpp
+++ b/rtemstoolkit/rld-rap.cpp
@@ -696,8 +696,7 @@ namespace rld
  * Helper for for_each to merge the related object sections into the RAP
  * section.
  */
-class section_merge:
-  public std::unary_function < const files::section, void >
+class section_merge
 {
 public:
 
@@ -1191,8 +1190,7 @@ namespace rld
 /**
  * Helper for for_each to write out the various sections.
  */
-class section_writer:
-  public std::unary_function < object, void >
+class section_writer
 {
 public:
 
@@ -1364,8 +1362,6 @@ namespace rld
 void
 image::write_relocations (compress::compressor& comp)
 {
-  uint32_t rr = 0;
-
   for (int s = 0; s < rap_secs; ++s)
   {
 uint32_t count = get_relocations (s);
@@ -1515,7 +1511,6 @@ namespace rld
 
 ++rc;
 ++sr;
-++rr;
   }
 }
   }
diff --git a/rtemstoolkit/rld.cpp b/rtemstoolkit/rld.cpp
index 90fb39d..d0848ad 100644
--- a/rtemstoolkit/rld.cpp
+++ b/rtemstoolkit/rld.cpp
@@ -106,9 +106,10 @@ namespace rld
   ltrim (const std::string& s)
   {
 std::string t = s;
-t.erase (t.begin (),
- std::find_if (t.begin (), t.end (),
- std::not1 (std::ptr_fun < int, int > 
(std::isspace;
+auto non_space =
+  std::find_if (t.begin (), t.end (),
+[](unsigned char c) { return !std::isspace (c); });
+t.erase (t.begin (), non_space);
 return t;
   }
 
@@ -116,9 +117,10 @@ namespace rld
   rtrim (const std::string& s)
   {
 std::string t = s;
-t.erase (std::find_if (t.rbegin (), t.rend (),
-   std::not1 (std::ptr_fun < int, int > 
(std::isspace))).base(),
- t.end());
+auto last_space =
+  std::find_if (t.rbegin (), t.rend (),
+[](unsigned char c) { return !std::isspace (c); }).base();
+t.erase (last_space, t.end());
 return t;
   }
 
-- 
2.37.1

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[PATCH] waf: Fix Python 3.12 escape sequences

2023-11-21 Thread chrisj 
From: Chris Johns 

Updates #4968
---
 wscript | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/wscript b/wscript
index 69732d4e17..dd7fda7225 100755
--- a/wscript
+++ b/wscript
@@ -125,7 +125,7 @@ class Template(string.Template):
 idpattern = "[_A-Za-z][_A-Za-z0-9:#]*"
 
 
-_VAR_PATTERN = re.compile("\$\{?(" + Template.idpattern + ")\}?$")
+_VAR_PATTERN = re.compile("\\$\\{?(" + Template.idpattern + ")\\}?$")
 
 
 def _is_enabled_op_and(enabled, enabled_by):
-- 
2.37.1

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Re: [PATCH] 6: Use GCC 13.2

2023-11-21 Thread Joel Sherrill 
On Tue, Nov 21, 2023 at 5:29 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:

> On 12.09.23 08:43, Sebastian Huber wrote:
> >
> >
> > On 12.09.23 08:40, Chris Johns wrote:
> >> On 12/9/2023 4:31 pm, Sebastian Huber wrote:
> >>> On 27.07.23 13:33, Sebastian Huber wrote:
>  Prepare for RTEMS 6.1 release.
> 
>  Update #4921.
> >>> How do we want to proceed with the tools for the RTEMS 6.1 release?
> >> I need to move 6 to tar files but other tickets have taken what time I
> >> had.
> >
> > The patch uses a tar file for GCC. I guess for Newlib we have to host an
> > archive.
> >
> >>
> >>> Is GCC 13.2 still the desired GCC release?
> >> What is the alternative?
> >
> > Do we need one? GCC 13.2 is the best option from my point of view right
> > now.
>
> Can I check in the update to GCC 13.2?
>

Are there any test results to point to?

I'm generally ok if there are test results. But I didn't see any in the
build@ list

>
> --
> embedded brains GmbH
> Herr Sebastian HUBER
> Dornierstr. 4
> 82178 Puchheim
> Germany
> email: sebastian.hu...@embedded-brains.de
> phone: +49-89-18 94 741 - 16
> fax:   +49-89-18 94 741 - 08
>
> Registergericht: Amtsgericht München
> Registernummer: HRB 157899
> Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
> Unsere Datenschutzerklärung finden Sie hier:
> https://embedded-brains.de/datenschutzerklaerung/
> ___
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Re: [RSB 1/3] 6/7: Update Newlib

2023-11-21 Thread Joel Sherrill 
Thanks.

Ask Kinsey some time the weird situation that caught this.

--joel

On Tue, Nov 21, 2023 at 3:05 PM Chris Johns  wrote:

> OK to all 3 and thanks
>
> Chris
>
> On 21/11/2023 11:39 pm, Sebastian Huber wrote:
> > Pick up fixes for ARM/optimized-routines and the memory reclamation at
> thread
> > exit.
> >
> > Update #4510.
> > Update #4967.
> > ---
> >  rtems/config/tools/rtems-gcc-10-newlib-head.cfg   | 4 ++--
> >  rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg | 4 ++--
> >  rtems/config/tools/rtems-gcc-12-newlib-head.cfg   | 4 ++--
> >  rtems/config/tools/rtems-gcc-13-newlib-head.cfg   | 4 ++--
> >  rtems/config/tools/rtems-gcc-13.2-newlib-head.cfg | 4 ++--
> >  rtems/config/tools/rtems-gcc-head-newlib-head.cfg | 4 ++--
> >  6 files changed, 12 insertions(+), 12 deletions(-)
> >
> > diff --git a/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
> b/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
> > index 6668bc6..387e8c9 100644
> > --- a/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
> > +++ b/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
> > @@ -14,12 +14,12 @@
> >  %patch add gcc -p1
> https://devel.rtems.org/raw-attachment/ticket/4215/0001-nios2-Remove-custom-instruction-warnings.patch
> >  %hash sha512 0001-nios2-Remove-custom-instruction-warnings.patch
> afd8a5e6bdcc5b75d5fbbf558bdf56ccac400521a6eec9d88cc95f6be67c481f2dbf8faa0f6ddc1e4ac7c56a84938714d80e46e9cf80ec4b8fcd739986449881
> >
> > -%define newlib_version fbc5496
> > +%define newlib_version 3cacedb
> >  %define newlib_external 1
> >  %define newlib_expand_name
> sourceware-mirror-newlib-cygwin-%{newlib_version}
> >  %source set newlib --rsb-file=newlib-%{newlib_version}.tar.gz
> https://codeload.github.com/RTEMS/sourceware-mirror-newlib-cygwin/tar.gz/%{newlib_version}
> >  %hash sha512 newlib-%{newlib_version}.tar.gz \
> > -
> AFwyCjHHXfddx/lUcJbmcxSFOYtfj8cshzthqF9B2OtZxxxN/NQ8O+znhUPKDv20KjOBEMGh4VHpoiFBjZOrmA==
> > +
> ia0ce+bdENUO3qYj00jrZB8FjSejmTWuRqEdNE8nI2llf30mh8leUn5fCoHB0Oa7rRVBjEu3n0F12ZK9skuegQ==
> >
> >  %define with_threads 1
> >  %define with_plugin 0
> > diff --git a/rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg
> b/rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg
> > index dae3d2a..b37af1e 100644
> > --- a/rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg
> > +++ b/rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg
> > @@ -17,12 +17,12 @@
> >  %patch add gcc -p1
> https://devel.rtems.org/raw-attachment/ticket/4215/0001-nios2-Remove-custom-instruction-warnings.patch
> >  %hash sha512 0001-nios2-Remove-custom-instruction-warnings.patch
> afd8a5e6bdcc5b75d5fbbf558bdf56ccac400521a6eec9d88cc95f6be67c481f2dbf8faa0f6ddc1e4ac7c56a84938714d80e46e9cf80ec4b8fcd739986449881
> >
> > -%define newlib_version fbc5496
> > +%define newlib_version 3cacedb
> >  %define newlib_external 1
> >  %define newlib_expand_name
> sourceware-mirror-newlib-cygwin-%{newlib_version}
> >  %source set newlib --rsb-file=newlib-%{newlib_version}.tar.gz
> https://codeload.github.com/RTEMS/sourceware-mirror-newlib-cygwin/tar.gz/%{newlib_version}
> >  %hash sha512 newlib-%{newlib_version}.tar.gz \
> > -
> AFwyCjHHXfddx/lUcJbmcxSFOYtfj8cshzthqF9B2OtZxxxN/NQ8O+znhUPKDv20KjOBEMGh4VHpoiFBjZOrmA==
> > +
> ia0ce+bdENUO3qYj00jrZB8FjSejmTWuRqEdNE8nI2llf30mh8leUn5fCoHB0Oa7rRVBjEu3n0F12ZK9skuegQ==
> >
> >  %define with_threads 1
> >  %define with_plugin 0
> > diff --git a/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
> b/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
> > index 9fe1ddd..4a0c6d1 100644
> > --- a/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
> > +++ b/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
> > @@ -34,13 +34,13 @@
> >
> KEmxHjYOqY4LTXCMZ3I60tbHusbR5GlnP0CLARHPAnhCnovDj9K3U43C1bsMxDDGRqD6fwtrEFoEgqVFX63IuQ==
> >  # Comment above related to #4657 and patches ends here
> >
> > -%define newlib_version fbc5496
> > +%define newlib_version 3cacedb
> >  %define newlib_external 1
> >  %define newlib_expand_name
> sourceware-mirror-newlib-cygwin-%{newlib_version}
> >  %source set newlib --rsb-file=newlib-%{newlib_version}.tar.gz \
> >
> https://codeload.github.com/RTEMS/sourceware-mirror-newlib-cygwin/tar.gz/%{newlib_version}
> >  %hash sha512 newlib-%{newlib_version}.tar.gz \
> > -
> AFwyCjHHXfddx/lUcJbmcxSFOYtfj8cshzthqF9B2OtZxxxN/NQ8O+znhUPKDv20KjOBEMGh4VHpoiFBjZOrmA==
> > +
> ia0ce+bdENUO3qYj00jrZB8FjSejmTWuRqEdNE8nI2llf30mh8leUn5fCoHB0Oa7rRVBjEu3n0F12ZK9skuegQ==
> >
> >  %define with_threads 1
> >  %define with_plugin 0
> > diff --git a/rtems/config/tools/rtems-gcc-13-newlib-head.cfg
> b/rtems/config/tools/rtems-gcc-13-newlib-head.cfg
> > index 7d5f610..5529563 100644
> > --- a/rtems/config/tools/rtems-gcc-13-newlib-head.cfg
> > +++ b/rtems/config/tools/rtems-gcc-13-newlib-head.cfg
> > @@ -8,12 +8,12 @@
> >  %hash sha512 %{gcc_expand_name}.tar.gz \
> >
> nKBXN9Qt/9CRYDVOp1geQdshXDP/kvr82RV1fE1LVIxNCbAVvhRmqz1p5kycg24T3TNGHPN58RySceaYgc6sCw==
> >
> > -%define newlib_version fbc5496
> > +%define newlib_version 3cacedb
> >  %define

Re: [PATCH rtems v2] once.c, onceimplh.h: Make synchronization variable volatile

2023-11-21 Thread Joel Sherrill 
Thanks. I will pass this along and resubmit a patch to at least add a
comment and fix formatting issues.

Do we have a good place to add this information to the documentation?

On Tue, Nov 21, 2023, 5:35 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:

> On 20.11.23 18:42, Joel Sherrill wrote:
> > The loop that waits for another thread to complete the once
> > initialization was flagged as a potential infinite loop.
> > This is because there was no way to break out of the loop
> > inside the loop.  The solution is to make the state variable
> > volatile which indicates it may be modified by another thread
> > of execution.
> >
> > This was flagged by a user Coverity Scan run which apparently is
> > configured differently from the instance provided by Coverity to
> > open source projects.
>
> This is a configuration issue of Coverity Scan. You have to teach
> Coverity Scan something about:
>
> _Atomic_Fence( ATOMIC_ORDER_ACQUIRE );
> _Atomic_Fence( ATOMIC_ORDER_RELEASE );
>
> rtems_mutex_lock();
> rtems_condition_variable_wait();
> rtems_mutex_unlock();
>
> Using "volatile" for multi-threaded synchronization is not correct in
> C11 or later. This keyword is for device access. For multi-threaded
> synchronization you need atomic operations or mutexes, etc. From my
> point of view, Coverity Scan should warn if you use volatile for
> multi-threaded synchronization.
>
> --
> embedded brains GmbH
> Herr Sebastian HUBER
> Dornierstr. 4
> 82178 Puchheim
> Germany
> email: sebastian.hu...@embedded-brains.de
> phone: +49-89-18 94 741 - 16
> fax:   +49-89-18 94 741 - 08
>
> Registergericht: Amtsgericht München
> Registernummer: HRB 157899
> Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
> Unsere Datenschutzerklärung finden Sie hier:
> https://embedded-brains.de/datenschutzerklaerung/
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Re: [RSB 1/3] 6/7: Update Newlib

2023-11-21 Thread Chris Johns 
OK to all 3 and thanks

Chris

On 21/11/2023 11:39 pm, Sebastian Huber wrote:
> Pick up fixes for ARM/optimized-routines and the memory reclamation at thread
> exit.
> 
> Update #4510.
> Update #4967.
> ---
>  rtems/config/tools/rtems-gcc-10-newlib-head.cfg   | 4 ++--
>  rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg | 4 ++--
>  rtems/config/tools/rtems-gcc-12-newlib-head.cfg   | 4 ++--
>  rtems/config/tools/rtems-gcc-13-newlib-head.cfg   | 4 ++--
>  rtems/config/tools/rtems-gcc-13.2-newlib-head.cfg | 4 ++--
>  rtems/config/tools/rtems-gcc-head-newlib-head.cfg | 4 ++--
>  6 files changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/rtems/config/tools/rtems-gcc-10-newlib-head.cfg 
> b/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
> index 6668bc6..387e8c9 100644
> --- a/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
> +++ b/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
> @@ -14,12 +14,12 @@
>  %patch add gcc -p1 
> https://devel.rtems.org/raw-attachment/ticket/4215/0001-nios2-Remove-custom-instruction-warnings.patch
>  %hash sha512 0001-nios2-Remove-custom-instruction-warnings.patch 
> afd8a5e6bdcc5b75d5fbbf558bdf56ccac400521a6eec9d88cc95f6be67c481f2dbf8faa0f6ddc1e4ac7c56a84938714d80e46e9cf80ec4b8fcd739986449881
>  
> -%define newlib_version fbc5496
> +%define newlib_version 3cacedb
>  %define newlib_external 1
>  %define newlib_expand_name sourceware-mirror-newlib-cygwin-%{newlib_version}
>  %source set newlib --rsb-file=newlib-%{newlib_version}.tar.gz 
> https://codeload.github.com/RTEMS/sourceware-mirror-newlib-cygwin/tar.gz/%{newlib_version}
>  %hash sha512 newlib-%{newlib_version}.tar.gz \
> -  
> AFwyCjHHXfddx/lUcJbmcxSFOYtfj8cshzthqF9B2OtZxxxN/NQ8O+znhUPKDv20KjOBEMGh4VHpoiFBjZOrmA==
> +  
> ia0ce+bdENUO3qYj00jrZB8FjSejmTWuRqEdNE8nI2llf30mh8leUn5fCoHB0Oa7rRVBjEu3n0F12ZK9skuegQ==
>  
>  %define with_threads 1
>  %define with_plugin 0
> diff --git a/rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg 
> b/rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg
> index dae3d2a..b37af1e 100644
> --- a/rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg
> +++ b/rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg
> @@ -17,12 +17,12 @@
>  %patch add gcc -p1 
> https://devel.rtems.org/raw-attachment/ticket/4215/0001-nios2-Remove-custom-instruction-warnings.patch
>  %hash sha512 0001-nios2-Remove-custom-instruction-warnings.patch 
> afd8a5e6bdcc5b75d5fbbf558bdf56ccac400521a6eec9d88cc95f6be67c481f2dbf8faa0f6ddc1e4ac7c56a84938714d80e46e9cf80ec4b8fcd739986449881
>  
> -%define newlib_version fbc5496
> +%define newlib_version 3cacedb
>  %define newlib_external 1
>  %define newlib_expand_name sourceware-mirror-newlib-cygwin-%{newlib_version}
>  %source set newlib --rsb-file=newlib-%{newlib_version}.tar.gz 
> https://codeload.github.com/RTEMS/sourceware-mirror-newlib-cygwin/tar.gz/%{newlib_version}
>  %hash sha512 newlib-%{newlib_version}.tar.gz \
> -  
> AFwyCjHHXfddx/lUcJbmcxSFOYtfj8cshzthqF9B2OtZxxxN/NQ8O+znhUPKDv20KjOBEMGh4VHpoiFBjZOrmA==
> +  
> ia0ce+bdENUO3qYj00jrZB8FjSejmTWuRqEdNE8nI2llf30mh8leUn5fCoHB0Oa7rRVBjEu3n0F12ZK9skuegQ==
>  
>  %define with_threads 1
>  %define with_plugin 0
> diff --git a/rtems/config/tools/rtems-gcc-12-newlib-head.cfg 
> b/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
> index 9fe1ddd..4a0c6d1 100644
> --- a/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
> +++ b/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
> @@ -34,13 +34,13 @@
>  
> KEmxHjYOqY4LTXCMZ3I60tbHusbR5GlnP0CLARHPAnhCnovDj9K3U43C1bsMxDDGRqD6fwtrEFoEgqVFX63IuQ==
>  # Comment above related to #4657 and patches ends here
>  
> -%define newlib_version fbc5496
> +%define newlib_version 3cacedb
>  %define newlib_external 1
>  %define newlib_expand_name sourceware-mirror-newlib-cygwin-%{newlib_version}
>  %source set newlib --rsb-file=newlib-%{newlib_version}.tar.gz \
> 
> https://codeload.github.com/RTEMS/sourceware-mirror-newlib-cygwin/tar.gz/%{newlib_version}
>  %hash sha512 newlib-%{newlib_version}.tar.gz \
> -  
> AFwyCjHHXfddx/lUcJbmcxSFOYtfj8cshzthqF9B2OtZxxxN/NQ8O+znhUPKDv20KjOBEMGh4VHpoiFBjZOrmA==
> +  
> ia0ce+bdENUO3qYj00jrZB8FjSejmTWuRqEdNE8nI2llf30mh8leUn5fCoHB0Oa7rRVBjEu3n0F12ZK9skuegQ==
>  
>  %define with_threads 1
>  %define with_plugin 0
> diff --git a/rtems/config/tools/rtems-gcc-13-newlib-head.cfg 
> b/rtems/config/tools/rtems-gcc-13-newlib-head.cfg
> index 7d5f610..5529563 100644
> --- a/rtems/config/tools/rtems-gcc-13-newlib-head.cfg
> +++ b/rtems/config/tools/rtems-gcc-13-newlib-head.cfg
> @@ -8,12 +8,12 @@
>  %hash sha512 %{gcc_expand_name}.tar.gz \
>
> nKBXN9Qt/9CRYDVOp1geQdshXDP/kvr82RV1fE1LVIxNCbAVvhRmqz1p5kycg24T3TNGHPN58RySceaYgc6sCw==
>  
> -%define newlib_version fbc5496
> +%define newlib_version 3cacedb
>  %define newlib_external 1
>  %define newlib_expand_name sourceware-mirror-newlib-cygwin-%{newlib_version}
>  %source set newlib --rsb-file=newlib-%{newlib_version}.tar.gz 
>

[PATCH v3 rtems master 3/3] ZYNQ7000: Add support PYNQ, PicoZed, MicroZed, ZYBO and ZYBO Z7

2023-11-21 Thread Bernd Moessner 
This patch adds basic support for the following boards:

xilinx_zynq_pynq - PYNQ Z1 / Z2
xilinx_zynq_microzed - MicroZed 7010 / 7020
xilinx_zynq_picozed - PicoZed 7010 / 7015 / 7020 / 7030
xilinx_zynq_zybo - ZYBO
xilinx_zynq_zybo_z7 - ZYBO Z7-10 / Z7-20

N.b. Arty Z7-20 is basically a PYNQ Z1 - different board
color and updated Eth PHY.
---
 .../xilinx_zynq_microzed-testsuite.tcfg   |  7 +++
 .../config/xilinx_zynq_microzed.cfg   |  1 +
 .../config/xilinx_zynq_picozed-testsuite.tcfg |  7 +++
 .../config/xilinx_zynq_picozed.cfg|  1 +
 .../config/xilinx_zynq_pynq-testsuite.tcfg|  7 +++
 .../xilinx-zynq/config/xilinx_zynq_pynq.cfg   |  1 +
 .../config/xilinx_zynq_zybo-testsuite.tcfg|  7 +++
 .../xilinx-zynq/config/xilinx_zynq_zybo.cfg   |  1 +
 .../config/xilinx_zynq_zybo_z7-testsuite.tcfg |  7 +++
 .../config/xilinx_zynq_zybo_z7.cfg|  1 +
 .../bsps/arm/xilinx-zynq/bspmicrozed.yml  | 19 +++
 .../build/bsps/arm/xilinx-zynq/bsppicozed.yml | 19 +++
 spec/build/bsps/arm/xilinx-zynq/bsppynq.yml   | 19 +++
 spec/build/bsps/arm/xilinx-zynq/bspzybo.yml   | 19 +++
 spec/build/bsps/arm/xilinx-zynq/bspzyboz7.yml | 19 +++
 .../bsps/arm/xilinx-zynq/opta9periphclk.yml   | 12 ++--
 .../bsps/arm/xilinx-zynq/optclkcpu1x.yml  |  5 +
 .../build/bsps/arm/xilinx-zynq/optclkuart.yml |  5 +
 spec/build/bsps/arm/xilinx-zynq/optramlen.yml |  9 -
 spec/build/bsps/optconminor.yml   |  3 +++
 spec/build/cpukit/optsmp.yml  |  6 ++
 21 files changed, 172 insertions(+), 3 deletions(-)
 create mode 100755 
bsps/arm/xilinx-zynq/config/xilinx_zynq_microzed-testsuite.tcfg
 create mode 100755 bsps/arm/xilinx-zynq/config/xilinx_zynq_microzed.cfg
 create mode 100755 
bsps/arm/xilinx-zynq/config/xilinx_zynq_picozed-testsuite.tcfg
 create mode 100755 bsps/arm/xilinx-zynq/config/xilinx_zynq_picozed.cfg
 create mode 100755 bsps/arm/xilinx-zynq/config/xilinx_zynq_pynq-testsuite.tcfg
 create mode 100755 bsps/arm/xilinx-zynq/config/xilinx_zynq_pynq.cfg
 create mode 100755 bsps/arm/xilinx-zynq/config/xilinx_zynq_zybo-testsuite.tcfg
 create mode 100755 bsps/arm/xilinx-zynq/config/xilinx_zynq_zybo.cfg
 create mode 100755 
bsps/arm/xilinx-zynq/config/xilinx_zynq_zybo_z7-testsuite.tcfg
 create mode 100755 bsps/arm/xilinx-zynq/config/xilinx_zynq_zybo_z7.cfg
 create mode 100644 spec/build/bsps/arm/xilinx-zynq/bspmicrozed.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynq/bsppicozed.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynq/bsppynq.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynq/bspzybo.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynq/bspzyboz7.yml

diff --git a/bsps/arm/xilinx-zynq/config/xilinx_zynq_microzed-testsuite.tcfg 
b/bsps/arm/xilinx-zynq/config/xilinx_zynq_microzed-testsuite.tcfg
new file mode 100755
index 00..ba80faab99
--- /dev/null
+++ b/bsps/arm/xilinx-zynq/config/xilinx_zynq_microzed-testsuite.tcfg
@@ -0,0 +1,7 @@
+#
+# Xilinx Zedboard RTEMS Test Database.
+#
+# Format is one line per test that is _NOT_ built.
+#
+
+include: xilinx_zynq-testsuite.tcfg
diff --git a/bsps/arm/xilinx-zynq/config/xilinx_zynq_microzed.cfg 
b/bsps/arm/xilinx-zynq/config/xilinx_zynq_microzed.cfg
new file mode 100755
index 00..2de871d46e
--- /dev/null
+++ b/bsps/arm/xilinx-zynq/config/xilinx_zynq_microzed.cfg
@@ -0,0 +1 @@
+include $(RTEMS_ROOT)/make/custom/xilinx_zynq.inc
diff --git a/bsps/arm/xilinx-zynq/config/xilinx_zynq_picozed-testsuite.tcfg 
b/bsps/arm/xilinx-zynq/config/xilinx_zynq_picozed-testsuite.tcfg
new file mode 100755
index 00..ba80faab99
--- /dev/null
+++ b/bsps/arm/xilinx-zynq/config/xilinx_zynq_picozed-testsuite.tcfg
@@ -0,0 +1,7 @@
+#
+# Xilinx Zedboard RTEMS Test Database.
+#
+# Format is one line per test that is _NOT_ built.
+#
+
+include: xilinx_zynq-testsuite.tcfg
diff --git a/bsps/arm/xilinx-zynq/config/xilinx_zynq_picozed.cfg 
b/bsps/arm/xilinx-zynq/config/xilinx_zynq_picozed.cfg
new file mode 100755
index 00..2de871d46e
--- /dev/null
+++ b/bsps/arm/xilinx-zynq/config/xilinx_zynq_picozed.cfg
@@ -0,0 +1 @@
+include $(RTEMS_ROOT)/make/custom/xilinx_zynq.inc
diff --git a/bsps/arm/xilinx-zynq/config/xilinx_zynq_pynq-testsuite.tcfg 
b/bsps/arm/xilinx-zynq/config/xilinx_zynq_pynq-testsuite.tcfg
new file mode 100755
index 00..ba80faab99
--- /dev/null
+++ b/bsps/arm/xilinx-zynq/config/xilinx_zynq_pynq-testsuite.tcfg
@@ -0,0 +1,7 @@
+#
+# Xilinx Zedboard RTEMS Test Database.
+#
+# Format is one line per test that is _NOT_ built.
+#
+
+include: xilinx_zynq-testsuite.tcfg
diff --git a/bsps/arm/xilinx-zynq/config/xilinx_zynq_pynq.cfg 
b/bsps/arm/xilinx-zynq/config/xilinx_zynq_pynq.cfg
new file mode 100755
index 00..2de871d46e
--- /dev/null
+++ b/bsps/arm/xilinx-zynq/config/xilinx_zynq_pynq.cfg
@@ -0,0 +1 @@
+include $(RTEMS_ROOT)/make/custom/xilinx_zynq.inc
diff --git

[PATCH v3 rtems master 2/3] Fix zedboard clock settings

2023-11-21 Thread Bernd Moessner 
From: Bernd Moessner 

---
 spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml 
b/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml
index fdee4c0568..ad34974665 100644
--- a/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml
@@ -9,9 +9,8 @@ default:
 - enabled-by: 
   - arm/xilinx_zynq_zc702
   - arm/xilinx_zynq_zc706
+  - arm/xilinx_zynq_zedboard
   value: 3
-- enabled-by: arm/xilinx_zynq_zedboard
-  value: 7
 - enabled-by: true
   value: 1
 description: |
-- 
2.25.1

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[PATCH v3 rtems master 1/3] Fix add missing clock settings for zc706

2023-11-21 Thread Bernd Moessner 
From: Bernd Moessner 

---
 spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml 
b/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml
index 7233f73d5a..fdee4c0568 100644
--- a/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml
@@ -6,7 +6,9 @@ build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH & Co. KG
 default:
-- enabled-by: arm/xilinx_zynq_zc702
+- enabled-by: 
+  - arm/xilinx_zynq_zc702
+  - arm/xilinx_zynq_zc706
   value: 3
 - enabled-by: arm/xilinx_zynq_zedboard
   value: 7
-- 
2.25.1

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Coverity Scan Runs are Down

2023-11-21 Thread Joel Sherrill 
Hi

I got a message from the last Coverity Scan run that I need to update the
Scan tool used to run them.

With this being a short week (US Thanksgiving), I don't know if I will get
to it in the next couple of days.

--joel
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[PATCH rtems v2 2/3] bsp/imxrt1166: Support GPIO CS pins in LPSPI

2023-11-21 Thread Christian Mauderer 
With this, it is possible to use GPIOs as CS pins in the LPSPI. To avoid
additional complexity, the GPIOs will have the same limitations as the
native (hardware) CS pins.

The GPIO CS feature adds a number of extra code when starting SPI
transfers on this controller. Therefore it is possible to disable the
additional code by just setting the IMXRT_LPSPI_MAX_CS option to 0. In
that case only native CS pins are supported.

At the moment, this feature is only enabled on i.MXRT1166 by default
because it is not tested on i.MXRT1050. But it should work there too.
---
 bsps/arm/imxrt/spi/imxrt-lpspi.c| 244 ++--
 spec/build/bsps/arm/imxrt/grp.yml   |   2 +
 spec/build/bsps/arm/imxrt/optlpspimaxcs.yml |  21 ++
 3 files changed, 248 insertions(+), 19 deletions(-)
 create mode 100644 spec/build/bsps/arm/imxrt/optlpspimaxcs.yml

diff --git a/bsps/arm/imxrt/spi/imxrt-lpspi.c b/bsps/arm/imxrt/spi/imxrt-lpspi.c
index aed4f07f88..f23df73734 100644
--- a/bsps/arm/imxrt/spi/imxrt-lpspi.c
+++ b/bsps/arm/imxrt/spi/imxrt-lpspi.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -36,6 +37,10 @@
 #include 
 #include 
 
+#if IMXRT_LPSPI_MAX_CS != 0 && IMXRT_LPSPI_MAX_CS < 4
+#error IMXRT_LPSPI_MAX_CS hast to be either 0 or at least 4.
+#endif
+
 struct imxrt_lpspi_bus {
   spi_bus base;
   volatile LPSPI_Type *regs;
@@ -57,6 +62,19 @@ struct imxrt_lpspi_bus {
   const uint8_t *tx_buf;
 
   uint32_t fifo_size;
+
+#if IMXRT_LPSPI_MAX_CS != 0
+  struct {
+bool is_gpio;
+struct imx_gpio_pin gpio;
+uint32_t active;
+  } cs[IMXRT_LPSPI_MAX_CS];
+  /*
+   * dummy_cs is either <0 if no dummy exists or the index of the cs that is
+   * used as dummy.
+   */
+  int dummy_cs;
+#endif
 };
 
 static const uint32_t word_size = 8;
@@ -148,7 +166,15 @@ static void imxrt_lpspi_config(
 tcr |= LPSPI_TCR_LSBF_MASK;
   }
 
+#if IMXRT_LPSPI_MAX_CS > 0
+  if (bus->cs[msg->cs].is_gpio || (msg->mode & SPI_NO_CS) != 0) {
+tcr |= LPSPI_TCR_PCS(bus->dummy_cs);
+  } else {
+tcr |= LPSPI_TCR_PCS(msg->cs);
+  }
+#else
   tcr |= LPSPI_TCR_PCS(msg->cs);
+#endif
   tcr |= LPSPI_TCR_CONT_MASK;
   tcr |= LPSPI_TCR_FRAMESZ(word_size-1);
 
@@ -308,14 +334,33 @@ static inline int imxrt_lpspi_settings_ok(
 )
 {
   /* most of this is currently just not implemented */
-  if (msg->cs > 3 ||
-  msg->speed_hz > bus->base.max_speed_hz ||
+  if (msg->speed_hz > bus->base.max_speed_hz ||
   msg->delay_usecs != 0 ||
-  (msg->mode & ~(SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST)) != 0 ||
+  (msg->mode & ~(SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_NO_CS)) != 0 ||
   msg->bits_per_word != word_size) {
 return -EINVAL;
   }
 
+#if IMXRT_LPSPI_MAX_CS == 0
+  if (msg->cs > 3 || (msg->mode & SPI_NO_CS) != 0) {
+return -EINVAL;
+  }
+#else /* IMXRT_LPSPI_MAX_CS != 0 */
+  /*
+   * Chip select is a bit tricky. This depends on whether it's a native or a
+   * GPIO chip select.
+   */
+  if (msg->cs > IMXRT_LPSPI_MAX_CS) {
+return -EINVAL;
+  }
+  if (!bus->cs[msg->cs].is_gpio && msg->cs > 3) {
+return -EINVAL;
+  }
+  if ((msg->mode & SPI_NO_CS) != 0 && bus->dummy_cs < 0) {
+return -EINVAL;
+  }
+#endif
+
   if (prev_msg != NULL && !prev_msg->cs_change) {
 /*
  * A lot of settings have to be the same in this case because the upper 8
@@ -355,6 +400,10 @@ static int imxrt_lpspi_check_messages(
* Check whether cs_change is set on last message. Can't work without it
* because the last received data is only put into the FIFO if it is the end
* of a transfer or if another TX byte is put into the FIFO.
+   *
+   * In theory, a GPIO CS wouldn't need that limitation. But handling it
+   * different for the GPIO CS would add complexity. So keep it as a driver
+   * limitation for now.
*/
   if (!prev_msg->cs_change) {
 return -EINVAL;
@@ -363,6 +412,92 @@ static int imxrt_lpspi_check_messages(
   return 0;
 }
 
+#if IMXRT_LPSPI_MAX_CS > 0
+/*
+ * Check how many of the messages can be processed in one go. At the moment it
+ * is necessary to pause on CS changes when GPIO CS are used.
+ */
+static int imxrt_lpspi_check_howmany(
+  struct imxrt_lpspi_bus *bus,
+  const spi_ioc_transfer *msgs,
+  uint32_t max
+)
+{
+  int i;
+
+  if (max == 0) {
+return max;
+  }
+
+  for (i = 0; i < max - 1; ++i) {
+const spi_ioc_transfer *msg = [i];
+const spi_ioc_transfer *next_msg = [i+1];
+
+bool cs_is_gpio = bus->cs[msg->cs].is_gpio;
+bool no_cs = msg->mode & SPI_NO_CS;
+bool no_cs_next = next_msg->mode & SPI_NO_CS;
+
+if (cs_is_gpio && msg->cs_change) {
+  break;
+}
+
+if (no_cs != no_cs_next) {
+  break;
+}
+
+if (cs_is_gpio && (msg->cs != next_msg->cs)) {
+  break;
+}
+  }
+
+  return i+1;
+}
+#endif
+
+/*
+ * Transfer some messages. CS must not change between messages if GPIO CS are
+ * used.
+ */
+static void imxrt_lpspi_transfer_some(
+  struct imxrt_lpspi_bus *bus,
+  const

[PATCH rtems-docs v2] bsps/imxrt: Document GPIO CS pins for LPSPI

2023-11-21 Thread Christian Mauderer 
---
 user/bsps/arm/imxrt.rst | 28 
 1 file changed, 28 insertions(+)

diff --git a/user/bsps/arm/imxrt.rst b/user/bsps/arm/imxrt.rst
index ad18766..30b1437 100644
--- a/user/bsps/arm/imxrt.rst
+++ b/user/bsps/arm/imxrt.rst
@@ -198,10 +198,38 @@ Note that the SPI-pins on the evaluation board are shared 
with the SD card.
 Populate R278, R279, R280, R281 on the IMXRT1050-EVKB (Rev A) to use the SPI
 pins on the Arduino connector.
 
+By default, the native chip selects are used. If you want to use GPIOs as chip
+select instead, you can use the `cs-gpios` and `num-cs` attributes just like on
+a Linux SPI controller. A maximum of `IMXRT_LPSPI_MAX_CS` pins can be used.
+
+The hardware doesn't support selecting no native chip select during a transfer.
+Therefore one native chip select has to be reserved as a dummy if you want to 
be
+able to use GPIOs. The pin function for this chip select must not be configured
+on any pin. Dummy will be the first of the first four chip selects that is not 
a
+native one. Example configuration::
+
+   {
+status = "okay";
+pinctrl-0 = <_pinctrl_lpspi4>;
+cs-gpios = <0>, <0>, < 1 0>, <0>, < 5 1>;
+num-cs = <5>;
+  }
+
+In this case, CS2 will be the dummy chip select and no pin must be configured
+with that function. CS0, CS1 and CS3 are just native chip selects and should be
+used via pin functions. GPIO1.1 is used as a high active CS and GPIO11.5 a low
+active one.
+
 Limitations:
 
 * Only a basic SPI driver is implemented. This is mostly a driver limitation 
and
   not a hardware one.
+* GPIO CS pins on i.MXRT10xx are not tested. The chip has a lot of errate so
+  they might not work.
+* Switching from one mode (CPOL/CPHA) to another one can lead to single wrong
+  edges on the CLK line if GPIO CS pins are involved. Make sure to stuff a 
dummy
+  transfer with `SPI_NO_CS` set if you use multiple modes together with a GPIO
+  CS.
 
 Network Interface Driver
 
-- 
2.35.3

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[PATCH rtems v2 3/3] bsps/imxrt1166: Disable video_mux

2023-11-21 Thread Christian Mauderer 
The pinctrl-0 of the video_mux might overwrite pin settings done by
other peripherals. Disabling it by default prevents unexpected pin
settings.
---
 bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.c   | 10 ++
 bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.dts |  1 +
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.c 
b/bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.c
index 78e7feda09..e312902ff9 100644
--- a/bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.c
+++ b/bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.c
@@ -7,10 +7,10 @@
 #include 
 
 const unsigned char imxrt_dtb[] __attribute__(( __aligned__(8) )) = {
-  0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x70, 0xf2, 0x00, 0x00, 0x00, 0x38, 
-  0x00, 0x00, 0x6a, 0xa8, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11, 
+  0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x71, 0x0a, 0x00, 0x00, 0x00, 0x38, 
+  0x00, 0x00, 0x6a, 0xc0, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11, 
   0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x0a, 
-  0x00, 0x00, 0x6a, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x6a, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 
@@ -1836,7 +1836,9 @@ const unsigned char imxrt_dtb[] __attribute__(( 
__aligned__(8) )) = {
   0x40, 0x81, 0x80, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x03, 
   0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x04, 0xd2, 0x00, 0x00, 0x00, 0x5f, 
   0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
-  0x00, 0x00, 0x05, 0x02, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x02, 
+  0x00, 0x00, 0x05, 0x02, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x04, 0xb3, 0x64, 0x69, 0x73, 0x61, 
+  0x62, 0x6c, 0x65, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
   0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x61, 0x69, 0x70, 0x73, 
   0x2d, 0x62, 0x75, 0x73, 0x40, 0x34, 0x30, 0x63, 0x30, 0x30, 0x30, 0x30, 
   0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x18, 
diff --git a/bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.dts 
b/bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.dts
index c961abcd37..0cce861716 100644
--- a/bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.dts
+++ b/bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.dts
@@ -125,6 +125,7 @@
 
 _mux {
pinctrl-0 = <_video_mux>;
+   status = "disabled";
 };
 
  {
-- 
2.35.3

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[PATCHES v2] bsps/imxrt: Support GPIO CS for LPSPI; Minor fix for imxrt1166

2023-11-21 Thread Christian Mauderer 
Hello,

I noted some minor bugs in the first version of the patches while using
them. So here is a second version.

That are BSP specific patches and I now used the driver in this
configuration for some time and found no further problems. So if no one
objects, I will push the patches in a few days.

Best regards

Christian


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[PATCH rtems v2 1/3] bsps/imx*: imx_gpio from pointer to fdt property

2023-11-21 Thread Christian Mauderer 
Device trees allow mixing different kinds of GPIOs in one property. For
that it is usefull to only provide a pointer to an arbitrary location in
the property and initialize a GPIO from that.
---
 bsps/arm/include/bsp/imx-gpio.h | 26 
 bsps/arm/shared/pins/imx-gpio.c | 55 ++---
 2 files changed, 69 insertions(+), 12 deletions(-)

diff --git a/bsps/arm/include/bsp/imx-gpio.h b/bsps/arm/include/bsp/imx-gpio.h
index 148f62a56e..5cda22972f 100644
--- a/bsps/arm/include/bsp/imx-gpio.h
+++ b/bsps/arm/include/bsp/imx-gpio.h
@@ -76,6 +76,32 @@ struct imx_gpio_pin {
  */
 void imx_gpio_init (struct imx_gpio_pin *pin);
 
+/**
+ * Initialize a GPIO pin from the fields in an FDT property.
+ *
+ * If you have for example the following property in an FDT node:
+ *
+ * some-node {
+ * mixed-stuff = <0>, <_node 1>, < 22 GPIO_ACTIVE_LOW>, 
<17>;
+ * };
+ *
+ * You can get the property using fdt_getprop(...) in your code, somehow find
+ * the right start position (the phandle ) and then pass it to this
+ * function.
+ *
+ * If you pass something != NULL to @a next_prop_pointer, you will get a 
pointer
+ * to the next part in the attribute. In the example above, that will be a
+ * pointer to the <17>.
+ *
+ * NOTE: The information from the third parameter in the FDT (GPIO_ACTIVE_LOW 
in
+ * the example) is currently ignored.
+ */
+rtems_status_code imx_gpio_init_from_fdt_property_pointer(
+  struct imx_gpio_pin *pin,
+  const uint32_t *prop_pointer,
+  enum imx_gpio_mode mode,
+  const uint32_t **next_prop_pointer);
+
 /**
  * Initialize a GPIO pin from a FDT property.
  *
diff --git a/bsps/arm/shared/pins/imx-gpio.c b/bsps/arm/shared/pins/imx-gpio.c
index 8b7d09e864..1e39822b93 100644
--- a/bsps/arm/shared/pins/imx-gpio.c
+++ b/bsps/arm/shared/pins/imx-gpio.c
@@ -191,12 +191,11 @@ static void imx_gpio_set_interrupt_mode(struct 
imx_gpio_pin *pin, uint32_t mode)
   }
 }
 
-rtems_status_code imx_gpio_init_from_fdt_property (
+rtems_status_code imx_gpio_init_from_fdt_property_pointer (
   struct imx_gpio_pin *pin,
-  int node_offset,
-  const char *property,
+  const uint32_t *prop_pointer,
   enum imx_gpio_mode mode,
-  size_t index
+  const uint32_t **next_prop_pointer
 )
 {
   int len;
@@ -205,7 +204,6 @@ rtems_status_code imx_gpio_init_from_fdt_property (
   const void *fdt;
   uint32_t gpio_regs;
   const unsigned pin_length_dwords = 3;
-  const unsigned pin_length_bytes = (pin_length_dwords * sizeof(uint32_t));
   uint32_t gpio_phandle;
   uint32_t pin_nr;
   int cfgnode;
@@ -213,16 +211,12 @@ rtems_status_code imx_gpio_init_from_fdt_property (
   memset(pin, 0, sizeof(*pin));
 
   fdt = bsp_fdt_get();
-  val = fdt_getprop(fdt, node_offset, property, );
-  if (val == NULL || (len % pin_length_bytes != 0) ||
-  (index >= len / pin_length_bytes)) {
-sc = RTEMS_UNSATISFIED;
-  }
   if (sc == RTEMS_SUCCESSFUL) {
-pin_nr = fdt32_to_cpu(val[1 + index * pin_length_dwords]);
-gpio_phandle = fdt32_to_cpu(val[0 + index * pin_length_dwords]);
+pin_nr = fdt32_to_cpu(prop_pointer[1]);
+gpio_phandle = fdt32_to_cpu(prop_pointer[0]);
 
 cfgnode = fdt_node_offset_by_phandle(fdt, gpio_phandle);
+/* FIXME: Check compatible strings here. */
 val = fdt_getprop(fdt, cfgnode, "reg", );
 if (len > 0) {
   gpio_regs = fdt32_to_cpu(val[0]);
@@ -239,6 +233,43 @@ rtems_status_code imx_gpio_init_from_fdt_property (
   if (sc == RTEMS_SUCCESSFUL) {
 imx_gpio_init(pin);
   }
+  if (sc == RTEMS_SUCCESSFUL && next_prop_pointer != NULL) {
+*next_prop_pointer = prop_pointer + pin_length_dwords;
+  }
+
+  return sc;
+}
+
+rtems_status_code imx_gpio_init_from_fdt_property (
+  struct imx_gpio_pin *pin,
+  int node_offset,
+  const char *property,
+  enum imx_gpio_mode mode,
+  size_t index
+)
+{
+  int len;
+  const uint32_t *val;
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+  const void *fdt;
+  const unsigned pin_length_dwords = 3;
+  const unsigned pin_length_bytes = pin_length_dwords * 4;
+
+  memset(pin, 0, sizeof(*pin));
+
+  fdt = bsp_fdt_get();
+  val = fdt_getprop(fdt, node_offset, property, );
+  if (val == NULL || (len % pin_length_bytes != 0) ||
+  (index >= len / pin_length_bytes)) {
+sc = RTEMS_UNSATISFIED;
+  }
+  if (sc == RTEMS_SUCCESSFUL) {
+sc = imx_gpio_init_from_fdt_property_pointer(
+  pin,
+  val + index * pin_length_dwords,
+  mode,
+  NULL);
+  }
 
   return sc;
 }
-- 
2.35.3

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Re: [PATCH] build: Add RTEMS_QUALIFIED

2023-11-21 Thread Sebastian Huber 

On 13.11.23 22:16, Chris Johns wrote:

On 10/11/2023 7:39 pm, Sebastian Huber wrote:

On 09.11.23 06:28, Chris Johns wrote:

On 8/11/2023 6:44 pm, Sebastian Huber wrote:

On 06.11.23 21:55, Chris Johns wrote:

On 6/11/2023 8:27 pm, Sebastian Huber wrote:

On 06.11.23 01:14, Chris Johns wrote:

On 4/11/2023 1:31 am, Sebastian Huber wrote:

On 03.11.23 15:08, Joel Sherrill wrote:

On Fri, Nov 3, 2023 at 3:58 AM Sebastian Huber
mailto:sebastian.hu...@embedded-brains.de>> wrote:

    The goal of the RTEMS pre-qualification activity #3701 is a
specified
    and validated subset of RTEMS.  For users of the pre-qualified
subset of
    RTEMS it is important to not accidentally use not pre-qualified
    features.  One way to achieve this, is to build only the sources
of the
    pre-qualified feature set. This customized build is enabled by
the new
    build configuration option RTEMS_QUALIFIED.  If it is enabled, then
only
    the pre-qualified subset of RTEMS is built and installed.

    Building with RTEMS_QUALIFIED enable is currently only supported for
the
    sparc/leon3 BSP family.  To support an RTEMS_QUALIFIED enabled
build,
    changes in the CPU port and the BSP are required to only use
features of
    the pre-qualified feature set.


Where is this documented?

You mean a documentation of what needs to be done to create pre-qualified
BSP? I
don't have it available yet. A good place to add this would be the how-to
section in the RTEMS Software Engineering manual.


This is a very large patch. Are you assuming that if "not qualified" is
specified,
then it is in the qualified set?

No, the logic is reversed. Everything is built by default. Some parts are
only
enabled if RTEMS_QUALIFIED is not enabled, for example
(spec/build/cpukit/objextra.yml):

enabled-by:
  not: RTEMS_QUALIFIED

It seems counter intuitive to me. I have no idea about qual work but my
limited
understanding is everything is controlled yet this is the inverse of that and
anything anyone adds will by default be qualified?

The goal of this patch set is to place each source and header file of RTEMS
into
two buckets, the pre-qualified bucket and the extra bucket. For two buckets
you
need just one option with two values. In the current patch it is
RTEMS_QUALIFIED
enabled or disabled.

I think we should also include in our discussion code contained within this
define (or defines) in shared files and how we manage changes to that code? In
an ideal world we would not have any need for conditional code however I
appreciate this may not be possible or initial achievable. We should however
look for approaches that try to avoid this and understand the constraints the
define brings. For example can I change code in a qualification or FACE define
when I do not know the standards they support?

We should avoid using the C preprocessor for the profile customization. For the
ECSS pre-qualification, there was no need to do this (with the exception of
testbeginend.c, but this could be changed).

+1


Since Joel already brought the FACE profile into play, an alternative could be
this approach. Lets assume that we pre-qualified the FACE profile
interfaces of
RTEMS. Use RTEMS_EVERYTHING for the I want everything profile. Use
RTEMS_QUALIFIED for the pre-qualified profile. Use RTEMS_FACE_PROFILE for
interfaces of the FACE profile.

If these are profiles I suggest RTEMS_PROFILE_EVERYTHING so RTEMS_PROFILE_.*
can
find all profiles?

Yes, this make sense.


The objects which are not pre-qualified would use this:

enabled-by: RTEMS_EVERYTHING

RTEMS_PROFILE_COMMERCIAL ?
RTEMS_PROFILE_INDUSTRIAL ?
RTEMS_PROFILE_RTEMS ?

... or something that reflects what we have always shipped? I borrowed those
labels from the way parts are classed. I tend to keep away from labels like
new,
next, everything etc because they quickly date.


The objects which are pre-qualified would use this:

enabled-by:
- RTEMS_EVERYTHING
- RTEMS_QUALIFIED

Qualified to what? RTEMS_PROFILE_FACE defines something useful and concrete. Is
there an equivalent we could use for the work you have been doing?

The selection of the feature set for the ECSS pre-qualification was based on a
survey:

https://ftp.rtems.org/pub/rtems/people/sebh/rtems-smp-userconsultation-27032019-release.pdf

https://ftp.rtems.org/pub/rtems/people/sebh/tn-space-profile-r6-23062019.pdf


RTEMS_PROFILE_SPACE ? I just used the name on page 1 of this document.

The profile in the patch set is by no means limited to the European space
industry. We need a name for the subset of RTEMS which fulfills the 4 rules
below. This subset may grow over time and include for example the POSIX threads
API. We already have plans to work on this.

Yes I agree the set of files covered is not limited to the EU space program
however I am confused by a qualification file set that is not explicitly defined
for a specific profile. Are you able to define a suitable subset for all
possible profiles? Maybe I do

Re: [PATCH] build: Add RTEMS_QUALIFIED

2023-11-21 Thread Christian MAUDERER 

On 2023-11-13 22:16, Chris Johns wrote:

On 10/11/2023 7:39 pm, Sebastian Huber wrote:

On 09.11.23 06:28, Chris Johns wrote:

On 8/11/2023 6:44 pm, Sebastian Huber wrote:

On 06.11.23 21:55, Chris Johns wrote:

On 6/11/2023 8:27 pm, Sebastian Huber wrote:

On 06.11.23 01:14, Chris Johns wrote:

On 4/11/2023 1:31 am, Sebastian Huber wrote:

On 03.11.23 15:08, Joel Sherrill wrote:

On Fri, Nov 3, 2023 at 3:58 AM Sebastian Huber
mailto:sebastian.hu...@embedded-brains.de>> wrote:

    The goal of the RTEMS pre-qualification activity #3701 is a
specified
    and validated subset of RTEMS.  For users of the pre-qualified
subset of
    RTEMS it is important to not accidentally use not pre-qualified
    features.  One way to achieve this, is to build only the sources
of the
    pre-qualified feature set. This customized build is enabled by
the new
    build configuration option RTEMS_QUALIFIED.  If it is enabled, then
only
    the pre-qualified subset of RTEMS is built and installed.

    Building with RTEMS_QUALIFIED enable is currently only supported for
the
    sparc/leon3 BSP family.  To support an RTEMS_QUALIFIED enabled
build,
    changes in the CPU port and the BSP are required to only use
features of
    the pre-qualified feature set.


Where is this documented?

You mean a documentation of what needs to be done to create pre-qualified
BSP? I
don't have it available yet. A good place to add this would be the how-to
section in the RTEMS Software Engineering manual.


This is a very large patch. Are you assuming that if "not qualified" is
specified,
then it is in the qualified set?

No, the logic is reversed. Everything is built by default. Some parts are
only
enabled if RTEMS_QUALIFIED is not enabled, for example
(spec/build/cpukit/objextra.yml):

enabled-by:
  not: RTEMS_QUALIFIED

It seems counter intuitive to me. I have no idea about qual work but my
limited
understanding is everything is controlled yet this is the inverse of that and
anything anyone adds will by default be qualified?


The goal of this patch set is to place each source and header file of RTEMS
into
two buckets, the pre-qualified bucket and the extra bucket. For two buckets
you
need just one option with two values. In the current patch it is
RTEMS_QUALIFIED
enabled or disabled.


I think we should also include in our discussion code contained within this
define (or defines) in shared files and how we manage changes to that code? In
an ideal world we would not have any need for conditional code however I
appreciate this may not be possible or initial achievable. We should however
look for approaches that try to avoid this and understand the constraints the
define brings. For example can I change code in a qualification or FACE define
when I do not know the standards they support?


We should avoid using the C preprocessor for the profile customization. For the
ECSS pre-qualification, there was no need to do this (with the exception of
testbeginend.c, but this could be changed).


+1


Since Joel already brought the FACE profile into play, an alternative could be
this approach. Lets assume that we pre-qualified the FACE profile
interfaces of
RTEMS. Use RTEMS_EVERYTHING for the I want everything profile. Use
RTEMS_QUALIFIED for the pre-qualified profile. Use RTEMS_FACE_PROFILE for
interfaces of the FACE profile.


If these are profiles I suggest RTEMS_PROFILE_EVERYTHING so RTEMS_PROFILE_.*
can
find all profiles?


Yes, this make sense.




The objects which are not pre-qualified would use this:

enabled-by: RTEMS_EVERYTHING


RTEMS_PROFILE_COMMERCIAL ?
RTEMS_PROFILE_INDUSTRIAL ?
RTEMS_PROFILE_RTEMS ?

... or something that reflects what we have always shipped? I borrowed those
labels from the way parts are classed. I tend to keep away from labels like
new,
next, everything etc because they quickly date.



The objects which are pre-qualified would use this:

enabled-by:
- RTEMS_EVERYTHING
- RTEMS_QUALIFIED


Qualified to what? RTEMS_PROFILE_FACE defines something useful and concrete. Is
there an equivalent we could use for the work you have been doing?


The selection of the feature set for the ECSS pre-qualification was based on a
survey:

https://ftp.rtems.org/pub/rtems/people/sebh/rtems-smp-userconsultation-27032019-release.pdf

https://ftp.rtems.org/pub/rtems/people/sebh/tn-space-profile-r6-23062019.pdf



RTEMS_PROFILE_SPACE ? I just used the name on page 1 of this document.


The profile in the patch set is by no means limited to the European space
industry. We need a name for the subset of RTEMS which fulfills the 4 rules
below. This subset may grow over time and include for example the POSIX threads
API. We already have plans to work on this.


Yes I agree the set of files covered is not limited to the EU space program
however I am confused by a qualification file set that is not explicitly defined
for a specific profile. Are you able to define a suitable subset for all
possible

[RSB 1/3] 6/7: Update Newlib

2023-11-21 Thread Sebastian Huber 
Pick up fixes for ARM/optimized-routines and the memory reclamation at thread
exit.

Update #4510.
Update #4967.
---
 rtems/config/tools/rtems-gcc-10-newlib-head.cfg   | 4 ++--
 rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg | 4 ++--
 rtems/config/tools/rtems-gcc-12-newlib-head.cfg   | 4 ++--
 rtems/config/tools/rtems-gcc-13-newlib-head.cfg   | 4 ++--
 rtems/config/tools/rtems-gcc-13.2-newlib-head.cfg | 4 ++--
 rtems/config/tools/rtems-gcc-head-newlib-head.cfg | 4 ++--
 6 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/rtems/config/tools/rtems-gcc-10-newlib-head.cfg 
b/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
index 6668bc6..387e8c9 100644
--- a/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
+++ b/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
@@ -14,12 +14,12 @@
 %patch add gcc -p1 
https://devel.rtems.org/raw-attachment/ticket/4215/0001-nios2-Remove-custom-instruction-warnings.patch
 %hash sha512 0001-nios2-Remove-custom-instruction-warnings.patch 
afd8a5e6bdcc5b75d5fbbf558bdf56ccac400521a6eec9d88cc95f6be67c481f2dbf8faa0f6ddc1e4ac7c56a84938714d80e46e9cf80ec4b8fcd739986449881
 
-%define newlib_version fbc5496
+%define newlib_version 3cacedb
 %define newlib_external 1
 %define newlib_expand_name sourceware-mirror-newlib-cygwin-%{newlib_version}
 %source set newlib --rsb-file=newlib-%{newlib_version}.tar.gz 
https://codeload.github.com/RTEMS/sourceware-mirror-newlib-cygwin/tar.gz/%{newlib_version}
 %hash sha512 newlib-%{newlib_version}.tar.gz \
-  
AFwyCjHHXfddx/lUcJbmcxSFOYtfj8cshzthqF9B2OtZxxxN/NQ8O+znhUPKDv20KjOBEMGh4VHpoiFBjZOrmA==
+  
ia0ce+bdENUO3qYj00jrZB8FjSejmTWuRqEdNE8nI2llf30mh8leUn5fCoHB0Oa7rRVBjEu3n0F12ZK9skuegQ==
 
 %define with_threads 1
 %define with_plugin 0
diff --git a/rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg 
b/rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg
index dae3d2a..b37af1e 100644
--- a/rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg
+++ b/rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg
@@ -17,12 +17,12 @@
 %patch add gcc -p1 
https://devel.rtems.org/raw-attachment/ticket/4215/0001-nios2-Remove-custom-instruction-warnings.patch
 %hash sha512 0001-nios2-Remove-custom-instruction-warnings.patch 
afd8a5e6bdcc5b75d5fbbf558bdf56ccac400521a6eec9d88cc95f6be67c481f2dbf8faa0f6ddc1e4ac7c56a84938714d80e46e9cf80ec4b8fcd739986449881
 
-%define newlib_version fbc5496
+%define newlib_version 3cacedb
 %define newlib_external 1
 %define newlib_expand_name sourceware-mirror-newlib-cygwin-%{newlib_version}
 %source set newlib --rsb-file=newlib-%{newlib_version}.tar.gz 
https://codeload.github.com/RTEMS/sourceware-mirror-newlib-cygwin/tar.gz/%{newlib_version}
 %hash sha512 newlib-%{newlib_version}.tar.gz \
-  
AFwyCjHHXfddx/lUcJbmcxSFOYtfj8cshzthqF9B2OtZxxxN/NQ8O+znhUPKDv20KjOBEMGh4VHpoiFBjZOrmA==
+  
ia0ce+bdENUO3qYj00jrZB8FjSejmTWuRqEdNE8nI2llf30mh8leUn5fCoHB0Oa7rRVBjEu3n0F12ZK9skuegQ==
 
 %define with_threads 1
 %define with_plugin 0
diff --git a/rtems/config/tools/rtems-gcc-12-newlib-head.cfg 
b/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
index 9fe1ddd..4a0c6d1 100644
--- a/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
+++ b/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
@@ -34,13 +34,13 @@
 
KEmxHjYOqY4LTXCMZ3I60tbHusbR5GlnP0CLARHPAnhCnovDj9K3U43C1bsMxDDGRqD6fwtrEFoEgqVFX63IuQ==
 # Comment above related to #4657 and patches ends here
 
-%define newlib_version fbc5496
+%define newlib_version 3cacedb
 %define newlib_external 1
 %define newlib_expand_name sourceware-mirror-newlib-cygwin-%{newlib_version}
 %source set newlib --rsb-file=newlib-%{newlib_version}.tar.gz \

https://codeload.github.com/RTEMS/sourceware-mirror-newlib-cygwin/tar.gz/%{newlib_version}
 %hash sha512 newlib-%{newlib_version}.tar.gz \
-  
AFwyCjHHXfddx/lUcJbmcxSFOYtfj8cshzthqF9B2OtZxxxN/NQ8O+znhUPKDv20KjOBEMGh4VHpoiFBjZOrmA==
+  
ia0ce+bdENUO3qYj00jrZB8FjSejmTWuRqEdNE8nI2llf30mh8leUn5fCoHB0Oa7rRVBjEu3n0F12ZK9skuegQ==
 
 %define with_threads 1
 %define with_plugin 0
diff --git a/rtems/config/tools/rtems-gcc-13-newlib-head.cfg 
b/rtems/config/tools/rtems-gcc-13-newlib-head.cfg
index 7d5f610..5529563 100644
--- a/rtems/config/tools/rtems-gcc-13-newlib-head.cfg
+++ b/rtems/config/tools/rtems-gcc-13-newlib-head.cfg
@@ -8,12 +8,12 @@
 %hash sha512 %{gcc_expand_name}.tar.gz \
   
nKBXN9Qt/9CRYDVOp1geQdshXDP/kvr82RV1fE1LVIxNCbAVvhRmqz1p5kycg24T3TNGHPN58RySceaYgc6sCw==
 
-%define newlib_version fbc5496
+%define newlib_version 3cacedb
 %define newlib_external 1
 %define newlib_expand_name sourceware-mirror-newlib-cygwin-%{newlib_version}
 %source set newlib --rsb-file=newlib-%{newlib_version}.tar.gz 
https://codeload.github.com/RTEMS/sourceware-mirror-newlib-cygwin/tar.gz/%{newlib_version}
 %hash sha512 newlib-%{newlib_version}.tar.gz \
-  
AFwyCjHHXfddx/lUcJbmcxSFOYtfj8cshzthqF9B2OtZxxxN/NQ8O+znhUPKDv20KjOBEMGh4VHpoiFBjZOrmA==
+  
ia0ce+bdENUO3qYj00jrZB8FjSejmTWuRqEdNE8nI2llf30mh8leUn5fCoHB0Oa7rRVBjEu3n0F12ZK9skuegQ==
 
 %define with_threads 1
 %define with_plugin 0

[RSB 2/3] 6: Update GCC 12 and 13

2023-11-21 Thread Sebastian Huber 
Keep RTEMS up to date with the upstream development.
---
 rtems/config/tools/rtems-gcc-12-newlib-head.cfg | 4 ++--
 rtems/config/tools/rtems-gcc-13-newlib-head.cfg | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/rtems/config/tools/rtems-gcc-12-newlib-head.cfg 
b/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
index 4a0c6d1..4a31a50 100644
--- a/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
+++ b/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
@@ -1,12 +1,12 @@
 %include %{_configdir}/checks.cfg
 %include %{_configdir}/base.cfg
 
-%define gcc_version 814ec21
+%define gcc_version a285310
 %define gcc_external 1
 %define gcc_expand_name gnu-mirror-gcc-%{gcc_version}
 %source set gcc --rsb-file=%{gcc_expand_name}.tar.gz 
https://codeload.github.com/RTEMS/gnu-mirror-gcc/tar.gz/%{gcc_version}
 %hash sha512 %{gcc_expand_name}.tar.gz \
-  
JyGpbsqRctCanDzH/sHmem+iJMXvQe2x8ZairztM034/vcElNQSMNgb2jICgdDWH032wrJOk5IYcZoA0fJx4Zw==
+  
sYxUkDJD7qaCzXndAljnAQMbmssg7AY97cBAMjwqDSC6vxseGSzvO8LGMW46ASM6Zq2frKj8XVj27GnPmwSIXQ==
 
 %patch add gcc -p1 
https://devel.rtems.org/raw-attachment/ticket/4196/0001-Back-port-v1-of-gcov-tool-merge-stream-to-GCC-12.patch
 %hash sha512 0001-Back-port-v1-of-gcov-tool-merge-stream-to-GCC-12.patch \
diff --git a/rtems/config/tools/rtems-gcc-13-newlib-head.cfg 
b/rtems/config/tools/rtems-gcc-13-newlib-head.cfg
index 5529563..efd546b 100644
--- a/rtems/config/tools/rtems-gcc-13-newlib-head.cfg
+++ b/rtems/config/tools/rtems-gcc-13-newlib-head.cfg
@@ -1,12 +1,12 @@
 %include %{_configdir}/checks.cfg
 %include %{_configdir}/base.cfg
 
-%define gcc_version f37fae5
+%define gcc_version 8c04837
 %define gcc_external 1
 %define gcc_expand_name gnu-mirror-gcc-%{gcc_version}
 %source set gcc --rsb-file=%{gcc_expand_name}.tar.gz 
https://codeload.github.com/RTEMS/gnu-mirror-gcc/tar.gz/%{gcc_version}
 %hash sha512 %{gcc_expand_name}.tar.gz \
-  
nKBXN9Qt/9CRYDVOp1geQdshXDP/kvr82RV1fE1LVIxNCbAVvhRmqz1p5kycg24T3TNGHPN58RySceaYgc6sCw==
+  
YSkX/JY61N+I4CPkJInUNGzwhb+uv+YNs9qcTxxJhg/HpGD5vI9duEPNw++F3y8J4re87DPJGIzV5DsFUBCJnA==
 
 %define newlib_version 3cacedb
 %define newlib_external 1
-- 
2.35.3

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[RSB 3/3] 7: Update Binutils, GDB, and GCC

2023-11-21 Thread Sebastian Huber 
Keep RTEMS up to date with the upstream development.
---
 rtems/config/tools/rtems-binutils-head.cfg| 4 ++--
 rtems/config/tools/rtems-gcc-head-newlib-head.cfg | 4 ++--
 rtems/config/tools/rtems-gdb-head.cfg | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/rtems/config/tools/rtems-binutils-head.cfg 
b/rtems/config/tools/rtems-binutils-head.cfg
index 3c38aae..3516d2c 100644
--- a/rtems/config/tools/rtems-binutils-head.cfg
+++ b/rtems/config/tools/rtems-binutils-head.cfg
@@ -1,12 +1,12 @@
 %include %{_configdir}/checks.cfg
 %include %{_configdir}/base.cfg
 
-%define binutils_version 29736fc
+%define binutils_version eb42bb1
 %define binutils_external 1
 %define binutils_expand_name sourceware-mirror-binutils-gdb-%{binutils_version}
 %source set binutils --rsb-file=%{binutils_expand_name}.tar.gz 
https://codeload.github.com/RTEMS/sourceware-mirror-binutils-gdb/tar.gz/%{binutils_version}
 %hash sha512 %{binutils_expand_name}.tar.gz \
-  
REf+CTG4FMoi5tVGd+ec1a2sexHCn6rNGWM7MjBIeOGKQvat/2GYXolOyIEDoITiCZSENAqwbzyc1fS3/3ndVA==
+  
qDuLOqwQ/kQX30hIu5UVDqMuKjnpoKTEZ4xo85lrzq6VtnCd6nwdO5t9szbhJc4P1UWww9rRNMcqj7d2BKeNqg==
 
 %define with_deterministic_archives 1
 %define with_64_bit_bfd 1
diff --git a/rtems/config/tools/rtems-gcc-head-newlib-head.cfg 
b/rtems/config/tools/rtems-gcc-head-newlib-head.cfg
index c65576e..c4f2aa3 100644
--- a/rtems/config/tools/rtems-gcc-head-newlib-head.cfg
+++ b/rtems/config/tools/rtems-gcc-head-newlib-head.cfg
@@ -1,12 +1,12 @@
 %include %{_configdir}/checks.cfg
 %include %{_configdir}/base.cfg
 
-%define gcc_version af4bb22
+%define gcc_version 41aacde
 %define gcc_external 1
 %define gcc_expand_name gnu-mirror-gcc-%{gcc_version}
 %source set gcc --rsb-file=%{gcc_expand_name}.tar.gz 
https://codeload.github.com/RTEMS/gnu-mirror-gcc/tar.gz/%{gcc_version}
 %hash sha512 %{gcc_expand_name}.tar.gz \
-  
/xNCazIZxy7diP2R1RUChqhEuQIZdD4otPeHyN48g1LiFbgPaUNZ167RDPCXkQEVVf31g/LvYFqicxeXMwj8cQ==
+  
xPwSCLLXsJfFKontgrGlU9ep/PVlP3bQOGbgRCG0mj8sD5dq2ifo5VOwGwVMRQD0VFVVOWqeykq3OVkZYlu1GA==
 
 %define newlib_version 3cacedb
 %define newlib_external 1
diff --git a/rtems/config/tools/rtems-gdb-head.cfg 
b/rtems/config/tools/rtems-gdb-head.cfg
index 2bda4fb..17ecee8 100644
--- a/rtems/config/tools/rtems-gdb-head.cfg
+++ b/rtems/config/tools/rtems-gdb-head.cfg
@@ -1,11 +1,11 @@
 %include %{_configdir}/checks.cfg
 %include %{_configdir}/base.cfg
 
-%define gdb_version 29736fc
+%define gdb_version eb42bb1
 %define gdb_external 1
 %define gdb_expand_name sourceware-mirror-binutils-gdb-%{gdb_version}
 %source set gdb --rsb-file=%{gdb_expand_name}.tar.gz 
https://codeload.github.com/RTEMS/sourceware-mirror-binutils-gdb/tar.gz/%{gdb_version}
 %hash sha512 %{gdb_expand_name}.tar.gz \
-  
REf+CTG4FMoi5tVGd+ec1a2sexHCn6rNGWM7MjBIeOGKQvat/2GYXolOyIEDoITiCZSENAqwbzyc1fS3/3ndVA==
+  
qDuLOqwQ/kQX30hIu5UVDqMuKjnpoKTEZ4xo85lrzq6VtnCd6nwdO5t9szbhJc4P1UWww9rRNMcqj7d2BKeNqg==
 
 %include %{_configdir}/gdb-8-1.cfg
-- 
2.35.3

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Re: [PATCH rtems v2] once.c, onceimplh.h: Make synchronization variable volatile

2023-11-21 Thread Sebastian Huber 

On 20.11.23 18:42, Joel Sherrill wrote:

The loop that waits for another thread to complete the once
initialization was flagged as a potential infinite loop.
This is because there was no way to break out of the loop
inside the loop.  The solution is to make the state variable
volatile which indicates it may be modified by another thread
of execution.

This was flagged by a user Coverity Scan run which apparently is
configured differently from the instance provided by Coverity to
open source projects.


This is a configuration issue of Coverity Scan. You have to teach 
Coverity Scan something about:


_Atomic_Fence( ATOMIC_ORDER_ACQUIRE );
_Atomic_Fence( ATOMIC_ORDER_RELEASE );

rtems_mutex_lock();
rtems_condition_variable_wait();
rtems_mutex_unlock();

Using "volatile" for multi-threaded synchronization is not correct in 
C11 or later. This keyword is for device access. For multi-threaded 
synchronization you need atomic operations or mutexes, etc. From my 
point of view, Coverity Scan should warn if you use volatile for 
multi-threaded synchronization.


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Re: [PATCH] 6: Use Binutils 2.41

2023-11-21 Thread Sebastian Huber 

On 03.08.23 09:37, Sebastian Huber wrote:

What about this patch and the GCC update to 13.2?


Ping.

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Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

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Re: [PATCH] 6: Use GCC 13.2

2023-11-21 Thread Sebastian Huber 

On 12.09.23 08:43, Sebastian Huber wrote:



On 12.09.23 08:40, Chris Johns wrote:

On 12/9/2023 4:31 pm, Sebastian Huber wrote:

On 27.07.23 13:33, Sebastian Huber wrote:

Prepare for RTEMS 6.1 release.

Update #4921.

How do we want to proceed with the tools for the RTEMS 6.1 release?
I need to move 6 to tar files but other tickets have taken what time I 
had.


The patch uses a tar file for GCC. I guess for Newlib we have to host an 
archive.





Is GCC 13.2 still the desired GCC release?

What is the alternative?


Do we need one? GCC 13.2 is the best option from my point of view right 
now.


Can I check in the update to GCC 13.2?

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email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

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