Adds functions to request cache operations on a set of cores.
Daniel Cederman (3):
score: Use consistent type for SMP messages
score: Add function to send a SMP message to a set of CPUs
score: Add SMP support to the cache manager
c/src/lib/libcpu/shared/src/cache_manager.c | 166
Adds functions that allows the user to specify which cores that should
perform the cache operation. SMP messages are sent to all the specified
cores and the caller waits until all cores have acknowledged that they
have flushed their cache. Implementation is shown using both function
pointers and
Check that data cache snooping exists and is enabled on all cores.
---
c/src/lib/libbsp/shared/include/fatal.h |1 +
c/src/lib/libbsp/sparc/leon3/include/leon.h | 10 ++
c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c |8 ++--
3 files changed, 17 insertions(+), 2
The flush instruction on LEON flushes both the data and the instruction
cache. Flushing of just the instruction cache can be done by setting
the flush instruction cache bit in the cache control register.
---
c/src/lib/libbsp/sparc/leon3/include/cache_.h |4 +++-
On 2014-07-09 16:40, Gedare Bloom wrote:
On Wed, Jul 9, 2014 at 3:02 AM, Daniel Cederman ceder...@gaisler.com wrote:
The flush instruction on LEON flushes both the data and the instruction
cache. Flushing of just the instruction cache can be done by setting
the flush instruction cache bit
+BSP_fatal_exit(
LEON3_FATAL_INVALID_CACHE_CONFIG_SECONDARY_PROCESSOR );
bsp_fatal()?
I wanted to use bsp_fatal, but it tries to acquire a ticket lock which
does not work when data cache snooping is disabled.
On 2014-07-09 09:28, Sebastian Huber wrote:
On 2014-07-09 09:02, Daniel
I'm currently working on adding tests. Thank you for your other comments!
On 2014-07-09 09:41, Sebastian Huber wrote:
The new cache manager functions should have tests, see also
http://git.rtems.org/rtems/tree/testsuites/sptests/spcache01/init.c
On 2014-07-09 09:02, Daniel Cederman wrote
Check that data cache snooping exists and is enabled on all cores.
---
c/src/lib/libbsp/shared/include/fatal.h |2 ++
c/src/lib/libbsp/sparc/leon3/include/leon.h | 10 ++
c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c | 14 --
3 files changed, 24 insertions(+),
Invokes SMP cache management routines under different scenarios.
---
testsuites/smptests/Makefile.am |1 +
testsuites/smptests/configure.ac |1 +
testsuites/smptests/smpcache01/Makefile.am| 19 ++
testsuites/smptests/smpcache01/init.c | 291
Looks like this function needs a guard on #if
defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
Yes, looks like I missed that. I will send a patch.
Daniel C
On 2014-08-22 16:38, Gedare Bloom wrote:
Looks like this function needs a guard on #if
defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
see
---
c/src/lib/libcpu/shared/src/cache_manager.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c
b/c/src/lib/libcpu/shared/src/cache_manager.c
index 7dd408f..7ff1166 100644
--- a/c/src/lib/libcpu/shared/src/cache_manager.c
+++
---
cpukit/score/cpu/sparc/rtems/score/cpu.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h
b/cpukit/score/cpu/sparc/rtems/score/cpu.h
index 9c38b55..d4c2ef0 100644
--- a/cpukit/score/cpu/sparc/rtems/score/cpu.h
+++
---
testsuites/smptests/smpcache01/init.c | 29 ++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/testsuites/smptests/smpcache01/init.c
b/testsuites/smptests/smpcache01/init.c
index dd2f9f1..48154d4 100644
--- a/testsuites/smptests/smpcache01/init.c
+++
Invalidation of data cache lines might cause data written to the stack
to get lost.
---
testsuites/smptests/smpcache01/init.c | 45 +++
testsuites/smptests/smpcache01/smpcache01.doc | 2 --
testsuites/smptests/smpcache01/smpcache01.scn | 18 ---
3 files
Invalidation of entire data cache might cause data written to the stack
to get lost.
---
testsuites/smptests/smpcache01/init.c | 47 +++
testsuites/smptests/smpcache01/smpcache01.doc | 1 -
testsuites/smptests/smpcache01/smpcache01.scn | 18 --
3 files
Hi,
I would like to add a way for the user of the leon3 bsp to specify the
irq that should be used for IPIs. Is it adding an option to
configure.ac for the bsp that is the recommended way? Or does there
exist a supported way of setting bsp specific parameters similar to how
it is done with
On 2014-09-30 16:45, Sebastian Huber wrote:
If you need a link time option, then there is no standard way to do this
on the BSP level. Most BSPs use some sort of weak tables or functions.
The LEON3 BSP already uses such a thing for debug_uart_index for
example.
Ok, then I'll do something
The LEON3_MP_IRQ define is used to pick the IRQ to be used by the
shared memory driver and for inter-processor interrupts. On some LEON3
systems, for example the GR712RC, the default value of 14 is not suitable.
To make this value configurable from the application, it is replaced with
a weakly
Hi,
I'm looking at GCC's libatomic, which provides software emulation of
atomic operations that are not supported by hardware. It does this by
using a compare-and-swap loop, or, failing that, using locks. At the
moment it is not selected for compilation for RTEMS since it requires
operating
to get an undefined reference error and make a custom
solution than to add locks indirectly. So I will put this on hold.
On 2014-10-02 07:50, Sebastian Huber wrote:
On 01/10/14 16:20, Daniel Cederman wrote:
I'm looking at GCC's libatomic, which provides software emulation of
atomic
operations
From: Daniel Hellstrom dan...@gaisler.com
This patch adds a default network tasks CPU affinity configuration
option. The network drivers have the option to create their own
daemon tasks with a custom CPU affinity set, or rely on the
default set.
---
cpukit/libnetworking/rtems/rtems_bsdnet.h
From: Daniel Hellstrom dan...@gaisler.com
Similar to the task priority option, the new CPU affinity
option is first controlled by the RPCI specific rpciodCpuset
option. If that is not set, it uses the global network task config.
If that is also not set, it falls back to not setting the affinity
On 2014-11-13 10:23, Sebastian Huber wrote:
On 13/11/14 10:09, Daniel Cederman wrote:
@@ -407,6 +410,8 @@ static rtems_intervalticksPerSec;/*
cached system clock rate (WHO IS ASSUMED
*/
rtems_task_priorityrpciodPriority = 0
From: Daniel Hellstrom dan...@gaisler.com
This patch adds a default network tasks CPU affinity configuration
option. The network drivers have the option to create their own
daemon tasks with a custom CPU affinity set, or rely on the
default set.
---
cpukit/libnetworking/rtems/rtems_bsdnet.h
From: Daniel Hellstrom dan...@gaisler.com
Similar to the task priority option, the new CPU affinity
option is first controlled by the RPCI specific rpciodCpuset
option. If that is not set, it uses the global network task config.
If that is also not set, it falls back to not setting the affinity
An oversight. I've now added const to all cpuset references.
On 2014-11-13 13:44, Sebastian Huber wrote:
On 13/11/14 11:21, Daniel Cederman wrote:
+cpu_set_t*network_task_cpuset;
The consumer of this field (rtems_task_set_affinity()) uses a const
cpuset, so why is this not const
Similar to the task priority option, the new CPU affinity
option is first controlled by the RPCI specific rpciodCpuset
option. If that is not set, it uses the global network task config.
If that is also not set, it falls back to not setting the affinity
at all, using all CPUs.
---
This patch adds a default network tasks CPU affinity configuration
option. The network drivers have the option to create their own
daemon tasks with a custom CPU affinity set, or rely on the
default set.
---
cpukit/libnetworking/rtems/rtems_bsdnet.h | 9 ++
---
testsuites/smptests/Makefile.am | 1 +
testsuites/smptests/configure.ac | 1 +
testsuites/smptests/smpcapture02/Makefile.am | 19 +
testsuites/smptests/smpcapture02/init.c | 425 ++
---
doc/networking/networkapp.t | 14 ++
1 file changed, 14 insertions(+)
diff --git a/doc/networking/networkapp.t b/doc/networking/networkapp.t
index 62b1a53..dd356a8 100644
--- a/doc/networking/networkapp.t
+++ b/doc/networking/networkapp.t
@@ -101,6 +101,11 @@ struct
This allows it to be wrapped by another function at link-time
and can be used to trace interrupts. If not placed in a separate
file, the function pointer address used in BSP_shared_interrupt_init
will be resolved at compile-time, and the function will not be wrappable.
---
---
doc/cpu_supplement/sparc.t | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/doc/cpu_supplement/sparc.t b/doc/cpu_supplement/sparc.t
index cd5602c..d21e9fe 100644
--- a/doc/cpu_supplement/sparc.t
+++ b/doc/cpu_supplement/sparc.t
@@ -951,10 +951,18 @@
Author:Daniel Cederman ceder...@gaisler.com
Date: Wed Feb 4 10:04:05 2015 +0100
smpcapture02: Add test of functionality to add custom entries to
capture trace
---
testsuites/smptests/Makefile.am | 1 +
testsuites/smptests/configure.ac | 1
---
c/src/lib/libcpu/shared/src/cache_manager.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c
b/c/src/lib/libcpu/shared/src/cache_manager.c
index 7ff1166..89ec88f 100644
--- a/c/src/lib/libcpu/shared/src/cache_manager.c
+++
Otherwise there is a risk that a CPU misses a cache manager message
from another CPU and the test hangs.
---
testsuites/smptests/smpcache01/init.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/testsuites/smptests/smpcache01/init.c
b/testsuites/smptests/smpcache01/init.c
.
--
Daniel Cederman
Software Engineer
Cobham Gaisler
F : +46 (0) 31 421407
daniel.ceder...@gaisler.com
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When I think a bit more of it, one probably should update the PSR after
the heir has been acquired, as the task could potentially be acquired
and released again with a new PSR by another core before the swap.
On 2015-11-12 11:27, Daniel Cederman wrote:
Hello,
I experienced a bug when using
Yes, definitely. Would you mind doing it? Daniel is away from office
this week and I do not have access.
On 2015-11-16 15:57, Sebastian Huber wrote:
Looks good, we should probably apply it to the 4.11 branch as well.
--
Daniel Cederman
Software Engineer
Cobham Gaisler
I was unsure if the ET bit was always set or not for newly created task
contexts, or if this was the first place that traps got enabled for a
new task. If it is always set we can remove that instruction.
On 2015-11-16 11:27, Sebastian Huber wrote:
On 16/11/15 11:06, Daniel Cederman wrote
We must not load registers (e.g. PSR) from the heir context area before
the heir stopped execution.
---
c/src/lib/libbsp/sparc/shared/irq_asm.S | 30 +-
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/c/src/lib/libbsp/sparc/shared/irq_asm.S
Great, thanks!
On 2015-11-17 09:01, Sebastian Huber wrote:
Thanks, I check in this patch on the 4.11 branch.
--
Daniel Cederman
Software Engineer
Cobham Gaisler
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We must not load registers (e.g. PSR) from the heir context area before
the heir stopped execution.
With this patch the write to PSR is divided into two steps. We first update
the current window pointer and then we restore the status registers and
enable traps. This allows us to move the first
The UT699 requires -mcpu=leon as it does not support the CAS instruction
provided by -mcpu=leon3. It also requires -mfix-ut699 for errata fixes.
UT700 and GR712RC requires the -mfix-ut700 and -mfix-gr712rc flags that
have been recently added to GCC's master and 7-branch.
Remove -msoft-float from
This patch adds NOP instructions to prevent instruction sequences
that are sensitive to the LEON3FT B2BST errata. See GRLIB-TN-0009:
"LEON3FT Stale Cache Entry After Store with Data Tag Parity Error"
for more information.
The sequences are only modified if __FIX_LEON3FT_B2BST is defined.
The
is detected by probing.
So in RCC hard floats have always been used if the hardware supports it,
as I understand it. I could revise the patch to remove the -msoft-flag
as, as you say, most people would like to use hard floats.
--
Daniel Cederman
Software Engineer
Cobham Gaisler
The UT699 requires -mcpu=leon as it does not support the CAS instruction
provided by -mcpu=leon3. It also requires -mfix-ut699 for errata fixes.
UT700 and GR712RC requires the -mfix-ut700 and -mfix-gr712rc flags that
have been recently added to GCC's master and 7-branch.
---
only being saved if the last FP task was
switched out as the result of an interrupt? And similar for loading the
FP context? No need to load it if returning from a call to
rtems_task_wake_after() I guess.
--
Daniel Cederman
Software Engineer
Cobham Gaisler
On 2017-07-14 14:02, Sebastian Huber wrote:
Could you please point me to the relevant thread on the mailing list?
No, this was just something I was told. If you do not recognize it I
might have misunderstood.
--
Daniel Cederman
Software Engineer
Cobham Gaisler
a good idea. I will revise my patch and remove -msoft-float.
--
Daniel Cederman
Software Engineer
Cobham Gaisler
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Hi Joel,
Yes, there was a bug in one of the errata fixes. It has been fixed now,
see https://gcc.gnu.org/ml/gcc-patches/2017-12/msg00593.html and
https://devel.rtems.org/ticket/3242#comment:4.
Daniel C
On 2017-12-19 16:18, Joel Sherrill wrote:
Hi
Has anyone else seen this?
Thanks Joel, I have updated the license information.
Martin Aberg (2):
bsp/riscv: Work area size based on stack pointer
bsp/riscv: Add NOEL-V BSP
bsps/riscv/include/bsp/start.h| 67 ++
bsps/riscv/noel/console/console-config.c | 209 ++
From: Martin Aberg
Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support
is implemented as a riscv BSP. Both 32-bit and 64-bit processor
systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP
is described here:
https://www.gaisler.com/NOELV
Compatible with the
From: Martin Aberg
Remember the initial stack pointer in start.S. It can later be used to
determine top of RAM.
---
bsps/riscv/include/bsp/start.h| 67
.../shared/start/bspgetworkarea-fromstack.c | 76 +++
bsps/riscv/shared/start/start.S
From: Martin Aberg
Remember the initial stack pointer in start.S. It can later be used to
determine top of RAM.
---
bsps/riscv/include/bsp/start.h| 65 +++
.../shared/start/bspgetworkarea-fromstack.c | 53 +++
bsps/riscv/shared/start/start.S
Thank you Sebastian for reviewing the patches. I have updated
them according to your comments.
Martin Aberg (2):
bsp/riscv: Work area size based on stack pointer
bsp/riscv: Add NOEL-V BSP
bsps/riscv/include/bsp/start.h| 65 ++
bsps/riscv/noel/console/console-config.c
From: Martin Aberg
Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support
is implemented as a riscv BSP. Both 32-bit and 64-bit processor
systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP
is described here:
https://www.gaisler.com/NOELV
Compatible with the
From: Martin Aberg
Remember the initial stack pointer in start.S. It can later be used to
determine top of RAM.
---
bsps/riscv/include/bsp/start.h| 65 +++
.../shared/start/bspgetworkarea-fromstack.c | 53 +++
bsps/riscv/shared/start/start.S
From: Martin Aberg
Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support
is implemented as a riscv BSP. Both 32-bit and 64-bit processor
systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP
is described here:
https://www.gaisler.com/NOELV
Compatible with the
From: Martin Aberg
---
spec/build/bsps/riscv/noel/abi.yml| 48 +++
spec/build/bsps/riscv/noel/bspnoel32im.yml| 19 ++
spec/build/bsps/riscv/noel/bspnoel32imafd.yml | 19 ++
spec/build/bsps/riscv/noel/bspnoel64imac.yml | 19 ++
From: Martin Aberg
---
bsps/riscv/noel/config/noel32im.cfg | 9 +
bsps/riscv/noel/config/noel32imafd.cfg | 9 +
bsps/riscv/noel/config/noel64imac.cfg | 9 +
bsps/riscv/noel/config/noel64imafd.cfg | 9 +
bsps/riscv/noel/config/noel64imafdc.cfg | 9
Hello,
This patch set adds support for the NOEL-V RISC-V processors.
Currently there is a problem linking the ts-validation-cache.exe test
for 64-bit configurations. It fails with the following error message:
bsps/riscv/shared/start/start.S:100:(.bsp_start_text+0x70): relocation
truncated to
From: Martin Aberg
The real dependency in this case is on rtems/irq-extension.h. The theme in
other other console drivers is to get it via bsp/irq.h, so that pattern is
followed.
---
bsps/shared/grlib/uart/apbuart_termios.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Defaults to "-kernel", but can be changed to, for example, "-bios".
---
tester/rtems/testing/qemu.cfg | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tester/rtems/testing/qemu.cfg b/tester/rtems/testing/qemu.cfg
index 3c51bee..0b592ef 100644
---
This avoids overlapping the RTEMS image with the builtin opensbi image
and the location of the fdt.
---
tester/rtems/testing/bsps/rv64imafd_medany.ini | 3 ++-
tester/rtems/testing/bsps/rv64imafdc_medany.ini | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git
On 2022-08-19 11:16, Hesham Almatary wrote:
On Thu, 18 Aug 2022 at 13:55, Daniel Cederman wrote:
I missed your comment, but have made the change now. Are there any instructions
on how to run the RISCV BSP tests on QEMU or Spike? I could not get it to work.
Do I need a special version of QEMU
v5
Made RISCV_CONSOLE_MAX_APBUART_DEVICES an option
bsp_fatal if no uart clock frequency is found
Changed CONSOLE_USE_INTERRUPTS to BSP_CONSOLE_USE_INTERRUPTS
Added error codes for APBUART
Get work area size from /memory node
Martin Aberg (1):
bsp/riscv: Add NOEL-V BSP
From: Martin Aberg
Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support
is implemented as a riscv BSP. Both 32-bit and 64-bit processor
systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP
is described here:
https://www.gaisler.com/NOELV
Compatible with the
== 0" with "end == NULL" as per my
comment above. Also please test on other RISC-V QEMU platforms to make
sure nothing got broken.
On Wed, 17 Aug 2022 at 14:10, Joel Sherrill wrote:
I'm ok with this if Hesham acks as well.
--joel
On Wed, Aug 17, 2022 at 6:35 AM Daniel Cederman wr
On 2022-08-30 21:04, Sebastian Huber wrote:
On 25/08/2022 10:33, Daniel Cederman wrote:
+#define BSP_INTERRUPT_VECTOR_MIN 0
+
+#define BSP_INTERRUPT_VECTOR_MAX
RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS - 1)
I am a bit surprised that this worked, since the API changed
.
--joel
On Tue, Aug 30, 2022 at 6:39 AM Daniel Cederman
wrote:
Hi,
Is it OK to push this or should I wait for additional comments?
On 2022-08-25 10:33, Daniel Cederman wrote:
v5
Made RISCV_CONSOLE_MAX_APBUART_DEVICES an option
bsp_fatal if no uart clock frequency
From: Martin Aberg
Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support
is implemented as a riscv BSP. Both 32-bit and 64-bit processor
systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP
is described here:
https://www.gaisler.com/NOELV
Compatible with the
v6
Change family entry to noel in all BSP build specs
Synchronize irq.h and riscv.h with versions in riscv BSP
Martin Aberg (1):
bsp/riscv: Add NOEL-V BSP
bsps/include/bsp/fatal.h | 3 +
bsps/riscv/noel/console/console-config.c | 208 ++
Hi,
Is it OK to push this or should I wait for additional comments?
On 2022-08-25 10:33, Daniel Cederman wrote:
v5
Made RISCV_CONSOLE_MAX_APBUART_DEVICES an option
bsp_fatal if no uart clock frequency is found
Changed CONSOLE_USE_INTERRUPTS to BSP_CONSOLE_USE_INTERRUPTS
Added error codes
---
user/bsps/bsps-riscv.rst | 57
1 file changed, 57 insertions(+)
diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst
index 48e7ee7..73a6038 100644
--- a/user/bsps/bsps-riscv.rst
+++ b/user/bsps/bsps-riscv.rst
@@ -248,6 +248,63 @@ Serial
---
user/bsps/bsps-sparc.rst | 74 ++--
1 file changed, 72 insertions(+), 2 deletions(-)
diff --git a/user/bsps/bsps-sparc.rst b/user/bsps/bsps-sparc.rst
index d0316a9..a2c2a47 100644
--- a/user/bsps/bsps-sparc.rst
+++ b/user/bsps/bsps-sparc.rst
@@ -20,11
From: Martin Aberg
Remember the initial stack pointer in start.S. It can later be used to
determine top of RAM.
---
bsps/riscv/include/bsp/start.h| 67
.../shared/start/bspgetworkarea-fromstack.c | 76 +++
bsps/riscv/shared/start/start.S
From: Martin Aberg
Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support
is implemented as a riscv BSP. Both 32-bit and 64-bit processor
systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP
is described here:
https://www.gaisler.com/NOELV
Compatible with the
v4
Changed .data to .bsp_start_data
Moved assembly defines to asm.h
Use the common optextirqmax
Use optconsoleirq instead of optconirq
Declared riscv_start_stack_pointer as const
Martin Aberg (2):
bsp/riscv: Work area size based on stack pointer
bsp/riscv: Add NOEL-V BSP
On 2022-08-15 15:43, Hesham Almatary wrote:
On Mon, 15 Aug 2022 at 08:16, Daniel Cederman wrote:
From: Martin Aberg
Remember the initial stack pointer in start.S. It can later be used to
determine top of RAM.
---
bsps/riscv/include/bsp/start.h| 67
Uses the first entry in the /memory node to determine the end of the
work area. Falls back on linker symbol if unable to parse the node.
---
bsps/riscv/shared/start/bspgetworkarea.c | 144 +++
spec/build/bsps/riscv/riscv/obj.yml | 1 +
2 files changed, 145 insertions(+)
Sure, I can move it to the shared directory (riscv/shared/start).
On 2022-08-17 11:16, Hesham Almatary wrote:
Thanks for the patch. LGTM. I wonder if we can also reuse that for the
generic shared RISC-V BSP (e.g., bsps/riscv/riscv) instead of just NOEL?
On Wed, 17 Aug 2022 at 09:58, Daniel
Uses the first entry in the /memory node to determine the end of the
work area. Falls back on linker symbol if unable to parse the node.
---
bsps/riscv/noel/start/bspgetworkarea.c | 144 +
spec/build/bsps/riscv/noel/obj.yml | 1 +
2 files changed, 145 insertions(+)
On 2022-08-15 17:19, Hesham Almatary wrote:
On Mon, 15 Aug 2022 at 15:35, Daniel Cederman wrote:
On 2022-08-15 15:43, Hesham Almatary wrote:
On Mon, 15 Aug 2022 at 08:16, Daniel Cederman wrote:
From: Martin Aberg
Remember the initial stack pointer in start.S. It can later be used
to
rtems-net-legacy but not deleted here.
On Mon, Nov 14, 2022 at 2:50 AM Daniel Cederman wrote:
---
bsps/include/libchip/greth.h | 152 ---
1 file changed, 152 deletions(-)
delete mode 100644 bsps/include/libchip/greth.h
diff --git a/bsps/include/libchip/greth.h b
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
---
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
---
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
---
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
---
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Updates #3053.
---
testsuites/smptests/smpcapture02/init.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
---
---
bsps/include/libchip/greth.h | 152 ---
1 file changed, 152 deletions(-)
delete mode 100644 bsps/include/libchip/greth.h
diff --git a/bsps/include/libchip/greth.h b/bsps/include/libchip/greth.h
deleted file mode 100644
index c6e000dbd3..00
---
Moved prototype for __gnat_install_handler and __gnat_install_handler_common to
common header file.
---
c/src/lib/libbsp/sparc/Makefile.am |1 +
c/src/lib/libbsp/sparc/erc32/Makefile.am |1 +
c/src/lib/libbsp/sparc/erc32/gnatsupp/gnatsupp.c |2 +-
---
c/src/lib/libbsp/sparc/leon2/pci/pci.c|4 ++--
c/src/lib/libbsp/sparc/leon3/pci/pci.c|4 ++--
c/src/lib/libbsp/sparc/shared/1553/b1553brm_pci.c | 10 ++
c/src/lib/libbsp/sparc/shared/can/occan_pci.c |2 ++
---
c/src/lib/libbsp/sparc/erc32/include/bsp.h |2 ++
c/src/lib/libbsp/sparc/leon2/include/bsp.h |2 ++
c/src/lib/libbsp/sparc/leon3/include/bsp.h |2 ++
3 files changed, 6 insertions(+)
diff --git a/c/src/lib/libbsp/sparc/erc32/include/bsp.h
---
.../lib/libbsp/powerpc/mpc55xxevb/network/if_smc.c |5 -
.../sparc/leon2/leon_smc9/leon_smc9.c |5 -
.../sparc/leon3/leon_smc9/leon_smc9.c |3 ---
c/src/libchip/network/smc9.c |7 ---
---
c/src/lib/libbsp/sparc/leon2/include/leon.h|2 +-
.../libbsp/sparc/leon3/console/printk_support.c|8
c/src/lib/libbsp/sparc/leon3/include/leon.h|2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git
---
cpukit/score/include/rtems/score/cpustdatomic.h |1 +
1 file changed, 1 insertion(+)
diff --git a/cpukit/score/include/rtems/score/cpustdatomic.h
b/cpukit/score/include/rtems/score/cpustdatomic.h
index 4023d0c..945467e 100644
--- a/cpukit/score/include/rtems/score/cpustdatomic.h
+++
So I should place gnatcommon.h in
c/src/lib/libbsp/sparc/shared/include/bsp instead?
On 2014-03-13 15:23, Joel Sherrill wrote:
On 3/13/2014 9:14 AM, Daniel Cederman wrote:
Moved prototype for __gnat_install_handler and __gnat_install_handler_common to
common header file.
---
c/src/lib
be private. I've rewritten the code so that it adds
static when included. Will post the new version shortly.
On 2014-03-13 16:01, Joel Sherrill wrote:
On 3/13/2014 9:26 AM, Gedare Bloom wrote:
On Thu, Mar 13, 2014 at 10:19 AM, Daniel Cederman ceder...@gaisler.com wrote:
---
c/src/lib/libbsp
Also move amba.h to bsp namespace.
---
c/src/lib/libbsp/sparc/leon3/Makefile.am |2 +-
c/src/lib/libbsp/sparc/leon3/include/cache_.h |2 +-
c/src/lib/libbsp/sparc/leon3/include/leon.h |2 +-
c/src/lib/libbsp/sparc/leon3/preinstall.am|6 +++---
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