Re: Repo Transition to GitLab

[Sebastian Huber]

On 26.04.24 00:38, Chris Johns wrote:

Hi RTEMS Community

The git repos on git.rtems.org are open and accepting patches. The GitLab repos
will move us to main, something we have been waiting to do. Allowing commits
into the repos means they will be brought across and played on top of the new
main branch. We have changes in the repo on GitLab as part of our testing and
new files such as CODEOWNERS.

As a result you will check out main and not rename your master to main.


When will the GitLab available? I can wait with my pending patches so 
that the associated tickets get updated when they are checked in. How 
will the ticket updates work in GitLab? Are the ticket numbers the same?


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[RFC v2] rtems: Add options to kernel output char handler

[Sebastian Huber]

Make the kernel I/O output character device processing configurable
through an option set parameter.  Add RTEMS_IO_NO_OUTPUT and
RTEMS_IO_DRAIN options.  The goal of this API change is to enable
draining the kernel output device in the system termination process
before a reset is issued.  A use case for using RTEMS_NO_WAIT is the
polled processing of an input and output stream from and to the I/O
device.
---
v2:

* Do not use EARS.

* Rename RTEMS_FLUSH in RTEMS_IO_DRAIN.

* Rename RTEMS_NO_OUTPUT in RTEMS_IO_NO_TRANSMISSION.

* Add example adoption for sparc/leon3.

 bsps/sparc/leon3/console/printk_support.c | 54 +++---
 cpukit/include/rtems/bspIo.h  | 55 ++-
 cpukit/include/rtems/rtems/options.h  | 22 -
 cpukit/libcsupport/src/rtems_putc.c   |  4 +-
 testsuites/validation/tc-io-put-char.c|  8 +++-
 testsuites/validation/tr-io-kernel.c  |  4 +-
 6 files changed, 132 insertions(+), 15 deletions(-)

diff --git a/bsps/sparc/leon3/console/printk_support.c 
b/bsps/sparc/leon3/console/printk_support.c
index fd23a5033f..adfd653060 100644
--- a/bsps/sparc/leon3/console/printk_support.c
+++ b/bsps/sparc/leon3/console/printk_support.c
@@ -43,6 +43,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -56,6 +57,11 @@ apbuart *leon3_debug_uart = NULL;
 
 static void bsp_debug_uart_init(void);
 
+static bool apbuart_can_transmit(apbuart *regs)
+{
+  return (grlib_load_32(>status) & APBUART_STATUS_TE) != 0;
+}
+
 static void apbuart_enable_receive_and_transmit(apbuart *regs)
 {
   uint32_t ctrl;
@@ -66,10 +72,38 @@ static void apbuart_enable_receive_and_transmit(apbuart 
*regs)
   grlib_store_32(>status, 0);
 }
 
-static void bsp_debug_uart_output_char(char c)
+static rtems_status_code bsp_debug_uart_output_char(
+  char c,
+  rtems_option option_set
+)
 {
-  apbuart_outbyte_polled(leon3_debug_uart, c);
-  apbuart_outbyte_wait(leon3_debug_uart);
+  apbuart *regs = leon3_debug_uart;
+  rtems_status_code status = RTEMS_SUCCESSFUL;
+
+  while (true) {
+if (apbuart_can_transmit(regs)) {
+  if ((option_set & RTEMS_IO_NO_TRANSMISSION) == 0) {
+grlib_store_32(>data, (uint8_t) c);
+  }
+
+  break;
+}
+
+if ((option_set & RTEMS_NO_WAIT) != 0) {
+  status = RTEMS_UNSATISFIED;
+  break;
+}
+
+_IO_Relax();
+  }
+
+  if ((option_set & RTEMS_IO_DRAIN) != 0) {
+while (!apbuart_can_transmit(regs)) {
+  _IO_Relax();
+}
+  }
+
+  return status;
 }
 
 static int bsp_debug_uart_poll_char(void)
@@ -77,10 +111,13 @@ static int bsp_debug_uart_poll_char(void)
   return apbuart_inbyte_nonblocking(leon3_debug_uart);
 }
 
-static void bsp_debug_uart_pre_init_out(char c)
+static rtems_status_code bsp_debug_uart_pre_init_out(
+  char c,
+  rtems_option option_set
+)
 {
   bsp_debug_uart_init();
-  (*BSP_output_char)(c);
+  return (*BSP_output_char)(c, option_set);
 }
 
 #if defined(LEON3_APBUART_BASE)
@@ -94,9 +131,14 @@ static void bsp_debug_uart_init(void)
 
 #else /* !LEON3_APBUART_BASE */
 
-static void bsp_debug_uart_discard(char c)
+static rtems_status_code bsp_debug_uart_discard(
+  char c,
+  rtems_option option_set
+)
 {
   (void) c;
+  (void) option_set;
+  return RTEMS_SUCCESSFUL;
 }
 
 /* Initialize the BSP system debug console layer. It will scan AMBA Plu
diff --git a/cpukit/include/rtems/bspIo.h b/cpukit/include/rtems/bspIo.h
index 31580cd800..7848704992 100644
--- a/cpukit/include/rtems/bspIo.h
+++ b/cpukit/include/rtems/bspIo.h
@@ -10,7 +10,7 @@
  */
 
 /*
- * Copyright (C) 2020, 2021 embedded brains GmbH & Co. KG
+ * Copyright (C) 2020, 2024 embedded brains GmbH & Co. KG
  * Copyright (C) 2015 On-Line Applications Research Corporation (OAR)
  *
  * Redistribution and use in source and binary forms, with or without
@@ -58,6 +58,8 @@
 #define _RTEMS_BSPIO_H
 
 #include 
+#include 
+#include 
 #include 
 
 #ifdef __cplusplus
@@ -89,8 +91,48 @@ extern "C" {
  * @ingroup RTEMSAPIKernelCharIO
  *
  * @brief Polled character output functions shall have this type.
+ *
+ * @param out is the character to transmit.
+ *
+ * @param option_set is the option set.
+ *
+ * The behaviour of polled character output functions can be controlled by the
+ * three options #RTEMS_NO_WAIT, #RTEMS_IO_NO_TRANSMISSION, and #RTEMS_IO_DRAIN
+ * specified in the ``option_set`` parameter.
+ *
+ * If the #RTEMS_NO_WAIT option is set in the ``option_set`` parameter and the
+ * device cannot immediately accept a character for transmission, then the
+ * character in ``out`` shall not be transmitted by the device, optionally the
+ * device shall be drained, and ::RTEMS_UNSATISFIED shall be returned.
+ *
+ * If the #RTEMS_IO_NO_TRANSMISSION option is set in the ``option_set``
+ * parameter, the character in the ``out`` parameter shall not be transmitted
+ * by the device.
+ *
+ * If the #RTEMS_NO_WAIT and #RTEMS_IO_NO_TRANSMISSION options are cleared in
+ * the ``option_set`` parameter, then the character in the 

Re: [PATCH v2] rtems: Add get/set interrupt priorities

[Sebastian Huber]

On 16.04.24 07:25, Sebastian Huber wrote:

On 09.04.24 16:28, Sebastian Huber wrote:

Add directives to get and set the priority of an interrupt vector.

Implement the directives for the following BSP families:

* arm/lpc24xx
* arm/lpc32xx
* powerpc/mpc55xxevb
* powerpc/qoriq

Implement the directives for the following interrupt controllers:

* GICv2 and GICv3 (arm and aarch64)
* NVIC (arm)
* PLIC (riscv)

Update #5002.


Any comments to this API extension?


If there are no objections, then I will commit this patch set next Monday.

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Re: Cortex-M floating point (Was: RTEMS 6 branching)

[Sebastian Huber]

On 24.04.24 14:37, Cedric Berger wrote:

Hello Sebastian,

On 23.04.2024 19:56, Sebastian Huber wrote:

1. Are all the things need for the release resolved? Tickets reviewed?

It would be nice to have the interrupt get/set priority API in RTEMS 6. The 
Cortex-M floating point issue is not yet fixed in the RTEMS master.


Do you have any feedback on the two patches that I posted on the ticket, 
which seems to fix the issue?


It would be great if you could check the patch at the end of this mail:

https://lists.rtems.org/pipermail/devel/2024-February/077228.html

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[PATCH 9/9] bsp/tms570: Use write-back/write-allocate SDRAM

[Sebastian Huber]

Update #4982.
---
 bsps/arm/tms570/start/tms570_sys_core.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bsps/arm/tms570/start/tms570_sys_core.S 
b/bsps/arm/tms570/start/tms570_sys_core.S
index 83dee26ec8..ef28d88ede 100644
--- a/bsps/arm/tms570/start/tms570_sys_core.S
+++ b/bsps/arm/tms570/start/tms570_sys_core.S
@@ -655,7 +655,7 @@ _mpuInit_:
 mcr   p15, #0,r0, c6, c2, #0
 ldr   r0,  r6Base
 mcr   p15, #0,r0, c6, c1, #0
-mov   r0,  #0x0002
+mov   r0,  #0x000B
 orr   r0,  r0,#0x0300
 mcr   p15, #0,r0, c6, c1, #4
 movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) 
+ (0 << 10) + (0 <<  9) + (0 <<  8) + (0x1A << 1) + (1))
-- 
2.35.3

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[PATCH 8/9] bsp/tms570: Use RTI for CPU counter

[Sebastian Huber]

The performance monitor counter is stopped when the core is waiting for
interrupts.

Update #4982.
---
 bsps/arm/tms570/clock/clock.c   | 71 --
 bsps/arm/tms570/cpucounter/cpucounterread.c | 83 -
 spec/build/bsps/arm/tms570/obj.yml  |  1 -
 3 files changed, 48 insertions(+), 107 deletions(-)
 delete mode 100644 bsps/arm/tms570/cpucounter/cpucounterread.c

diff --git a/bsps/arm/tms570/clock/clock.c b/bsps/arm/tms570/clock/clock.c
index 2fb884b3ce..4465e33843 100644
--- a/bsps/arm/tms570/clock/clock.c
+++ b/bsps/arm/tms570/clock/clock.c
@@ -44,27 +44,24 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 
 static struct timecounter tms570_rti_tc;
 
-static uint32_t tms570_rti_get_timecount(struct timecounter *tc)
+uint32_t _CPU_Counter_frequency(void)
 {
-  return TMS570_RTI.CNT[0].FRCx;
+  return TMS570_RTICLK_HZ / 2;
 }
 
-static void tms570_clock_driver_support_initialize_hardware( void )
+CPU_Counter_ticks _CPU_Counter_read(void)
 {
+  return TMS570_RTI.CNT[0].FRCx;
+}
 
-  uint64_t usec_per_tick;
-  uint32_t tc_frequency;
-  uint32_t tc_increments_per_tick;
-  struct timecounter *tc;
-
-  usec_per_tick = rtems_configuration_get_microseconds_per_tick();
-  tc_frequency = TMS570_RTICLK_HZ / 2;
-  tc_increments_per_tick = (usec_per_tick * tc_frequency + 50) / 100;
-
+static void tms570_rti_initialize( void )
+{
   /* Initialize module */
   TMS570_RTI.GCTRL = 0;
   TMS570_RTI.CAPCTRL = 0;
@@ -72,14 +69,7 @@ static void tms570_clock_driver_support_initialize_hardware( 
void )
   TMS570_RTI.TBCTRL = TMS570_RTI_TBCTRL_INC;
   TMS570_RTI.INTCLRENABLE = 0x05050505;
 
-  /* Initialize counter 0 */
-  TMS570_RTI.CNT[0].CPUCx = 1;
-  TMS570_RTI.CNT[0].UCx = 0;
-  TMS570_RTI.CNT[0].FRCx = 0;
-  TMS570_RTI.CMP[0].COMPx = tc_increments_per_tick;
-  TMS570_RTI.CMP[0].UDCPx = tc_increments_per_tick;
-
-  /* Clear interrupts */
+  /* Disable interrupts */
   TMS570_RTI.CLEARINTENA = TMS570_RTI_CLEARINTENA_CLEAROVL1INT |
TMS570_RTI_CLEARINTENA_CLEAROVL0INT |
TMS570_RTI_CLEARINTENA_CLEARTBINT |
@@ -91,6 +81,44 @@ static void tms570_clock_driver_support_initialize_hardware( 
void )
TMS570_RTI_CLEARINTENA_CLEARINT2 |
TMS570_RTI_CLEARINTENA_CLEARINT1 |
TMS570_RTI_CLEARINTENA_CLEARINT0;
+
+  /* Initialize counter 0 */
+  TMS570_RTI.CNT[0].CPUCx = 1;
+  TMS570_RTI.CNT[0].UCx = 0;
+  TMS570_RTI.CNT[0].FRCx = 0;
+
+  /* Enable counter 0 */
+  TMS570_RTI.GCTRL = TMS570_RTI_GCTRL_CNT0EN;
+}
+
+RTEMS_SYSINIT_ITEM(
+  tms570_rti_initialize,
+  RTEMS_SYSINIT_CPU_COUNTER,
+  RTEMS_SYSINIT_ORDER_MIDDLE
+);
+
+static uint32_t tms570_rti_get_timecount(struct timecounter *tc)
+{
+  return TMS570_RTI.CNT[0].FRCx;
+}
+
+static void tms570_clock_driver_support_initialize_hardware( void )
+{
+
+  uint64_t usec_per_tick;
+  uint32_t tc_frequency;
+  uint32_t tc_increments_per_tick;
+  struct timecounter *tc;
+
+  usec_per_tick = rtems_configuration_get_microseconds_per_tick();
+  tc_frequency = TMS570_RTICLK_HZ / 2;
+  tc_increments_per_tick = (usec_per_tick * tc_frequency + 50) / 100;
+
+  /* Initialize compare 0 */
+  TMS570_RTI.CMP[0].UDCPx = tc_increments_per_tick;
+  TMS570_RTI.CMP[0].COMPx = TMS570_RTI.CNT[0].FRCx + tc_increments_per_tick;
+
+  /* Clear interrupts */
   TMS570_RTI.INTFLAG = TMS570_RTI_INTFLAG_OVL1INT |
TMS570_RTI_INTFLAG_OVL0INT |
TMS570_RTI_INTFLAG_TBINT |
@@ -99,9 +127,6 @@ static void tms570_clock_driver_support_initialize_hardware( 
void )
TMS570_RTI_INTFLAG_INT1 |
TMS570_RTI_INTFLAG_INT0;
 
-  /* Enable counter 0 */
-  TMS570_RTI.GCTRL = TMS570_RTI_GCTRL_CNT0EN;
-
   /* Enable interrupts for counter 0 */
   TMS570_RTI.SETINTENA = TMS570_RTI_SETINTENA_SETINT0;
 
diff --git a/bsps/arm/tms570/cpucounter/cpucounterread.c 
b/bsps/arm/tms570/cpucounter/cpucounterread.c
deleted file mode 100644
index 8cda09f0c6..00
--- a/bsps/arm/tms570/cpucounter/cpucounterread.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMTMS570
- *
- * @brief This source file contains the CPU Counter implementation.
- *
- * The counters setup functions are these which has been suggested on
- * StackOverflow.  Code is probably for use on Cortex-A without modifications
- * as well.
- *
- * 
http://stackoverflow.com/questions/3247373/how-to-measure-program-execution-time-in-arm-cortex-a8-processor
- */
-
-/*
- * Copyright (C) 2014 Pavel Pisa 
- *
- * Czech Technical University in Prague
- * Zikova 1903/4
- * 166 36 Praha 6
- * Czech Republic
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the 

[PATCH 7/9] bsp/tms570: Add TMS570_FATAL_RTI_IRQ_INSTALL

[Sebastian Huber]

Update #4982.
---
 bsps/arm/tms570/clock/clock.c | 15 ---
 bsps/include/bsp/fatal.h  |  3 +++
 2 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/bsps/arm/tms570/clock/clock.c b/bsps/arm/tms570/clock/clock.c
index cf14d5772f..2fb884b3ce 100644
--- a/bsps/arm/tms570/clock/clock.c
+++ b/bsps/arm/tms570/clock/clock.c
@@ -41,6 +41,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -117,19 +118,11 @@ static void tms570_clock_driver_support_at_tick(volatile 
tms570_rti_t *rti)
   rti->INTFLAG = TMS570_RTI_INTFLAG_INT0;
 }
 
-/**
- * @brief registers RTI interrupt handler
- *
- * @param[in] Clock_isr new ISR handler
- * @param[in] Old_ticker old ISR handler (unused and type broken)
- *
- * @retval Void
- */
 static void tms570_clock_driver_support_install_isr(
   rtems_interrupt_handler handler
 )
 {
-  rtems_status_code sc = RTEMS_SUCCESSFUL;
+  rtems_status_code sc;
 
   sc = rtems_interrupt_handler_install(
 TMS570_IRQ_TIMER_0,
@@ -138,8 +131,8 @@ static void tms570_clock_driver_support_install_isr(
 handler,
 RTEMS_DEVOLATILE(tms570_rti_t *, _RTI)
   );
-  if ( sc != RTEMS_SUCCESSFUL ) {
-rtems_fatal_error_occurred(0xdeadbeef);
+  if (sc != RTEMS_SUCCESSFUL) {
+bsp_fatal(TMS570_FATAL_RTI_IRQ_INSTALL);
   }
 }
 
diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h
index 87fc481ead..b41ef2d5c2 100644
--- a/bsps/include/bsp/fatal.h
+++ b/bsps/include/bsp/fatal.h
@@ -217,6 +217,9 @@ typedef enum {
 
   /* Xilinx fatal codes */
   XIL_FATAL_TTC_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(17),
+
+  /* TMS570 fatal codes */
+  TMS570_FATAL_RTI_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(18),
 } bsp_fatal_code;
 
 RTEMS_NO_RETURN static inline void
-- 
2.35.3

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[PATCH 1/9] arm: Add arm_cp15_data_cache_all_invalidate()

[Sebastian Huber]

Update #4982.
---
 cpukit/score/cpu/arm/include/libcpu/arm-cp15.h | 17 +
 1 file changed, 17 insertions(+)

diff --git a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h 
b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
index c239eaccc8..4a5ddb561e 100644
--- a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
+++ b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
@@ -2371,6 +2371,23 @@ arm_cp15_set_diagnostic_control(uint32_t val)
   );
 }
 
+/* This is probably a Cortex-R5 specific operation */
+ARM_CP15_TEXT_SECTION static inline void
+arm_cp15_data_cache_all_invalidate(void)
+{
+  ARM_SWITCH_REGISTERS;
+  uint32_t sbz = 0;
+
+  __asm__ volatile (
+ARM_SWITCH_TO_ARM
+"mcr p15, 0, %[sbz], c15, c5, 0\n"
+ARM_SWITCH_BACK
+: ARM_SWITCH_OUTPUT
+: [sbz] "r" (sbz)
+: "memory"
+  );
+}
+
 /**
  * @brief Sets the @a section_flags for the address range [@a begin, @a end).
  *
-- 
2.35.3

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[PATCH 6/9] bsp/tms570: Fix clock driver

[Sebastian Huber]

The clock tick rate was off by a factor of two in some configurations.
Use the maximum counter frequency to get the best time resolution.  Do
not use the automatic interrupt clear feature.

Update #4982.
---
 bsps/arm/tms570/clock/clock.c | 99 +++
 1 file changed, 32 insertions(+), 67 deletions(-)

diff --git a/bsps/arm/tms570/clock/clock.c b/bsps/arm/tms570/clock/clock.c
index a3ea08c967..cf14d5772f 100644
--- a/bsps/arm/tms570/clock/clock.c
+++ b/bsps/arm/tms570/clock/clock.c
@@ -9,6 +9,7 @@
  */
 
 /*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
  * Copyright (C) 2014 Premysl Houdek 
  *
  * Google Summer of Code 2014 at
@@ -39,9 +40,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include 
-
-#include 
 #include 
 #include 
 #include 
@@ -54,57 +52,33 @@ static uint32_t tms570_rti_get_timecount(struct timecounter 
*tc)
   return TMS570_RTI.CNT[0].FRCx;
 }
 
-#ifndef TMS570_PREFERRED_TC_FREQUENCY
-/*
- * Define preferred main time base counter frequency
- * The value of 1MHz is the best matching RTEMS
- * timing system because then there is no need
- * to scale RTEMS configuration microseconds_per_tick
- * parameter
- */
-#define TMS570_PREFERRED_TC_FREQUENCY 100
-#endif /* TMS570_PREFERRED_TC_FREQUENCY */
-
-/**
- *  @brief Initialize the HW peripheral for clock driver
- *
- *  Clock driver is implemented by RTI module
- *
- * @retval Void
- */
 static void tms570_clock_driver_support_initialize_hardware( void )
 {
 
-  uint32_t microsec_per_tick;
+  uint64_t usec_per_tick;
   uint32_t tc_frequency;
-  uint32_t tc_prescaler;
   uint32_t tc_increments_per_tick;
+  struct timecounter *tc;
 
-  microsec_per_tick = rtems_configuration_get_microseconds_per_tick();
-  tc_frequency = TMS570_PREFERRED_TC_FREQUENCY;
-
-  tc_prescaler = (TMS570_RTICLK_HZ + tc_frequency) / (tc_frequency * 2);
-
-  /* Recompute actual most close frequency which can be realized */
-  tc_frequency = (TMS570_RTICLK_HZ + tc_prescaler) / (tc_prescaler * 2);
+  usec_per_tick = rtems_configuration_get_microseconds_per_tick();
+  tc_frequency = TMS570_RTICLK_HZ / 2;
+  tc_increments_per_tick = (usec_per_tick * tc_frequency + 50) / 100;
 
-  /*
-   * Recompute tick period to adjust for configurable or exact
-   * preferred time base 1 usec resolution.
-   */
-  tc_increments_per_tick = ((uint64_t)microsec_per_tick * tc_frequency +
-   50) / 100;
-
-  /* Hardware specific initialize */
+  /* Initialize module */
   TMS570_RTI.GCTRL = 0;
-  TMS570_RTI.CNT[0].CPUCx = tc_prescaler - 1;
-  TMS570_RTI.TBCTRL = TMS570_RTI_TBCTRL_INC;
   TMS570_RTI.CAPCTRL = 0;
   TMS570_RTI.COMPCTRL = 0;
-  /* set counter to zero */
+  TMS570_RTI.TBCTRL = TMS570_RTI_TBCTRL_INC;
+  TMS570_RTI.INTCLRENABLE = 0x05050505;
+
+  /* Initialize counter 0 */
+  TMS570_RTI.CNT[0].CPUCx = 1;
   TMS570_RTI.CNT[0].UCx = 0;
   TMS570_RTI.CNT[0].FRCx = 0;
-  /* clear interrupts*/
+  TMS570_RTI.CMP[0].COMPx = tc_increments_per_tick;
+  TMS570_RTI.CMP[0].UDCPx = tc_increments_per_tick;
+
+  /* Clear interrupts */
   TMS570_RTI.CLEARINTENA = TMS570_RTI_CLEARINTENA_CLEAROVL1INT |
TMS570_RTI_CLEARINTENA_CLEAROVL0INT |
TMS570_RTI_CLEARINTENA_CLEARTBINT |
@@ -123,27 +97,21 @@ static void 
tms570_clock_driver_support_initialize_hardware( void )
TMS570_RTI_INTFLAG_INT2 |
TMS570_RTI_INTFLAG_INT1 |
TMS570_RTI_INTFLAG_INT0;
-  /* set timer */
-  TMS570_RTI.CMP[0].COMPx = TMS570_RTI.CNT[0].FRCx + tc_increments_per_tick;
-  TMS570_RTI.COMP0CLR = TMS570_RTI.CMP[0].COMPx + tc_increments_per_tick / 2;
-  TMS570_RTI.CMP[0].UDCPx = tc_increments_per_tick;
-  /* enable interupt */
-  TMS570_RTI.SETINTENA = TMS570_RTI_SETINTENA_SETINT0;
-  /* enable timer */
+
+  /* Enable counter 0 */
   TMS570_RTI.GCTRL = TMS570_RTI_GCTRL_CNT0EN;
-  /* set timecounter */
-  tms570_rti_tc.tc_get_timecount = tms570_rti_get_timecount;
-  tms570_rti_tc.tc_counter_mask = 0x;
-  tms570_rti_tc.tc_frequency = tc_frequency;
-  tms570_rti_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
-  rtems_timecounter_install(_rti_tc);
+
+  /* Enable interrupts for counter 0 */
+  TMS570_RTI.SETINTENA = TMS570_RTI_SETINTENA_SETINT0;
+
+  tc = _rti_tc;
+  tc->tc_get_timecount = tms570_rti_get_timecount;
+  tc->tc_counter_mask = 0x;
+  tc->tc_frequency = tc_frequency;
+  tc->tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
+  rtems_timecounter_install(tc);
 }
 
-/**
- * @brief Clears interrupt source
- *
- * @retval Void
- */
 static void tms570_clock_driver_support_at_tick(volatile tms570_rti_t *rti)
 {
   rti->INTFLAG = TMS570_RTI_INTFLAG_INT0;
@@ -175,14 +143,11 @@ static void tms570_clock_driver_support_install_isr(
   }
 }
 
-#define Clock_driver_support_initialize_hardware \
-tms570_clock_driver_support_initialize_hardware
+#define Clock_driver_support_initialize_hardware() 

[PATCH 4/9] bsp/tms570: Add TMS570LC4357 PLL support

[Sebastian Huber]

Update #4982.
---
 bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h 
b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h
index d5583a1cca..1ca2bff685 100644
--- a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h
+++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h
@@ -355,6 +355,11 @@ typedef struct{
 /* field: ROS - Reset on PLL Slip */
 #define TMS570_SYS1_PLLCTL1_ROS BSP_BIT32(31)
 
+/* field: BPOS - Bypass of PLL Slip */
+#define TMS570_SYS1_PLLCTL1_BPOS(val) BSP_FLD32(val,29, 30)
+#define TMS570_SYS1_PLLCTL1_BPOS_GET(reg) BSP_FLD32GET(reg,29, 30)
+#define TMS570_SYS1_PLLCTL1_BPOS_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
+
 /* field: MASK_SLIP - Mask detection of PLL slip */
 #define TMS570_SYS1_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
 #define TMS570_SYS1_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30)
@@ -404,6 +409,28 @@ typedef struct{
 #define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
 
 
+/*TMS570_SYS1_PLLCTL3*/
+/* field: ODPLL2 - Internal PLL Output Divider. */
+#define TMS570_SYS1_PLLCTL3_ODPLL2(val) BSP_FLD32(val, 29, 31)
+#define TMS570_SYS1_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg, 29, 31)
+#define TMS570_SYS1_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val, 29, 31)
+
+/* field: PLLDIV2 - PLL2 Output Clock Divider. */
+#define TMS570_SYS1_PLLCTL3_PLLDIV2(val) BSP_FLD32(val, 24, 28)
+#define TMS570_SYS1_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg, 24, 28)
+#define TMS570_SYS1_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val, 24, 28)
+
+/* field: REFCLKDIV2 - Reference Clock Divider. */
+#define TMS570_SYS1_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val, 16, 21)
+#define TMS570_SYS1_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg, 16, 21)
+#define TMS570_SYS1_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val, 16, 
21)
+
+/* field: PLLMUL2 - PLL2 Multiplication Factor. */
+#define TMS570_SYS1_PLLCTL3_PLLMUL2(val) BSP_FLD32(val, 0, 15)
+#define TMS570_SYS1_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg, 0, 15)
+#define TMS570_SYS1_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val, 0, 15)
+
+
 /*TMS570_SYS1_SYSPC10*/
 /* field: ECPCLK_SLEW - ECPCLK slew control. This bit controls between the 
fast or slow slew mode. */
 #define TMS570_SYS1_SYSPC10_ECPCLK_SLEW BSP_BIT32(0)
-- 
2.35.3

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[PATCH 5/9] bsp/tms570: Add clock BSP options

[Sebastian Huber]

Update #4982.
---
 bsps/arm/tms570/clock/clock.c   |  4 ++--
 bsps/arm/tms570/console/tms570-sci.c|  2 +-
 bsps/arm/tms570/cpucounter/cpucounterread.c |  2 +-
 bsps/arm/tms570/include/bsp.h   |  6 --
 spec/build/bsps/arm/tms570/grp.yml  | 12 
 spec/build/bsps/arm/tms570/optgclk.yml  | 21 +
 spec/build/bsps/arm/tms570/opthclk.yml  | 21 +
 spec/build/bsps/arm/tms570/optrticlk.yml| 21 +
 spec/build/bsps/arm/tms570/optvclk.yml  | 21 +
 spec/build/bsps/arm/tms570/optvclk2.yml | 21 +
 spec/build/bsps/arm/tms570/optvclk3.yml | 21 +
 11 files changed, 142 insertions(+), 10 deletions(-)
 create mode 100644 spec/build/bsps/arm/tms570/optgclk.yml
 create mode 100644 spec/build/bsps/arm/tms570/opthclk.yml
 create mode 100644 spec/build/bsps/arm/tms570/optrticlk.yml
 create mode 100644 spec/build/bsps/arm/tms570/optvclk.yml
 create mode 100644 spec/build/bsps/arm/tms570/optvclk2.yml
 create mode 100644 spec/build/bsps/arm/tms570/optvclk3.yml

diff --git a/bsps/arm/tms570/clock/clock.c b/bsps/arm/tms570/clock/clock.c
index 2e71440857..a3ea08c967 100644
--- a/bsps/arm/tms570/clock/clock.c
+++ b/bsps/arm/tms570/clock/clock.c
@@ -83,10 +83,10 @@ static void 
tms570_clock_driver_support_initialize_hardware( void )
   microsec_per_tick = rtems_configuration_get_microseconds_per_tick();
   tc_frequency = TMS570_PREFERRED_TC_FREQUENCY;
 
-  tc_prescaler = (BSP_PLL_OUT_CLOCK + tc_frequency) / (tc_frequency * 2);
+  tc_prescaler = (TMS570_RTICLK_HZ + tc_frequency) / (tc_frequency * 2);
 
   /* Recompute actual most close frequency which can be realized */
-  tc_frequency = (BSP_PLL_OUT_CLOCK + tc_prescaler) / (tc_prescaler * 2);
+  tc_frequency = (TMS570_RTICLK_HZ + tc_prescaler) / (tc_prescaler * 2);
 
   /*
* Recompute tick period to adjust for configurable or exact
diff --git a/bsps/arm/tms570/console/tms570-sci.c 
b/bsps/arm/tms570/console/tms570-sci.c
index 63f8e7c8ee..6cb61f2b5d 100644
--- a/bsps/arm/tms570/console/tms570-sci.c
+++ b/bsps/arm/tms570/console/tms570-sci.c
@@ -297,7 +297,7 @@ bool tms570_sci_set_attributes(
 
   /* Apply baudrate to the hardware */
   baudrate *= 2 * 16;
-  bauddiv = (BSP_PLL_OUT_CLOCK + baudrate / 2) / baudrate;
+  bauddiv = (TMS570_VCLK_HZ + baudrate / 2) / baudrate;
   ctx->regs->BRS = bauddiv? bauddiv - 1: 0;
 
   ctx->regs->GCR1 |= TMS570_SCI_GCR1_SWnRST | TMS570_SCI_GCR1_TXENA |
diff --git a/bsps/arm/tms570/cpucounter/cpucounterread.c 
b/bsps/arm/tms570/cpucounter/cpucounterread.c
index 009a37bec3..8cda09f0c6 100644
--- a/bsps/arm/tms570/cpucounter/cpucounterread.c
+++ b/bsps/arm/tms570/cpucounter/cpucounterread.c
@@ -68,7 +68,7 @@ static void tms570_cpu_counter_initialize(void)
 
 uint32_t _CPU_Counter_frequency(void)
 {
-  return 2 * BSP_PLL_OUT_CLOCK;
+  return TMS570_GCLK_HZ;
 }
 
 CPU_Counter_ticks _CPU_Counter_read(void)
diff --git a/bsps/arm/tms570/include/bsp.h b/bsps/arm/tms570/include/bsp.h
index 287750295f..1f84486ad4 100644
--- a/bsps/arm/tms570/include/bsp.h
+++ b/bsps/arm/tms570/include/bsp.h
@@ -61,12 +61,6 @@
 #include 
 #include 
 
-#if TMS570_VARIANT == 4357
-#define BSP_PLL_OUT_CLOCK 15000
-#else
-#define BSP_PLL_OUT_CLOCK 16000
-#endif
-
 RTEMS_NO_RETURN void bsp_restart(const void *addr);
 
 #endif /* ASM */
diff --git a/spec/build/bsps/arm/tms570/grp.yml 
b/spec/build/bsps/arm/tms570/grp.yml
index 5a3d4784be..c6d9f02d14 100644
--- a/spec/build/bsps/arm/tms570/grp.yml
+++ b/spec/build/bsps/arm/tms570/grp.yml
@@ -32,6 +32,18 @@ links:
   uid: optmintskstksz
 - role: build-dependency
   uid: optoscmain
+- role: build-dependency
+  uid: optgclk
+- role: build-dependency
+  uid: opthclk
+- role: build-dependency
+  uid: optvclk
+- role: build-dependency
+  uid: optvclk2
+- role: build-dependency
+  uid: optvclk3
+- role: build-dependency
+  uid: optrticlk
 - role: build-dependency
   uid: optreginit
 - role: build-dependency
diff --git a/spec/build/bsps/arm/tms570/optgclk.yml 
b/spec/build/bsps/arm/tms570/optgclk.yml
new file mode 100644
index 00..f7ec86a250
--- /dev/null
+++ b/spec/build/bsps/arm/tms570/optgclk.yml
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by:
+  - arm/tms570lc4357_hdk
+  - arm/tms570lc4357_hdk_sdram
+  value: 3
+- enabled-by: true
+  value: 16000
+description: |
+  The option value shall be the GCLK frequency in Hz.
+enabled-by: true
+format: '{}'
+links: []
+name: TMS570_GCLK_HZ
+type: build
diff --git a/spec/build/bsps/arm/tms570/opthclk.yml 
b/spec/build/bsps/arm/tms570/opthclk.yml
new file mode 100644
index 00..652c151eec
--- /dev/null
+++ b/spec/build/bsps/arm/tms570/opthclk.yml
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: 

[PATCH 3/9] bsps/cache: Fix ARM CP-15 get cache size

[Sebastian Huber]

The rtems_cache_get_data_cache_size() and
rtems_cache_get_instruction_cache_size() functions shall return the entire
cache size for a level of 0.  Levels greater than 0 shall return the size of
the associated level.

Update #4982.
---
 bsps/arm/shared/cache/cache-cp15.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/bsps/arm/shared/cache/cache-cp15.c 
b/bsps/arm/shared/cache/cache-cp15.c
index 92ccfcb276..8e0f22282b 100644
--- a/bsps/arm/shared/cache/cache-cp15.c
+++ b/bsps/arm/shared/cache/cache-cp15.c
@@ -222,12 +222,12 @@ static inline size_t arm_cp15_get_cache_size(
   clidr = arm_cp15_get_cache_level_id();
   loc = arm_clidr_get_level_of_coherency(clidr);
 
-  if (level >= loc) {
-return 0;
-  }
-
   if (level == 0) {
 level = loc - 1;
+  } else if (level - 1 >= loc) {
+return 0;
+  } else {
+--level;
   }
 
   ccsidr = arm_cp15_get_cache_size_id_for_level(
-- 
2.35.3

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[PATCH 2/9] bsps/cache: Simplify Cortex-R5 cache support

[Sebastian Huber]

Update #4982.
---
 bsps/arm/shared/cache/cache-cp15.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/bsps/arm/shared/cache/cache-cp15.c 
b/bsps/arm/shared/cache/cache-cp15.c
index 88fae2fb1f..92ccfcb276 100644
--- a/bsps/arm/shared/cache/cache-cp15.c
+++ b/bsps/arm/shared/cache/cache-cp15.c
@@ -54,6 +54,10 @@
   #define CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA
 #endif
 
+#if __ARM_ARCH == 7 && __ARM_ARCH_PROFILE == 'R'
+  #define CACHE_CP15_IS_CORTEX_R5
+#endif
+
 static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
 {
   arm_cache_l1_flush_1_data_line(d_addr);
@@ -128,7 +132,9 @@ static inline void _CPU_cache_unfreeze_instruction(void)
 static inline void _CPU_cache_flush_entire_data(void)
 {
   _ARM_Data_synchronization_barrier();
-#if __ARM_ARCH >= 7
+#if defined(CACHE_CP15_IS_CORTEX_R5)
+  arm_cp15_data_cache_clean_level(0);
+#elif __ARM_ARCH >= 7
   arm_cp15_data_cache_clean_all_levels();
 #else
   arm_cp15_data_cache_clean_and_invalidate();
@@ -139,7 +145,9 @@ static inline void _CPU_cache_flush_entire_data(void)
 
 static inline void _CPU_cache_invalidate_entire_data(void)
 {
-#if __ARM_ARCH >= 7
+#if defined(CACHE_CP15_IS_CORTEX_R5)
+  arm_cp15_data_cache_all_invalidate();
+#elif __ARM_ARCH >= 7
   arm_cp15_data_cache_invalidate_all_levels();
 #else
   arm_cp15_data_cache_invalidate();
-- 
2.35.3

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[PATCH 0/9] bsp/tms570 Improvements

[Sebastian Huber]

Sebastian Huber (9):
  arm: Add arm_cp15_data_cache_all_invalidate()
  bsps/cache: Simplify Cortex-R5 cache support
  bsps/cache: Fix ARM CP-15 get cache size
  bsp/tms570: Add TMS570LC4357 PLL support
  bsp/tms570: Add clock BSP options
  bsp/tms570: Fix clock driver
  bsp/tms570: Add TMS570_FATAL_RTI_IRQ_INSTALL
  bsp/tms570: Use RTI for CPU counter
  bsp/tms570: Use write-back/write-allocate SDRAM

 bsps/arm/shared/cache/cache-cp15.c|  20 ++-
 bsps/arm/tms570/clock/clock.c | 157 --
 bsps/arm/tms570/console/tms570-sci.c  |   2 +-
 bsps/arm/tms570/cpucounter/cpucounterread.c   |  83 -
 bsps/arm/tms570/include/bsp.h |   6 -
 bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h |  27 +++
 bsps/arm/tms570/start/tms570_sys_core.S   |   2 +-
 bsps/include/bsp/fatal.h  |   3 +
 .../score/cpu/arm/include/libcpu/arm-cp15.h   |  17 ++
 spec/build/bsps/arm/tms570/grp.yml|  12 ++
 spec/build/bsps/arm/tms570/obj.yml|   1 -
 spec/build/bsps/arm/tms570/optgclk.yml|  21 +++
 spec/build/bsps/arm/tms570/opthclk.yml|  21 +++
 spec/build/bsps/arm/tms570/optrticlk.yml  |  21 +++
 spec/build/bsps/arm/tms570/optvclk.yml|  21 +++
 spec/build/bsps/arm/tms570/optvclk2.yml   |  21 +++
 spec/build/bsps/arm/tms570/optvclk3.yml   |  21 +++
 17 files changed, 271 insertions(+), 185 deletions(-)
 delete mode 100644 bsps/arm/tms570/cpucounter/cpucounterread.c
 create mode 100644 spec/build/bsps/arm/tms570/optgclk.yml
 create mode 100644 spec/build/bsps/arm/tms570/opthclk.yml
 create mode 100644 spec/build/bsps/arm/tms570/optrticlk.yml
 create mode 100644 spec/build/bsps/arm/tms570/optvclk.yml
 create mode 100644 spec/build/bsps/arm/tms570/optvclk2.yml
 create mode 100644 spec/build/bsps/arm/tms570/optvclk3.yml

-- 
2.35.3

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[PATCH 6/6] bsps/arm: Fix Doxygen group assignment

[Sebastian Huber]

---
 bsps/arm/shared/cache/cache-cp15.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/bsps/arm/shared/cache/cache-cp15.c 
b/bsps/arm/shared/cache/cache-cp15.c
index d78ec4feb4..88fae2fb1f 100644
--- a/bsps/arm/shared/cache/cache-cp15.c
+++ b/bsps/arm/shared/cache/cache-cp15.c
@@ -3,9 +3,10 @@
 /**
  * @file
  *
- * @ingroup arm
+ * @ingroup RTEMSImplClassicCache
  *
- * @brief ARM cache defines and implementation.
+ * @brief This source file contains the Cache Manager implementation for
+ *   devices using the ARM CP15.
  */
 
 /*
-- 
2.35.3

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[PATCH 4/6] bsps/arm: Add Doxygen group for Armv7-M SysTick

[Sebastian Huber]

Change license to BSD-2-Clause according to file history and contributor
agreements.
---
 bsps/arm/include/bsp/clock-armv7m.h   | 49 +--
 bsps/arm/shared/clock/clock-armv7m.c  |  8 +++
 .../arm/shared/cpucounter/cpucounter-armv7m.c |  8 +++
 3 files changed, 61 insertions(+), 4 deletions(-)

diff --git a/bsps/arm/include/bsp/clock-armv7m.h 
b/bsps/arm/include/bsp/clock-armv7m.h
index 62f201153e..28adf34453 100644
--- a/bsps/arm/include/bsp/clock-armv7m.h
+++ b/bsps/arm/include/bsp/clock-armv7m.h
@@ -1,9 +1,37 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSDriverClockArmv7MSysTick
+ *
+ * @brief This header file provides support for Armv7-M clock drivers.
+ */
+
 /*
- * Copyright (c) 2011, 2018 Sebastian Huber.  All rights reserved.
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ * Copyright (C) 2011, 2018 Sebastian Huber
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef BSP_CLOCK_ARMV7M_H
@@ -18,6 +46,17 @@
 extern "C" {
 #endif /* __cplusplus */
 
+/**
+ * @defgroup RTEMSDriverClockArmv7MSysTick Armv7-M SysTick Clock Driver
+ *
+ * @ingroup RTEMSDriverClockImpl
+ *
+ * @brief This group contains the Armv7-M SysTick support and Clock Driver
+ *   implementation.
+ *
+ * @{
+ */
+
 #ifdef ARM_MULTILIB_ARCH_V7M
 
 typedef struct {
@@ -67,6 +106,8 @@ static uint32_t _ARMV7M_Clock_counter(ARMV7M_Timecounter *tc)
 
 #endif /* ARM_MULTILIB_ARCH_V7M */
 
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
diff --git a/bsps/arm/shared/clock/clock-armv7m.c 
b/bsps/arm/shared/clock/clock-armv7m.c
index ce1d3b38bd..ee3b8a7939 100644
--- a/bsps/arm/shared/clock/clock-armv7m.c
+++ b/bsps/arm/shared/clock/clock-armv7m.c
@@ -1,5 +1,13 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSDriverClockArmv7MSysTick
+ *
+ * @brief This source file contains the Armv7-M SysTick Clock Driver.
+ */
+
 /*
  * Copyright (C) 2020 embedded brains GmbH & Co. KG
  * Copyright (C) 2011, 2018 Sebastian Huber
diff --git a/bsps/arm/shared/cpucounter/cpucounter-armv7m.c 
b/bsps/arm/shared/cpucounter/cpucounter-armv7m.c
index f43ad42248..95fdee365c 100644
--- a/bsps/arm/shared/cpucounter/cpucounter-armv7m.c
+++ b/bsps/arm/shared/cpucounter/cpucounter-armv7m.c
@@ -1,5 +1,13 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSDriverClockArmv7MSysTick
+ *
+ * @brief This source file contains the Armv7-M SysTick CPU counter.
+ */
+
 /*
  * Copyright (C) 2016, 2018 embedded brains GmbH & Co. KG
  *
-- 
2.35.3

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[PATCH 5/6] bsps/arm: Add CMSIS files to Doxygen group

[Sebastian Huber]

---
 bsps/arm/shared/doxygen.h | 56 +++
 1 file changed, 56 insertions(+)

diff --git a/bsps/arm/shared/doxygen.h b/bsps/arm/shared/doxygen.h
index 469928d712..8dbf129f07 100644
--- a/bsps/arm/shared/doxygen.h
+++ b/bsps/arm/shared/doxygen.h
@@ -29,3 +29,59 @@
  *
  * @brief Cortex Microcontroller Software Interface Standard (CMSIS).
  */
+
+/**
+ * @file cachel1_armv7.h
+ *
+ * @ingroup CMSIS
+ *
+ * @brief This header file provides CMSIS interfaces.
+ */
+
+/**
+ * @file cmsis_compiler.h
+ *
+ * @ingroup CMSIS
+ *
+ * @brief This header file provides CMSIS interfaces.
+ */
+
+/**
+ * @file cmsis_gcc.h
+ *
+ * @ingroup CMSIS
+ *
+ * @brief This header file provides CMSIS interfaces.
+ */
+
+/**
+ * @file cmsis_version.h
+ *
+ * @ingroup CMSIS
+ *
+ * @brief This header file provides CMSIS interfaces.
+ */
+
+/**
+ * @file core_cm4.h
+ *
+ * @ingroup CMSIS
+ *
+ * @brief This header file provides CMSIS interfaces.
+ */
+
+/**
+ * @file core_cm7.h
+ *
+ * @ingroup CMSIS
+ *
+ * @brief This header file provides CMSIS interfaces.
+ */
+
+/**
+ * @file mpu_armv7.h
+ *
+ * @ingroup CMSIS
+ *
+ * @brief This header file provides CMSIS interfaces.
+ */
-- 
2.35.3

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[PATCH 3/6] bsps/aarch64: Define Doxygen groups

[Sebastian Huber]

Fix typos.
---
 bsps/aarch64/include/bsp/linker-symbols.h |  2 +-
 bsps/aarch64/include/bsp/start.h  |  2 +-
 bsps/aarch64/shared/doxygen.h | 23 +++
 3 files changed, 25 insertions(+), 2 deletions(-)
 create mode 100644 bsps/aarch64/shared/doxygen.h

diff --git a/bsps/aarch64/include/bsp/linker-symbols.h 
b/bsps/aarch64/include/bsp/linker-symbols.h
index 222c217abb..c550bd9eba 100644
--- a/bsps/aarch64/include/bsp/linker-symbols.h
+++ b/bsps/aarch64/include/bsp/linker-symbols.h
@@ -46,7 +46,7 @@ extern "C" {
 /**
  * @defgroup aarch64_linker Linker Support
  *
- * @ingroup RTEMSBSPsAARCH64Shared
+ * @ingroup RTEMSBSPsAArch64Shared
  *
  * @brief Linker support.
  *
diff --git a/bsps/aarch64/include/bsp/start.h b/bsps/aarch64/include/bsp/start.h
index f0af5be841..bd46087949 100644
--- a/bsps/aarch64/include/bsp/start.h
+++ b/bsps/aarch64/include/bsp/start.h
@@ -48,7 +48,7 @@ extern "C" {
 /**
  * @defgroup aarch64_start System Start
  *
- * @ingroup RTEMSBSPsAarch64Shared
+ * @ingroup RTEMSBSPsAArch64Shared
  *
  * @brief Aarch64 system low level start.
  *
diff --git a/bsps/aarch64/shared/doxygen.h b/bsps/aarch64/shared/doxygen.h
new file mode 100644
index 00..5f639f5008
--- /dev/null
+++ b/bsps/aarch64/shared/doxygen.h
@@ -0,0 +1,23 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSImplDoxygen
+ *
+ * @brief This header file defines BSP-specific groups.
+ */
+
+/**
+ * @defgroup RTEMSBSPsAArch64 AArch64
+ *
+ * @ingroup RTEMSBSPs
+ *
+ * @brief This group contains AArch64 Board Support Packages.
+ */
+
+/**
+ * @defgroup RTEMSBSPsAArch64Shared Shared
+ *
+ * @ingroup RTEMSBSPsAArch64
+ *
+ * @brief This group contains support shared by AArch64 Board Support Packages.
+ */
-- 
2.35.3

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[PATCH 2/6] aarch64: Add files to Doxygen groups

[Sebastian Huber]

---
 cpukit/score/cpu/aarch64/aarch64-thread-idle.c |  7 +--
 cpukit/score/cpu/aarch64/include/rtems/asm.h   |  5 -
 .../include/rtems/score/aarch64-system-registers.h |  2 ++
 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 10 +++---
 4 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/cpukit/score/cpu/aarch64/aarch64-thread-idle.c 
b/cpukit/score/cpu/aarch64/aarch64-thread-idle.c
index ce93b4facd..cbaa29a166 100644
--- a/cpukit/score/cpu/aarch64/aarch64-thread-idle.c
+++ b/cpukit/score/cpu/aarch64/aarch64-thread-idle.c
@@ -1,9 +1,12 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
 /**
- *  @file
+ * @file
  *
- *  @brief CPU Thread Idle Body
+ * @ingroup RTEMSScoreCPUAArch64
+ *
+ * @brief This source file contains the AArch64-specific
+ *   _CPU_Thread_Idle_body() implementation.
  */
 
 /*
diff --git a/cpukit/score/cpu/aarch64/include/rtems/asm.h 
b/cpukit/score/cpu/aarch64/include/rtems/asm.h
index fa53e08291..1870af97d2 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/asm.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/asm.h
@@ -3,7 +3,10 @@
 /**
  * @file
  *
- * @brief AArch64 Assembler Support API
+ * @ingroup RTEMSScoreCPUAArch64ASM
+ *
+ * @brief This header file provides interfaces to address problems caused by
+ *   incompatible flavor of assemblers and toolsets.
  *
  * This include file attempts to address the problems
  * caused by incompatible flavors of assemblers and
diff --git 
a/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h 
b/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h
index 8ddad5becf..364ff8e836 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h
@@ -3,6 +3,8 @@
 /**
  * @file
  *
+ * @ingroup RTEMSScoreCPUAArch64
+ *
  * @brief This header file provides the API to read and write the AArch64
  *   system registers.
  */
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h 
b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index aa4f90f1a8..8a8e80832f 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -3,9 +3,9 @@
 /**
  * @file
  *
- * @ingroup RTEMSScoreCPU
+ * @ingroup RTEMSScoreCPUAArch64
  *
- * @brief AArch64 Architecture Support API
+ * @brief This header file provides interfaces of the AArch64 CPU port.
  */
 
 /*
@@ -46,7 +46,11 @@
 #include 
 
 /**
- * @addtogroup RTEMSScoreCPUAArch64
+ * @defgroup RTEMSScoreCPUAArch64 AArch64
+ *
+ * @ingroup RTEMSScoreCPU
+ *
+ * @brief This group contains the AArch64 CPU port.
  *
  * @{
  */
-- 
2.35.3

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[PATCH 0/6] Doxygen improvements

[Sebastian Huber]

Sebastian Huber (6):
  bsps: Add Doxygen group for Arm Generic Timer
  aarch64: Add files to Doxygen groups
  bsps/aarch64: Define Doxygen groups
  bsps/arm: Add Doxygen group for Armv7-M SysTick
  bsps/arm: Add CMSIS files to Doxygen group
  bsps/arm: Fix Doxygen group assignment

 bsps/aarch64/include/bsp/linker-symbols.h |  2 +-
 bsps/aarch64/include/bsp/start.h  |  2 +-
 bsps/aarch64/shared/doxygen.h | 23 
 bsps/arm/include/bsp/clock-armv7m.h   | 49 ++--
 bsps/arm/shared/cache/cache-cp15.c|  5 +-
 bsps/arm/shared/clock/clock-armv7m.c  |  8 +++
 .../arm/shared/cpucounter/cpucounter-armv7m.c |  8 +++
 bsps/arm/shared/doxygen.h | 56 +++
 bsps/shared/dev/clock/arm-generic-timer.c | 26 -
 .../score/cpu/aarch64/aarch64-thread-idle.c   |  7 ++-
 cpukit/score/cpu/aarch64/include/rtems/asm.h  |  5 +-
 .../rtems/score/aarch64-system-registers.h|  2 +
 .../cpu/aarch64/include/rtems/score/cpu.h | 10 +++-
 13 files changed, 186 insertions(+), 17 deletions(-)
 create mode 100644 bsps/aarch64/shared/doxygen.h

-- 
2.35.3

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[PATCH 1/6] bsps: Add Doxygen group for Arm Generic Timer

[Sebastian Huber]

---
 bsps/shared/dev/clock/arm-generic-timer.c | 26 ---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/bsps/shared/dev/clock/arm-generic-timer.c 
b/bsps/shared/dev/clock/arm-generic-timer.c
index 44cf1ebe6c..b2842df175 100644
--- a/bsps/shared/dev/clock/arm-generic-timer.c
+++ b/bsps/shared/dev/clock/arm-generic-timer.c
@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSDriverClockArmGenericTimer
+ *
+ * @brief This source file contains a Clock Driver implementation using
+ *   Armv7-AR/AArch64 Generic Timer.
+ */
+
 /*
  * Copyright (c) 2017 embedded brains GmbH & Co. KG
  *
@@ -36,14 +45,23 @@
 #include 
 #include 
 
-/*
- * Clock driver using the ARMv7-AR/AArch64 Generic Timer.  The BSP must 
provide the
- * following function:
+/**
+ * @defgroup RTEMSDriverClockArmGenericTimer \
+ *   Armv7-AR/AArch64 Generic Timer Clock Driver
+ *
+ * @ingroup RTEMSDriverClockImpl
+ *
+ * @brief This group contains the Armv7-AR/AArch64 Generic Timer Clock Driver
+ *   implementation.
+ *
+ * The BSP must provide the following function:
  *
  * void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq);
  *
  * The BSP may optionally define ARM_GENERIC_TIMER_USE_VIRTUAL in  to
  * use the virtual timer instead of the physical timer.
+ *
+ * @{
  */
 
 typedef struct {
@@ -197,5 +215,7 @@ RTEMS_SYSINIT_ITEM(
 #define Clock_driver_support_install_isr(isr) \
   arm_gt_clock_handler_install(isr)
 
+/** @} */
+
 /* Include shared source clock driver code */
 #include "../../shared/dev/clock/clockimpl.h"
-- 
2.35.3

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[PATCH 3/3] bsps/arm: Move BSP-specific header file

[Sebastian Huber]

---
 bsps/arm/{ => edb7312}/include/uart.h  | 0
 spec/build/bsps/arm/edb7312/bspedb7312.yml | 1 +
 spec/build/bsps/arm/grp.yml| 1 -
 3 files changed, 1 insertion(+), 1 deletion(-)
 rename bsps/arm/{ => edb7312}/include/uart.h (100%)

diff --git a/bsps/arm/include/uart.h b/bsps/arm/edb7312/include/uart.h
similarity index 100%
rename from bsps/arm/include/uart.h
rename to bsps/arm/edb7312/include/uart.h
diff --git a/spec/build/bsps/arm/edb7312/bspedb7312.yml 
b/spec/build/bsps/arm/edb7312/bspedb7312.yml
index a86000cbc5..9461841aa4 100644
--- a/spec/build/bsps/arm/edb7312/bspedb7312.yml
+++ b/spec/build/bsps/arm/edb7312/bspedb7312.yml
@@ -14,6 +14,7 @@ install:
   source:
   - bsps/arm/edb7312/include/bsp.h
   - bsps/arm/edb7312/include/ep7312.h
+  - bsps/arm/edb7312/include/uart.h
 - destination: ${BSP_INCLUDEDIR}/bsp
   source:
   - bsps/arm/edb7312/include/bsp/irq.h
diff --git a/spec/build/bsps/arm/grp.yml b/spec/build/bsps/arm/grp.yml
index 6979e02fb2..1086e0f7ab 100644
--- a/spec/build/bsps/arm/grp.yml
+++ b/spec/build/bsps/arm/grp.yml
@@ -17,7 +17,6 @@ install:
   - bsps/arm/include/core_cm7.h
   - bsps/arm/include/core_cm4.h
   - bsps/arm/include/mpu_armv7.h
-  - bsps/arm/include/uart.h
 - destination: ${BSP_INCLUDEDIR}/bsp
   source:
   - bsps/arm/include/bsp/arm-a9mpcore-clock.h
-- 
2.35.3

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[PATCH 2/3] bsps/arm: Use shared object for ARM920 MMU support

[Sebastian Huber]

---
 spec/build/bsps/arm/csb336/bspcsb336.yml |  3 ++-
 spec/build/bsps/arm/csb337/grp.yml   |  2 ++
 spec/build/bsps/arm/csb337/obj.yml   |  1 -
 spec/build/bsps/arm/grp.yml  |  3 ---
 spec/build/bsps/arm/gumstix/bspgumstix.yml   |  3 ++-
 spec/build/bsps/arm/objarm920mmu.yml | 17 +
 spec/build/bsps/arm/smdk2410/bspsmdk2410.yml |  3 ++-
 7 files changed, 25 insertions(+), 7 deletions(-)
 create mode 100644 spec/build/bsps/arm/objarm920mmu.yml

diff --git a/spec/build/bsps/arm/csb336/bspcsb336.yml 
b/spec/build/bsps/arm/csb336/bspcsb336.yml
index edfd813227..7028925662 100644
--- a/spec/build/bsps/arm/csb336/bspcsb336.yml
+++ b/spec/build/bsps/arm/csb336/bspcsb336.yml
@@ -28,6 +28,8 @@ links:
   uid: start
 - role: build-dependency
   uid: ../grp
+- role: build-dependency
+  uid: ../objarm920mmu
 - role: build-dependency
   uid: ../../obj
 - role: build-dependency
@@ -46,7 +48,6 @@ source:
 - bsps/arm/csb336/start/bspstart.c
 - bsps/arm/csb336/start/memmap.c
 - bsps/arm/shared/cache/cache-cp15.c
-- bsps/arm/shared/cp15/arm920-mmu.c
 - bsps/shared/dev/cpucounter/cpucounterfrequency.c
 - bsps/shared/dev/cpucounter/cpucounterread.c
 - bsps/shared/dev/getentropy/getentropy-cpucounter.c
diff --git a/spec/build/bsps/arm/csb337/grp.yml 
b/spec/build/bsps/arm/csb337/grp.yml
index 47c3b68a26..7a8602aea4 100644
--- a/spec/build/bsps/arm/csb337/grp.yml
+++ b/spec/build/bsps/arm/csb337/grp.yml
@@ -40,6 +40,8 @@ links:
   uid: start
 - role: build-dependency
   uid: ../grp
+- role: build-dependency
+  uid: ../objarm920mmu
 - role: build-dependency
   uid: ../../linkcmds
 - role: build-dependency
diff --git a/spec/build/bsps/arm/csb337/obj.yml 
b/spec/build/bsps/arm/csb337/obj.yml
index 3858e4f00d..d817e08a58 100644
--- a/spec/build/bsps/arm/csb337/obj.yml
+++ b/spec/build/bsps/arm/csb337/obj.yml
@@ -42,7 +42,6 @@ source:
 - bsps/arm/csb337/start/memmap.c
 - bsps/arm/csb337/start/pmc.c
 - bsps/arm/shared/cache/cache-cp15.c
-- bsps/arm/shared/cp15/arm920-mmu.c
 - bsps/shared/dev/cpucounter/cpucounterfrequency.c
 - bsps/shared/dev/cpucounter/cpucounterread.c
 - bsps/shared/dev/getentropy/getentropy-cpucounter.c
diff --git a/spec/build/bsps/arm/grp.yml b/spec/build/bsps/arm/grp.yml
index ff4ff854ee..6979e02fb2 100644
--- a/spec/build/bsps/arm/grp.yml
+++ b/spec/build/bsps/arm/grp.yml
@@ -47,9 +47,6 @@ install:
   - bsps/include/dev/irq/arm-gic-regs.h
   - bsps/include/dev/irq/arm-gic-tm27.h
   - bsps/include/dev/irq/arm-gic.h
-- destination: ${BSP_INCLUDEDIR}/libcpu
-  source:
-  - bsps/arm/include/libcpu/mmu.h
 - destination: ${BSP_LIBDIR}
   source:
   - bsps/arm/shared/start/linkcmds.armv4
diff --git a/spec/build/bsps/arm/gumstix/bspgumstix.yml 
b/spec/build/bsps/arm/gumstix/bspgumstix.yml
index 7946a64ed4..2b40b50e0e 100644
--- a/spec/build/bsps/arm/gumstix/bspgumstix.yml
+++ b/spec/build/bsps/arm/gumstix/bspgumstix.yml
@@ -30,6 +30,8 @@ links:
   uid: optskyeye
 - role: build-dependency
   uid: start
+- role: build-dependency
+  uid: ../objarm920mmu
 - role: build-dependency
   uid: ../../obj
 - role: build-dependency
@@ -50,7 +52,6 @@ source:
 - bsps/arm/gumstix/start/bspreset.c
 - bsps/arm/gumstix/start/bspstart.c
 - bsps/arm/gumstix/start/memmap.c
-- bsps/arm/shared/cp15/arm920-mmu.c
 - bsps/shared/cache/nocache.c
 - bsps/shared/dev/cpucounter/cpucounterfrequency.c
 - bsps/shared/dev/cpucounter/cpucounterread.c
diff --git a/spec/build/bsps/arm/objarm920mmu.yml 
b/spec/build/bsps/arm/objarm920mmu.yml
new file mode 100644
index 00..f440a15d7d
--- /dev/null
+++ b/spec/build/bsps/arm/objarm920mmu.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/libcpu
+  source:
+  - bsps/arm/include/libcpu/mmu.h
+links: []
+source:
+- bsps/arm/shared/cp15/arm920-mmu.c
+type: build
diff --git a/spec/build/bsps/arm/smdk2410/bspsmdk2410.yml 
b/spec/build/bsps/arm/smdk2410/bspsmdk2410.yml
index ec7dc73af4..967bd8b87e 100644
--- a/spec/build/bsps/arm/smdk2410/bspsmdk2410.yml
+++ b/spec/build/bsps/arm/smdk2410/bspsmdk2410.yml
@@ -34,6 +34,8 @@ links:
   uid: optskyeye
 - role: build-dependency
   uid: start
+- role: build-dependency
+  uid: ../objarm920mmu
 - role: build-dependency
   uid: ../../obj
 - role: build-dependency
@@ -46,7 +48,6 @@ links:
   uid: ../../bspopts
 source:
 - bsps/arm/shared/cache/cache-cp15.c
-- bsps/arm/shared/cp15/arm920-mmu.c
 - bsps/arm/smdk2410/btimer/btimer.c
 - bsps/arm/smdk2410/clock/clockdrv.c
 - bsps/arm/smdk2410/clock/support.c
-- 
2.35.3

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[PATCH 1/3] bsps/arm: Move BSP-specific header file installs

[Sebastian Huber]

---
 spec/build/bsps/arm/beagle/obj.yml | 5 +
 spec/build/bsps/arm/grp.yml| 3 ---
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/spec/build/bsps/arm/beagle/obj.yml 
b/spec/build/bsps/arm/beagle/obj.yml
index 0f2f354ab9..eaaf09f6ac 100644
--- a/spec/build/bsps/arm/beagle/obj.yml
+++ b/spec/build/bsps/arm/beagle/obj.yml
@@ -21,6 +21,11 @@ install:
   - bsps/arm/beagle/include/bsp/pwmss.h
   - bsps/arm/beagle/include/bsp/qep.h
   - bsps/arm/beagle/include/bsp/spi.h
+- destination: ${BSP_INCLUDEDIR}/libcpu
+  source:
+  - bsps/arm/include/libcpu/am335x.h
+  - bsps/arm/include/libcpu/omap3.h
+  - bsps/arm/include/libcpu/omap_timer.h
 - destination: ${BSP_LIBDIR}
   source:
   - bsps/arm/beagle/start/linkcmds
diff --git a/spec/build/bsps/arm/grp.yml b/spec/build/bsps/arm/grp.yml
index a48cd80d74..ff4ff854ee 100644
--- a/spec/build/bsps/arm/grp.yml
+++ b/spec/build/bsps/arm/grp.yml
@@ -49,10 +49,7 @@ install:
   - bsps/include/dev/irq/arm-gic.h
 - destination: ${BSP_INCLUDEDIR}/libcpu
   source:
-  - bsps/arm/include/libcpu/am335x.h
   - bsps/arm/include/libcpu/mmu.h
-  - bsps/arm/include/libcpu/omap3.h
-  - bsps/arm/include/libcpu/omap_timer.h
 - destination: ${BSP_LIBDIR}
   source:
   - bsps/arm/shared/start/linkcmds.armv4
-- 
2.35.3

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[PATCH 0/3] Build optimizations for arm BSPs

[Sebastian Huber]

Sebastian Huber (3):
  bsps/arm: Move BSP-specific header file installs
  bsps/arm: Use shared object for ARM920 MMU support
  bsps/arm: Move BSP-specific header file

 bsps/arm/{ => edb7312}/include/uart.h|  0
 spec/build/bsps/arm/beagle/obj.yml   |  5 +
 spec/build/bsps/arm/csb336/bspcsb336.yml |  3 ++-
 spec/build/bsps/arm/csb337/grp.yml   |  2 ++
 spec/build/bsps/arm/csb337/obj.yml   |  1 -
 spec/build/bsps/arm/edb7312/bspedb7312.yml   |  1 +
 spec/build/bsps/arm/grp.yml  |  7 ---
 spec/build/bsps/arm/gumstix/bspgumstix.yml   |  3 ++-
 spec/build/bsps/arm/objarm920mmu.yml | 17 +
 spec/build/bsps/arm/smdk2410/bspsmdk2410.yml |  3 ++-
 10 files changed, 31 insertions(+), 11 deletions(-)
 rename bsps/arm/{ => edb7312}/include/uart.h (100%)
 create mode 100644 spec/build/bsps/arm/objarm920mmu.yml

-- 
2.35.3

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[PATCH] bsps: Use interrupt entry in clock driver

[Sebastian Huber]

This avoids a dependency on memory allocations.
---
 bsps/shared/dev/clock/arm-generic-timer.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/bsps/shared/dev/clock/arm-generic-timer.c 
b/bsps/shared/dev/clock/arm-generic-timer.c
index ba159f6833..44cf1ebe6c 100644
--- a/bsps/shared/dev/clock/arm-generic-timer.c
+++ b/bsps/shared/dev/clock/arm-generic-timer.c
@@ -68,16 +68,22 @@ static void arm_gt_clock_at_tick(arm_gt_clock_context *ctx)
 #endif /* ARM_GENERIC_TIMER_UNMASK_AT_TICK */
 }
 
+static rtems_interrupt_entry arm_gt_interrupt_entry;
+
 static void arm_gt_clock_handler_install(rtems_interrupt_handler handler)
 {
   rtems_status_code sc;
 
-  sc = rtems_interrupt_handler_install(
+  rtems_interrupt_entry_initialize(
+_gt_interrupt_entry,
+handler,
+_gt_clock_instance,
+"Clock"
+  );
+  sc = rtems_interrupt_entry_install(
 arm_gt_clock_instance.irq,
-"Clock",
 RTEMS_INTERRUPT_UNIQUE,
-handler,
-_gt_clock_instance
+_gt_interrupt_entry
   );
   if (sc != RTEMS_SUCCESSFUL) {
 bsp_fatal(BSP_ARM_FATAL_GENERIC_TIMER_CLOCK_IRQ_INSTALL);
-- 
2.35.3

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Re: RTEMS 6 branching

[Sebastian Huber]

- Am 21. Apr 2024 um 3:00 schrieb Chris Johns chr...@rtems.org:

> Hi,
> 
> There has been some discussion about when we will branch and it is timely we
> discuss this. This is my input. :)
> 
> While I create the releases I am not solely responsible for milestone dates or
> thresholds for a release.
> 
> Please test the RC snaphots on our ftp server. Saying you have is as important
> as reporting issues.
> 
> 1. Are all the things need for the release resolved? Tickets reviewed?

It would be nice to have the interrupt get/set priority API in RTEMS 6. The 
Cortex-M floating point issue is not yet fixed in the RTEMS master.

> 
> 2. The tickets are now in GitLab and locked down in Trac so how does that work
> if we make a release now? I do not think it does.
> 
> 3. GitLab is going to happen soon so do we take this moment in time and make 6
> with GitLab and learn what we need to do easing dot releases that always 
> follow?
> If we do not we may end up with 6.1 and then 6.2 that has differences.

We should definitely wait with the release after the Gitlab migration is done 
and some basic CI is running.

> 
> 4. GitLab breaks the release scripts for the release notes (ChangeLog). Amar 
> and
> I have discussed a few options but we are yet to test and settle on anything. 
> As
> is the case with these things easy is often is a series of small things that
> take time to get right.
> 
> 5. Have the docs been reviewed for RTEMS 5 vs RTEMS 6 changes? Are they 
> updated
> for a separated legacy network stack, net services and waf building?
> 
> 6. I have a few small patches to push and then an update to the RSB to pick
> those changes up before I can create RC4.

I recently checked in a fix for powerpc and the AArch64 multilib changes for 
Cortex-A53 in GCC 13. To pick this up, the GCC commit needs to be updated. 
Maybe we should even wait for the GCC 13.3 release.

> 
> 
> Thanks
> Chris
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Re: [PATCH] Fix the CPU count calculation error.

[Sebastian Huber]

On 19.04.24 09:16, zhengxiaojun wrote:
I tested on arm64, the cpu_count do not increase when (redist->icrtyper 
& GIC_REDIST_ICRTYPER_LAST != 0)，but it is the last core.


The current code assumes that you have exactly one interrupt export 
port. With which SoC are you working currently? One option could be to 
make the number of interrupt export ports configurable.


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Re: [PATCH] Fix the CPU count calculation error.

[Sebastian Huber]

Hello,

on which platform does this fix a error?

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Re: 6.1rc3 CentOS 7 Build Sweep Report

[Sebastian Huber]

Hallo Joel,

it would be nice to have the interrupt get/set priority directives in 
RTEMS 6. When do you want to create the RTEMS 6 branch?


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Re: [RFC] rtems: Add options to kernel output char handler

[Sebastian Huber]

On 18.04.24 04:02, Chris Johns wrote:

On 17/4/2024 11:06 pm, Sebastian Huber wrote:

Make the kernel I/O output character device processing configurable
through an option set parameter.  Add RTEMS_NO_OUTPUT and RTEMS_FLUSH
options.  The goal of this API change is to enable flushing the kernel
output device in the system termination process before a reset is
issued.  A use case for using RTEMS_NO_WAIT is the polled processing of
an input and output stream from and to the I/O device.


Thanks for providing this overview.

I am still confused about the differences in terms of why you would need the
RTEMS_NO_WAIT. Do you have a specific application where this is required? It
might help me understand the need for the change? Examples are need to reset in
a specific period, a test mode you are running in a system, etc?


The RTEMS_NO_WAIT can be used to process an input stream using 
getchark() and then send responses using a non-blocking output char 
variant. This helps to have enough processing time and allows an 
overlapping send/receive.




Is this change for RTEMS 7?


Yes, this would be good.



In the context of the change:

1. RTEMS_FLUSH etc are too generic.


I added them to , so they could be reused in 
other directives. A bit less generic names could be:


* RTEMS_IO_FLUSH

* RTEMS_IO_DRAIN

* RTEMS_IO_NO_OUTPUT

This would be in the IO namespace similar to RTEMS_EVENT_ANY and 
RTEMS_EVENT_ALL.




2. The language used needs some work, maybe fewer "while"s. For example:

  While the #RTEMS_NO_WAIT option is set in the option_set parameter, while
  the #RTEMS_NO_OUTPUT option is cleared in the option_set parameter, while
  the device can immediately accept a character for output, the character in
  out shall be hand over to the device for output.

This is difficult to read and when it is probability easier to read the code it
is of questionable value. I appreciate it is not always easy to write but I feel
clarity would be a good to have here.


This is the documentation of a function pointer type, so there is no 
direct code. With three flags, you have to specify for eight variants 
what should happen. The wording is in EARS. It should be easy to 
translate this into code for a particular device.


https://docs.rtems.org/branches/master/eng/req/req-for-req.html#syntax



Another example:

  While no character is available in the device, a polled
  character input functions shall return minus one.

It could be written as:

  A polled character input function shall return a character if the device
  has successfully received one else the function returns minus one.


I would prefer the EARS variant. This function type should define 
requirements for the associated implementations.




I think receive and transmit is better than for example "be hand over to the
device for output", maybe "shall be transmitted by the device".


The name of this function type is BSP_output_char_function_type and not 
BSP_transmit_char_function_type, so I used "output" here and not 
"transmit". Also, the character may not get immediately transmitted if 
FIFOs are involved (thus the need for the flush). Maybe my understanding 
of transmitted is wrong, but for me transmitting has something to do 
with signals on a medium.




3. Flush needs to be worded in terms of successfully transmitted by the device
to avoid the case of data being written to the device is held in FIFOs awaiting
transmission and reset is asserted. Maybe FLUSH is the wrong term because it is
so overloaded in what it means? An alternative could be
RTEMS_BSP_IO_TRANSMISSION_COMPLETE? And following on you could have
RTEMS_BSP_IO_NO_TRANSMISSION? The key point is "transmission" relates to the
external data pin of the interface.


The no-output option is used to just flush the device without 
transmitting a new character. For the flush, we could add something like 
this:


Flushing the device should ensure that all characters handed over to the 
device for output are visible to external consumers. For example, the 
device output FIFO and transmit shift registers should be empty.




Chris


---
  cpukit/include/rtems/bspIo.h | 50 ++--
  cpukit/include/rtems/rtems/options.h | 20 ++-
  2 files changed, 67 insertions(+), 3 deletions(-)

diff --git a/cpukit/include/rtems/bspIo.h b/cpukit/include/rtems/bspIo.h
index 31580cd800..09a3c47243 100644
--- a/cpukit/include/rtems/bspIo.h
+++ b/cpukit/include/rtems/bspIo.h
@@ -10,7 +10,7 @@
   */
  
  /*

- * Copyright (C) 2020, 2021 embedded brains GmbH & Co. KG
+ * Copyright (C) 2020, 2024 embedded brains GmbH & Co. KG
   * Copyright (C) 2015 On-Line Applications Research Corporation (OAR)
   *
   * Redistribution and use in source and binary forms, with or without
@@ -58,6 +58,8 @@
  #define _RTEMS_BSPIO_H
  
  #include 

+#include 
+#include 
  #include 
  
  #ifdef __cplusplus

@@ -89,8 +91,42 @@ extern "

[RFC] rtems: Add options to kernel output char handler

[Sebastian Huber]

Make the kernel I/O output character device processing configurable
through an option set parameter.  Add RTEMS_NO_OUTPUT and RTEMS_FLUSH
options.  The goal of this API change is to enable flushing the kernel
output device in the system termination process before a reset is
issued.  A use case for using RTEMS_NO_WAIT is the polled processing of
an input and output stream from and to the I/O device.
---
 cpukit/include/rtems/bspIo.h | 50 ++--
 cpukit/include/rtems/rtems/options.h | 20 ++-
 2 files changed, 67 insertions(+), 3 deletions(-)

diff --git a/cpukit/include/rtems/bspIo.h b/cpukit/include/rtems/bspIo.h
index 31580cd800..09a3c47243 100644
--- a/cpukit/include/rtems/bspIo.h
+++ b/cpukit/include/rtems/bspIo.h
@@ -10,7 +10,7 @@
  */
 
 /*
- * Copyright (C) 2020, 2021 embedded brains GmbH & Co. KG
+ * Copyright (C) 2020, 2024 embedded brains GmbH & Co. KG
  * Copyright (C) 2015 On-Line Applications Research Corporation (OAR)
  *
  * Redistribution and use in source and binary forms, with or without
@@ -58,6 +58,8 @@
 #define _RTEMS_BSPIO_H
 
 #include 
+#include 
+#include 
 #include 
 
 #ifdef __cplusplus
@@ -89,8 +91,42 @@ extern "C" {
  * @ingroup RTEMSAPIKernelCharIO
  *
  * @brief Polled character output functions shall have this type.
+ *
+ * @param out is the character to output.
+ *
+ * @param option_set is the option set.
+ *
+ * While the #RTEMS_NO_WAIT option is set in the option_set parameter, while
+ * the device cannot immediately accept a character for output, the character
+ * in out shall not be hand over to the device for output, optionally the
+ * device output shall be flushed, and ::RTEMS_UNSATISFIED shall be returned.
+ *
+ * While the #RTEMS_NO_OUTPUT option is set in the option_set parameter, the
+ * character in the out parameter shall not be handed over to the device for
+ * output.
+ *
+ * While the #RTEMS_NO_WAIT option is cleared in the option_set parameter,
+ * while the #RTEMS_NO_OUTPUT option is cleared in the option_set parameter,
+ * the character in the out parameter shall be hand over to the device for
+ * output.
+ *
+ * While the #RTEMS_NO_WAIT option is set in the option_set parameter, while
+ * the #RTEMS_NO_OUTPUT option is cleared in the option_set parameter, while
+ * the device can immediately accept a character for output, the character in
+ * out shall be hand over to the device for output.
+ *
+ * While the #RTEMS_FLUSH option is set in the option_set parameter, the device
+ * output shall be flushed before the function returns.
+ *
+ * @retval ::RTEMS_SUCCESSFUL The requested operation was successful.
+ *
+ * @retval ::RTEMS_UNSATISFIED The device is was not ready to output a
+ *   character.
  */
-typedef void ( *BSP_output_char_function_type )( char );
+typedef rtems_status_code ( *BSP_output_char_function_type )(
+  char out,
+  rtems_option option_set
+);
 
 /* Generated from spec:/rtems/io/if/bsp-output-char */
 
@@ -333,6 +369,16 @@ int rtems_printk_printer( void *unused, const char *fmt, 
va_list ap );
  * @ingroup RTEMSAPIKernelCharIO
  *
  * @brief Polled character input functions shall have this type.
+ *
+ * While a character is available in the device, a polled character input
+ * function shall return the least recently received character as an unsigned
+ * character.  While no character is available in the device, a polled
+ * character input functions shall return minus one.
+ *
+ * @retval -1 There was no input character available in the device.
+ *
+ * @return Returns the least recently received character available in the
+ *   device as an unsigned character.
  */
 typedef int (* BSP_polling_getchar_function_type )( void );
 
diff --git a/cpukit/include/rtems/rtems/options.h 
b/cpukit/include/rtems/rtems/options.h
index 44a8d6ccb8..3522fc4fcd 100644
--- a/cpukit/include/rtems/rtems/options.h
+++ b/cpukit/include/rtems/rtems/options.h
@@ -9,7 +9,7 @@
  */
 
 /*
- * Copyright (C) 2020 embedded brains GmbH & Co. KG
+ * Copyright (C) 2020, 2024 embedded brains GmbH & Co. KG
  * Copyright (C) 1989, 2008 On-Line Applications Research Corporation (OAR)
  *
  * Redistribution and use in source and binary forms, with or without
@@ -103,6 +103,24 @@ extern "C" {
  */
 #define RTEMS_EVENT_ANY 0x0002
 
+/* Generated from spec:/rtems/option/if/flush */
+
+/**
+ * @ingroup RTEMSAPIClassicOptions
+ *
+ * @brief This option constant indicates that something shall be flushed.
+ */
+#define RTEMS_FLUSH 0x0008
+
+/* Generated from spec:/rtems/option/if/no-output */
+
+/**
+ * @ingroup RTEMSAPIClassicOptions
+ *
+ * @brief This option constant indicates that the nothing shall be output.
+ */
+#define RTEMS_NO_OUTPUT 0x0004
+
 /* Generated from spec:/rtems/option/if/no-wait */
 
 /**
-- 
2.35.3

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Re: [PATCH] bsps/arm: Improve GICv3 support

[Sebastian Huber]

On 16.04.24 16:51, Kinsey Moore wrote:
This adds warnings for arm_interrupt_enable_interrupts and 
arm_interrupt_restore_interrupts. I suspect a missing header. They also 
generate a link error on the a53_lp64_qemu bsp. I also dislike the 
while(true), but I don't think we officially have anything against it 
and there are existing examples in the codebase.


Did you test this with the latest master? Actually, I committed a 
similar patch for the GICv2 and then noticed that this broke the GICv3 
support. This is fixed by the current patch.


What would be your alternative to this while (true) loop?

void bsp_interrupt_dispatch(void)
{
  while (true) {
uint32_t icciar = READ_SR(ICC_IAR1);
rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
uint32_t status;

if (!bsp_interrupt_is_valid_vector(vector)) {
  break;
}

status = arm_interrupt_enable_interrupts();
bsp_interrupt_handler_dispatch_unchecked(vector);
arm_interrupt_restore_interrupts(status);

WRITE_SR(ICC_EOIR1, icciar);
  }
}

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[PATCH] bsps/arm: Improve GICv3 support

[Sebastian Huber]

In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.

Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.
---
 bsps/shared/dev/irq/arm-gicv3.c | 16 +++-
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index 88ac3c8293..dcfada6cd0 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -42,12 +42,18 @@
 
 void bsp_interrupt_dispatch(void)
 {
-  uint32_t icciar = READ_SR(ICC_IAR1);
-  rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
-  rtems_vector_number spurious = 1023;
+  while (true) {
+uint32_t icciar = READ_SR(ICC_IAR1);
+rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
+uint32_t status;
 
-  if (vector != spurious) {
-arm_interrupt_handler_dispatch(vector);
+if (!bsp_interrupt_is_valid_vector(vector)) {
+  break;
+}
+
+status = arm_interrupt_enable_interrupts();
+bsp_interrupt_handler_dispatch_unchecked(vector);
+arm_interrupt_restore_interrupts(status);
 
 WRITE_SR(ICC_EOIR1, icciar);
   }
-- 
2.35.3

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Re: [PATCH v2] rtems: Add get/set interrupt priorities

[Sebastian Huber]

On 09.04.24 16:28, Sebastian Huber wrote:

Add directives to get and set the priority of an interrupt vector.

Implement the directives for the following BSP families:

* arm/lpc24xx
* arm/lpc32xx
* powerpc/mpc55xxevb
* powerpc/qoriq

Implement the directives for the following interrupt controllers:

* GICv2 and GICv3 (arm and aarch64)
* NVIC (arm)
* PLIC (riscv)

Update #5002.


Any comments to this API extension?

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Re: [PATCH] bsps/aarch64/raspberrypi: Add system timer support

[Sebastian Huber]

On 13.04.24 12:13, Ning Yang wrote:

diff --git a/bsps/aarch64/raspberrypi/include/bsp/irq.h 
b/bsps/aarch64/raspberrypi/include/bsp/irq.h
index 1ff6ae80de..f2dd2f6c14 100644
--- a/bsps/aarch64/raspberrypi/include/bsp/irq.h
+++ b/bsps/aarch64/raspberrypi/include/bsp/irq.h
@@ -9,6 +9,7 @@
  /**
   * Copyright (c) 2013 Alan Cudmore
   * Copyright (c) 2022 Mohd Noor Aman
+ * Copyright (c) 2024 Ning Yang
   *
   *  The license and distribution terms for this file may be
   *  found in the file LICENSE in this distribution or at
@@ -24,6 +25,7 @@
  
  #include 

  #include 
+#include 


This is a legacy API, please don't include this header.

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Re: [PATCH 0/3] Improve Xilinx TTC clock driver

[Sebastian Huber]

On 11.04.24 16:56, Kinsey Moore wrote:

Beyond the rebase issue, this patch set looks good.


Thanks for the review, I checked it in.

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Re: [PATCH 1/3] bsps/xil-ttc: Use interrupt entry

[Sebastian Huber]

On 11.04.24 16:27, Kinsey Moore wrote:

  static void zynqmp_ttc_clock_driver_support_install_isr(
    rtems_interrupt_handler handler
  )
  {
    rtems_status_code sc;

-  sc = rtems_interrupt_handler_install(
-    BSP_SELECTED_TTC_IRQ,
-    "Clock",
-    RTEMS_INTERRUPT_UNIQUE,
+  rtems_interrupt_entry_initialize(
+    _ttc_interrupt_entry,
      handler,
      _clock_instance


There is a missing comma here preventing compilation.


Thanks, I will fix this. I introduced this error in a rebase.

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[PATCH] dev/irq: Improve Doxgyen group assignments

[Sebastian Huber]

Make the GIC interrupt controller support a subgroup of the generic interrupt
controller support.
---
 bsps/aarch64/include/dev/irq/arm-gic-arch.h| 13 +++--
 bsps/arm/include/dev/irq/arm-gic-arch.h| 13 +++--
 bsps/include/dev/irq/arm-gic-irq.h | 15 ---
 bsps/include/dev/irq/arm-gic-regs.h| 15 ---
 bsps/include/dev/irq/arm-gic-tm27.h|  7 ---
 bsps/include/dev/irq/arm-gic.h | 18 --
 bsps/include/dev/irq/arm-gicv3.h   | 13 +++--
 bsps/shared/dev/irq/arm-gicv2-get-attributes.c |  5 +++--
 bsps/shared/dev/irq/arm-gicv2-zynqmp.c |  6 --
 bsps/shared/dev/irq/arm-gicv2.c|  5 +++--
 bsps/shared/dev/irq/arm-gicv3.c| 13 +++--
 11 files changed, 94 insertions(+), 29 deletions(-)

diff --git a/bsps/aarch64/include/dev/irq/arm-gic-arch.h 
b/bsps/aarch64/include/dev/irq/arm-gic-arch.h
index 94b832c2c5..5ca2c7314e 100644
--- a/bsps/aarch64/include/dev/irq/arm-gic-arch.h
+++ b/bsps/aarch64/include/dev/irq/arm-gic-arch.h
@@ -3,9 +3,10 @@
 /**
  * @file
  *
- * @ingroup RTEMSBSPsAArch64Shared
+ * @ingroup DevIRQGIC
  *
- * @brief AArch64-specific ARM GICv3 handlers.
+ * @brief This header file provides interfaces of the ARM Generic Interrupt
+ *   Controller (GIC) support specific to the AArch64 architecture.
  */
 
 /*
@@ -46,6 +47,12 @@
 extern "C" {
 #endif
 
+/**
+ * @addtogroup DevIRQGIC
+ *
+ * @{
+ */
+
 static inline uint32_t arm_interrupt_enable_interrupts(void)
 {
   uint32_t status = _CPU_ISR_Get_level();
@@ -72,6 +79,8 @@ static inline void 
arm_interrupt_facility_set_exception_handler(void)
   );
 }
 
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsps/arm/include/dev/irq/arm-gic-arch.h 
b/bsps/arm/include/dev/irq/arm-gic-arch.h
index f2ea76f22f..f6c8b5d426 100644
--- a/bsps/arm/include/dev/irq/arm-gic-arch.h
+++ b/bsps/arm/include/dev/irq/arm-gic-arch.h
@@ -3,9 +3,10 @@
 /**
  * @file
  *
- * @ingroup RTEMSBSPsARMShared
+ * @ingroup DevIRQGIC
  *
- * @brief ARM-specific IRQ handlers.
+ * @brief This header file provides interfaces of the ARM Generic Interrupt
+ *   Controller (GIC) support specific to the Arm architecture.
  */
 
 /*
@@ -44,6 +45,12 @@
 extern "C" {
 #endif
 
+/**
+ * @addtogroup DevIRQGIC
+ *
+ * @{
+ */
+
 static inline uint32_t arm_interrupt_enable_interrupts(void)
 {
   return _ARMV4_Status_irq_enable();
@@ -62,6 +69,8 @@ static inline void 
arm_interrupt_facility_set_exception_handler(void)
*/
 }
 
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsps/include/dev/irq/arm-gic-irq.h 
b/bsps/include/dev/irq/arm-gic-irq.h
index 518256ad2b..25870fec07 100644
--- a/bsps/include/dev/irq/arm-gic-irq.h
+++ b/bsps/include/dev/irq/arm-gic-irq.h
@@ -1,11 +1,12 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
 /**
- *  @file
+ * @file
  *
- *  @ingroup arm_gic
+ * @ingroup DevIRQGIC
  *
- *  @brief ARM GIC IRQ
+ * @brief This header file provides interfaces of the ARM Generic Interrupt
+ *   Controller (GIC) support.
  */
 
 /*
@@ -43,6 +44,12 @@
 extern "C" {
 #endif /* __cplusplus */
 
+/**
+ * @addtogroup DevIRQGIC
+ *
+ * @{
+ */
+
 #define ARM_GIC_IRQ_SGI_0 0
 #define ARM_GIC_IRQ_SGI_1 1
 #define ARM_GIC_IRQ_SGI_2 2
@@ -98,6 +105,8 @@ uint32_t arm_gic_irq_processor_count(void);
 void arm_gic_irq_initialize_secondary_cpu(void);
 #endif
 
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
diff --git a/bsps/include/dev/irq/arm-gic-regs.h 
b/bsps/include/dev/irq/arm-gic-regs.h
index 097ff67c13..c03a7a7a07 100644
--- a/bsps/include/dev/irq/arm-gic-regs.h
+++ b/bsps/include/dev/irq/arm-gic-regs.h
@@ -1,11 +1,12 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
 /**
- *  @file
+ * @file
  *
- *  @ingroup arm_gic
+ * @ingroup DevIRQGIC
  *
- *  @brief ARM GIC Register definitions
+ * @brief This header file provides interfaces of the ARM Generic Interrupt
+ *   Controller (GIC) memory-mapped registers.
  */
 
 /*
@@ -38,6 +39,12 @@
 
 #include 
 
+/**
+ * @addtogroup DevIRQGIC
+ *
+ * @{
+ */
+
 typedef struct {
   uint32_t iccicr;
 #define GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4)
@@ -225,4 +232,6 @@ typedef struct {
   uint32_t icspigrpmodr[64];
 } gic_sgi_ppi;
 
+/** @} */
+
 #endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */
diff --git a/bsps/include/dev/irq/arm-gic-tm27.h 
b/bsps/include/dev/irq/arm-gic-tm27.h
index 6baab7a45c..38e3ecf938 100644
--- a/bsps/include/dev/irq/arm-gic-tm27.h
+++ b/bsps/include/dev/irq/arm-gic-tm27.h
@@ -1,11 +1,12 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
 /**
- *  @file
+ * @file
  *
- *  @ingroup arm_gic
+ * @ingroup DevIRQGIC
  *
- *  @brief ARM GIC TM27 Support
+ * @brief This header file provides the TM27 support for the ARM Generic
+ *   Interrupt Controller (GIC).
  */
 
 /*
diff --git a/bsps/include/dev/irq/arm-gic.h b/bsps/include/dev/irq/arm-gic.h
index 73c9a688d5..4e418de68f 100644
--- a/bsps/include/dev/irq/arm-gic.h
+++ 

[PATCH 2/3] bsps/xil-ttc: Add XIL_FATAL_TTC_IRQ_INSTALL

[Sebastian Huber]

---
 bsps/include/bsp/fatal.h  |   3 +
 bsps/shared/dev/clock/xil-ttc.c   |   6 +-
 .../bsps/fatal-clock-xil-ttc-irq-install.yml  |  21 ++
 spec/build/testsuites/validation/grp.yml  |   2 +
 .../bsps/tr-fatal-clock-xil-ttc-irq-install.c | 187 ++
 .../bsps/tr-fatal-clock-xil-ttc-irq-install.h |  84 
 .../bsps/ts-fatal-clock-xil-ttc-irq-install.c |  79 
 7 files changed, 378 insertions(+), 4 deletions(-)
 create mode 100644 
spec/build/testsuites/validation/bsps/fatal-clock-xil-ttc-irq-install.yml
 create mode 100644 
testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.c
 create mode 100644 
testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.h
 create mode 100644 
testsuites/validation/bsps/ts-fatal-clock-xil-ttc-irq-install.c

diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h
index ffdb4bc8e1..87fc481ead 100644
--- a/bsps/include/bsp/fatal.h
+++ b/bsps/include/bsp/fatal.h
@@ -214,6 +214,9 @@ typedef enum {
 
   /* MicroBlaze fatal codes */
   MICROBLAZE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(16),
+
+  /* Xilinx fatal codes */
+  XIL_FATAL_TTC_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(17),
 } bsp_fatal_code;
 
 RTEMS_NO_RETURN static inline void
diff --git a/bsps/shared/dev/clock/xil-ttc.c b/bsps/shared/dev/clock/xil-ttc.c
index 384f23663b..0140bb7445 100644
--- a/bsps/shared/dev/clock/xil-ttc.c
+++ b/bsps/shared/dev/clock/xil-ttc.c
@@ -35,11 +35,9 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include 
-
-#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -211,7 +209,7 @@ static void zynqmp_ttc_clock_driver_support_install_isr(
 _ttc_interrupt_entry
   );
   if ( sc != RTEMS_SUCCESSFUL ) {
-rtems_fatal_error_occurred(0xdeadbeef);
+bsp_fatal(XIL_FATAL_TTC_IRQ_INSTALL);
   }
 }
 
diff --git 
a/spec/build/testsuites/validation/bsps/fatal-clock-xil-ttc-irq-install.yml 
b/spec/build/testsuites/validation/bsps/fatal-clock-xil-ttc-irq-install.yml
new file mode 100644
index 00..253131551d
--- /dev/null
+++ b/spec/build/testsuites/validation/bsps/fatal-clock-xil-ttc-irq-install.yml
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: test-program
+cflags: []
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+cppflags: []
+cxxflags: []
+enabled-by: bsps/arm/xilinx-zynqmp-rpu
+features: c cprogram
+includes: []
+ldflags: []
+links: []
+source:
+- testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.c
+- testsuites/validation/bsps/ts-fatal-clock-xil-ttc-irq-install.c
+stlib: []
+target: testsuites/validation/bsps/ts-fatal-clock-xil-ttc-irq-install.exe
+type: build
+use-after:
+- validation
+use-before: []
diff --git a/spec/build/testsuites/validation/grp.yml 
b/spec/build/testsuites/validation/grp.yml
index 726cf732dd..f10c6a9823 100644
--- a/spec/build/testsuites/validation/grp.yml
+++ b/spec/build/testsuites/validation/grp.yml
@@ -78,6 +78,8 @@ links:
   uid: validation-tls-0
 - role: build-dependency
   uid: validation-tls-1
+- role: build-dependency
+  uid: bsps/fatal-clock-xil-ttc-irq-install
 - role: build-dependency
   uid: bsps/fatal-sparc-leon3-cache-snooping-disabled-boot
 - role: build-dependency
diff --git a/testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.c 
b/testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.c
new file mode 100644
index 00..731b454ee4
--- /dev/null
+++ b/testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.c
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup DevClockXilTtcValFatalIrqInstall
+ */
+
+/*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 

[PATCH 0/3] Improve Xilinx TTC clock driver

[Sebastian Huber]

Sebastian Huber (3):
  bsps/xil-ttc: Use interrupt entry
  bsps/xil-ttc: Add XIL_FATAL_TTC_IRQ_INSTALL
  bsps/xil-ttc: Improve clock driver

 bsps/arm/xilinx-zynqmp-rpu/include/bsp.h  |   3 -
 bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h  |   1 -
 bsps/include/bsp/fatal.h  |   3 +
 bsps/shared/dev/clock/xil-ttc.c   | 267 +-
 spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml |   6 +
 spec/build/bsps/optxilclockttcbaseaddr.yml|  18 ++
 spec/build/bsps/optxilclockttcirq.yml |  18 ++
 spec/build/bsps/optxilclockttcrefclk.yml  |  18 ++
 .../bsps/fatal-clock-xil-ttc-irq-install.yml  |  21 ++
 .../validation/bsps/objclockxilttc.yml|  14 +
 .../validation/bsps/validation-bsp-0.yml  |   6 +-
 spec/build/testsuites/validation/grp.yml  |   2 +
 .../bsps/tr-fatal-clock-xil-ttc-irq-install.c | 187 
 .../bsps/tr-fatal-clock-xil-ttc-irq-install.h |  84 ++
 .../bsps/ts-fatal-clock-xil-ttc-irq-install.c |  79 ++
 testsuites/validation/tc-dev-clock-xil-ttc.c  | 136 +
 16 files changed, 721 insertions(+), 142 deletions(-)
 create mode 100644 spec/build/bsps/optxilclockttcbaseaddr.yml
 create mode 100644 spec/build/bsps/optxilclockttcirq.yml
 create mode 100644 spec/build/bsps/optxilclockttcrefclk.yml
 create mode 100644 
spec/build/testsuites/validation/bsps/fatal-clock-xil-ttc-irq-install.yml
 create mode 100644 spec/build/testsuites/validation/bsps/objclockxilttc.yml
 create mode 100644 
testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.c
 create mode 100644 
testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.h
 create mode 100644 
testsuites/validation/bsps/ts-fatal-clock-xil-ttc-irq-install.c
 create mode 100644 testsuites/validation/tc-dev-clock-xil-ttc.c

-- 
2.35.3

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[PATCH 1/3] bsps/xil-ttc: Use interrupt entry

[Sebastian Huber]

---
 bsps/shared/dev/clock/xil-ttc.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/bsps/shared/dev/clock/xil-ttc.c b/bsps/shared/dev/clock/xil-ttc.c
index 340c428a48..384f23663b 100644
--- a/bsps/shared/dev/clock/xil-ttc.c
+++ b/bsps/shared/dev/clock/xil-ttc.c
@@ -191,18 +191,24 @@ static void 
zynqmp_ttc_clock_driver_support_at_tick(ttc_clock_context *tc)
   /* Else, something is set up wrong, only match should be enabled */
 }
 
+static rtems_interrupt_entry zynqmp_ttc_interrupt_entry;
+
 static void zynqmp_ttc_clock_driver_support_install_isr(
   rtems_interrupt_handler handler
 )
 {
   rtems_status_code sc;
 
-  sc = rtems_interrupt_handler_install(
-BSP_SELECTED_TTC_IRQ,
-"Clock",
-RTEMS_INTERRUPT_UNIQUE,
+  rtems_interrupt_entry_initialize(
+_ttc_interrupt_entry,
 handler,
 _clock_instance
+"Clock"
+  );
+  sc = rtems_interrupt_entry_install(
+BSP_SELECTED_TTC_IRQ,
+RTEMS_INTERRUPT_UNIQUE,
+_ttc_interrupt_entry
   );
   if ( sc != RTEMS_SUCCESSFUL ) {
 rtems_fatal_error_occurred(0xdeadbeef);
-- 
2.35.3

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[PATCH 3/3] bsps/xil-ttc: Improve clock driver

[Sebastian Huber]

Make the clock driver parameters configurable.  Use the maximum counter
frequency to get the best time resolution.  Decouple the CPU counter from the
timecounter.  Make the tick catch up handling more robust.  Add a validation
test for the tick catch up.
---
 bsps/arm/xilinx-zynqmp-rpu/include/bsp.h  |   3 -
 bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h  |   1 -
 bsps/shared/dev/clock/xil-ttc.c   | 255 +-
 spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml |   6 +
 spec/build/bsps/optxilclockttcbaseaddr.yml|  18 ++
 spec/build/bsps/optxilclockttcirq.yml |  18 ++
 spec/build/bsps/optxilclockttcrefclk.yml  |  18 ++
 .../validation/bsps/objclockxilttc.yml|  14 +
 .../validation/bsps/validation-bsp-0.yml  |   6 +-
 testsuites/validation/tc-dev-clock-xil-ttc.c  | 136 ++
 10 files changed, 337 insertions(+), 138 deletions(-)
 create mode 100644 spec/build/bsps/optxilclockttcbaseaddr.yml
 create mode 100644 spec/build/bsps/optxilclockttcirq.yml
 create mode 100644 spec/build/bsps/optxilclockttcrefclk.yml
 create mode 100644 spec/build/testsuites/validation/bsps/objclockxilttc.yml
 create mode 100644 testsuites/validation/tc-dev-clock-xil-ttc.c

diff --git a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h 
b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
index d80cedbd0d..70ad4f3c57 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
+++ b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
@@ -59,7 +59,6 @@
 
 #include 
 #include 
-#include 
 
 #include 
 
@@ -76,8 +75,6 @@ extern "C" {
 
 #define BSP_ARM_A9MPCORE_GT_BASE 0
 
-#define BSP_SELECTED_TTC_ADDR ZYNQMP_TTC0
-
 /**
  * @brief Zynq UltraScale+ MPSoC specific set up of the MMU.
  *
diff --git a/bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h 
b/bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h
index a65e5404f0..51aa613cdd 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h
+++ b/bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h
@@ -51,7 +51,6 @@
 extern "C" {
 #endif /* __cplusplus */
 
-#define BSP_SELECTED_TTC_IRQ ZYNQMP_IRQ_TTC_0_0
 #define BSP_INTERRUPT_VECTOR_COUNT 188
 
 /** @} */
diff --git a/bsps/shared/dev/clock/xil-ttc.c b/bsps/shared/dev/clock/xil-ttc.c
index 0140bb7445..624845d71c 100644
--- a/bsps/shared/dev/clock/xil-ttc.c
+++ b/bsps/shared/dev/clock/xil-ttc.c
@@ -1,14 +1,16 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
 /**
  * @file
  *
- * @ingroup RTEMSBSPsARMZynqMP
+ * @ingroup RTEMSDriverClockXilTTC
  *
- * @brief Triple Timer Counter clock functions definitions.
+ * @brief This source file contains a Clock Driver implementation using the
+ *   Xilinx Triple Timer Counter (TTC).
  */
 
 /*
- * SPDX-License-Identifier: BSD-2-Clause
- *
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
  * Copyright (C) 2023 Reflex Aerospace GmbH
  *
  * Written by Philip Kirkpatrick 
@@ -38,175 +40,160 @@
 #include 
 #include 
 #include 
-#include 
 #include 
+#include 
 #include 
 
-typedef struct {
-  struct timecounter ttc_tc;
-  uint32_t irq_match_interval;
-  uint32_t tick_miss;
-} ttc_clock_context;
-
-static ttc_clock_context ttc_clock_instance = {0, };
+#if XTTCPS_COUNT_VALUE_MASK != UINT32_MAX
+#error "unexpected XTTCPS_COUNT_VALUE_MASK value"
+#endif
 
-#define TTC_REFERENCE_CLOCK 1
+/**
+ * @defgroup RTEMSDriverClockXilTTC \
+ *   Xilinx Triple Timer Counter (TTC) Clock Driver
+ *
+ * @ingroup RTEMSDriverClockImpl
+ *
+ * @brief This group contains the Xilinx Triple Timer Counter (TTC) Clock
+ *   Driver implementation.
+ *
+ * @{
+ */
 
 uint32_t _CPU_Counter_frequency( void )
 {
-  return ttc_clock_instance.ttc_tc.tc_frequency;
+  return XIL_CLOCK_TTC_REFERENCE_CLOCK;
 }
 
-static uint32_t zynqmp_ttc_get_timecount(struct timecounter *tc)
+CPU_Counter_ticks _CPU_Counter_read(void)
 {
-  uint32_t time;
-  time = XTtcPs_ReadReg(BSP_SELECTED_TTC_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
-  return time;
+  return XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
 }
 
-CPU_Counter_ticks _CPU_Counter_read(void)
+static void xil_ttc_initialize(void)
 {
-  return zynqmp_ttc_get_timecount(_clock_instance.ttc_tc);
+  /* Do not use a prescaler to get a high resolution time source */
+  XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_CLK_CNTRL_OFFSET, 0);
+
+  /* Disable interupts */
+  XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_IER_OFFSET, 0);
+
+  /*
+   * Enable the timer, do not enable waveform output, increment up, use
+   * overflow mode, enable match mode.
+   */
+  XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_CNT_CNTRL_OFFSET,
+  XTTCPS_CNT_CNTRL_EN_WAVE_MASK | XTTCPS_CNT_CNTRL_MATCH_MASK);
 }
 
-/**
- *  @brief Initialize the HW peripheral for clock driver
- *
- *  Clock driver is implemented by RTI module
- *
- * @retval Void
- */
-static void zynqmp_ttc_clock_driver_support_initialize_hardware(void)
-{
+RTEMS_SYSINIT_ITEM(
+  xil_ttc_initialize,
+  RTEMS_SYSINIT_CPU_COUNTER,
+  RTEMS_SYSINIT_ORDER_MIDDLE
+);
+
+typedef struct {
+  struct timecounter base;
+  

[rtems-docs] c-user: Document interrupt get/set priority

[Sebastian Huber]

Update #5002.
---
 c-user/interrupt/directives.rst   | 185 +-
 c-user/interrupt/introduction.rst |  10 +-
 c-user/rtems_data_types.rst   |  19 ++-
 3 files changed, 211 insertions(+), 3 deletions(-)

diff --git a/c-user/interrupt/directives.rst b/c-user/interrupt/directives.rst
index 80eddfd..a8f7a79 100644
--- a/c-user/interrupt/directives.rst
+++ b/c-user/interrupt/directives.rst
@@ -1,6 +1,6 @@
 .. SPDX-License-Identifier: CC-BY-SA-4.0
 
-.. Copyright (C) 2008, 2022 embedded brains GmbH & Co. KG
+.. Copyright (C) 2008, 2024 embedded brains GmbH & Co. KG
 .. Copyright (C) 1988, 2008 On-Line Applications Research Corporation (OAR)
 
 .. This file is part of the RTEMS quality process and was automatically
@@ -2005,6 +2005,189 @@ The following constraints apply to this directive:
 
 * The directive will not cause the calling task to be preempted.
 
+.. Generated from spec:/rtems/intr/if/get-priority
+
+.. raw:: latex
+
+\clearpage
+
+.. index:: rtems_interrupt_get_priority()
+
+.. _InterfaceRtemsInterruptGetPriority:
+
+rtems_interrupt_get_priority()
+--
+
+Gets the priority of the interrupt vector.
+
+.. rubric:: CALLING SEQUENCE:
+
+.. code-block:: c
+
+rtems_status_code rtems_interrupt_get_priority(
+  rtems_vector_number vector,
+  uint32_t   *priority
+);
+
+.. rubric:: PARAMETERS:
+
+``vector``
+This parameter is the interrupt vector number.
+
+``priority``
+This parameter is the pointer to an `uint32_t
+`_ object.  When the
+directive call is successful, the priority of the interrupt vector will be
+stored in this object.
+
+.. rubric:: RETURN VALUES:
+
+:c:macro:`RTEMS_SUCCESSFUL`
+The requested operation was successful.
+
+:c:macro:`RTEMS_INVALID_ADDRESS`
+The ``priority`` parameter was `NULL
+`_.
+
+:c:macro:`RTEMS_INVALID_ID`
+There was no interrupt vector associated with the number specified by
+``vector``.
+
+:c:macro:`RTEMS_UNSATISFIED`
+There is no priority associated with the interrupt vector.
+
+.. rubric:: NOTES:
+
+The :ref:`InterfaceRtemsInterruptSetPriority` directive may be used to set the
+priority associated with an interrupt vector.
+
+.. rubric:: CONSTRAINTS:
+
+The following constraints apply to this directive:
+
+* The directive may be called from within interrupt context.
+
+* The directive may be called from within device driver initialization context.
+
+* The directive may be called from within task context.
+
+* The directive will not cause the calling task to be preempted.
+
+.. Generated from spec:/rtems/intr/if/set-priority
+
+.. raw:: latex
+
+\clearpage
+
+.. index:: rtems_interrupt_set_priority()
+
+.. _InterfaceRtemsInterruptSetPriority:
+
+rtems_interrupt_set_priority()
+--
+
+Sets the priority of the interrupt vector.
+
+.. rubric:: CALLING SEQUENCE:
+
+.. code-block:: c
+
+rtems_status_code rtems_interrupt_set_priority(
+  rtems_vector_number vector,
+  uint32_tpriority
+);
+
+.. rubric:: PARAMETERS:
+
+``vector``
+This parameter is the interrupt vector number.
+
+``priority``
+This parameter is the new priority for the interrupt vector.
+
+.. rubric:: DESCRIPTION:
+
+This directive sets the priority of the interrupt specified by ``vector`` to
+the priority specified by ``priority``.
+
+For processor-specific interrupts, the priority of the interrupt specific to a
+processor executing the directive call will be set.
+
+.. rubric:: RETURN VALUES:
+
+:c:macro:`RTEMS_SUCCESSFUL`
+The requested operation was successful.
+
+:c:macro:`RTEMS_INVALID_ID`
+There was no interrupt vector associated with the number specified by
+``vector``.
+
+:c:macro:`RTEMS_INVALID_PRIORITY`
+The priority specified by ``priority`` was not a valid new priority for the
+interrupt vector.
+
+:c:macro:`RTEMS_UNSATISFIED`
+The request to set the priority of the interrupt vector has not been
+satisfied.
+
+.. rubric:: NOTES:
+
+The :ref:`InterfaceRtemsInterruptGetPriority` directive may be used to get the
+priority associated with an interrupt vector.
+
+The interrupt prioritization support depends on the interrupt controller of the
+:term:`target`.  It is strongly recommended to read the relevant hardware
+documentation.  What happens when the priority of a pending or active interrupt
+is changed, depends on the interrupt controller.  In general, you should set
+the interrupt priority of an interrupt vector before a handler is installed.
+On some interrupt controllers, setting the priority to the maximum value
+(lowest importance) effectively disables the interrupt. On some architectures,
+a range of interrupt priority values may be not disabled by the interrupt
+disable directives.  Handlers of such interrupts shall not use operating system
+services.
+
+For the ARM Generic 

[PATCH v2] rtems: Add get/set interrupt priorities

[Sebastian Huber]

Add directives to get and set the priority of an interrupt vector.

Implement the directives for the following BSP families:

* arm/lpc24xx
* arm/lpc32xx
* powerpc/mpc55xxevb
* powerpc/qoriq

Implement the directives for the following interrupt controllers:

* GICv2 and GICv3 (arm and aarch64)
* NVIC (arm)
* PLIC (riscv)

Update #5002.
---

v2:

* Clarify documentation
* Add implementations
* Add validation tests

 bsps/arm/beagle/irq/irq.c |  19 +
 bsps/arm/csb336/irq/irq.c |  19 +
 bsps/arm/csb337/irq/irq.c |  19 +
 bsps/arm/edb7312/irq/irq.c|  19 +
 bsps/arm/gumstix/irq/irq.c|  19 +
 bsps/arm/lpc24xx/include/bsp/irq.h|  10 +-
 bsps/arm/lpc24xx/irq/irq.c|  58 +-
 bsps/arm/lpc32xx/include/bsp/irq.h|   4 -
 bsps/arm/lpc32xx/include/tm27.h   |  10 +-
 bsps/arm/lpc32xx/irq/irq.c|  56 +-
 bsps/arm/raspberrypi/irq/irq.c|  19 +
 bsps/arm/rtl22xx/irq/irq.c|  19 +
 bsps/arm/shared/irq/irq-armv7m.c  |  30 +
 bsps/arm/smdk2410/irq/irq.c   |  19 +
 bsps/arm/tms570/irq/irq.c |  19 +
 bsps/i386/shared/irq/irq.c|  19 +
 bsps/include/bsp/irq-generic.h|  41 ++
 bsps/include/dev/irq/arm-gic-irq.h|  10 -
 bsps/include/dev/irq/arm-gic-tm27.h   |   4 +-
 bsps/include/dev/irq/arm-gicv3.h  |   3 +
 bsps/lm32/shared/irq/irq.c|  19 +
 bsps/m68k/genmcf548x/irq/irq.c|  19 +
 bsps/microblaze/microblaze_fpga/irq/irq.c |  19 +
 bsps/mips/shared/irq/irq.c|  19 +
 bsps/powerpc/gen5200/irq/irq.c|  19 +
 bsps/powerpc/gen83xx/irq/irq.c|  19 +
 bsps/powerpc/mpc55xxevb/include/bsp/irq.h |  17 +-
 bsps/powerpc/mpc55xxevb/start/irq.c   |  46 +-
 bsps/powerpc/mpc8260ads/irq/irq.c |  19 +
 bsps/powerpc/psim/irq/irq_init.c  |  19 +
 bsps/powerpc/qemuppc/irq/irq_init.c   |  19 +
 bsps/powerpc/qoriq/clock/clock-config.c   |   5 +-
 bsps/powerpc/qoriq/include/bsp/irq.h  |  23 +-
 bsps/powerpc/qoriq/include/tm27.h |   7 +-
 bsps/powerpc/qoriq/irq/irq.c  |  56 +-
 bsps/powerpc/qoriq/mpci/intercom.c|   5 +-
 bsps/powerpc/shared/irq/ppc-irq-generic.c |  19 +
 bsps/powerpc/t32mppc/irq/irq.c|  19 +
 bsps/powerpc/tqm8xx/irq/irq.c |  19 +
 bsps/powerpc/virtex/irq/irq_init.c|  19 +
 bsps/riscv/griscv/irq/irq.c   |  19 +
 bsps/riscv/riscv/irq/irq.c|  44 +-
 .../shared/dev/irq/arm-gicv2-get-attributes.c |   3 +
 bsps/shared/dev/irq/arm-gicv2-zynqmp.c|   3 +
 bsps/shared/dev/irq/arm-gicv2.c   |  36 +-
 bsps/shared/dev/irq/arm-gicv3.c   |  65 +-
 bsps/shared/irq/irq-default.c |  19 +
 bsps/shared/irq/irq-priority.c|  65 ++
 bsps/sparc/leon3/start/eirq.c |  19 +
 bsps/sparc/shared/irq/irq-shared.c|  19 +
 bsps/x86_64/amd64/interrupts/idt.c|  19 +
 cpukit/include/rtems/rtems/intr.h | 166 -
 spec/build/bsps/objirq.yml|   1 +
 spec/build/bsps/powerpc/ss555/bspss555.yml|   1 +
 .../testsuites/validation/validation-intr.yml |   2 +
 testsuites/validation/tc-intr-get-priority.c  | 567 ++
 testsuites/validation/tc-intr-set-priority.c  | 504 
 57 files changed, 2162 insertions(+), 212 deletions(-)
 create mode 100644 bsps/shared/irq/irq-priority.c
 create mode 100644 testsuites/validation/tc-intr-get-priority.c
 create mode 100644 testsuites/validation/tc-intr-set-priority.c

diff --git a/bsps/arm/beagle/irq/irq.c b/bsps/arm/beagle/irq/irq.c
index 0ae82aa95e..7cb37d86e4 100644
--- a/bsps/arm/beagle/irq/irq.c
+++ b/bsps/arm/beagle/irq/irq.c
@@ -163,6 +163,25 @@ rtems_status_code 
bsp_interrupt_vector_disable(rtems_vector_number vector)
   return RTEMS_SUCCESSFUL;
 }
 
+rtems_status_code bsp_interrupt_set_priority(
+  rtems_vector_number vector,
+  uint32_t priority
+)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+  return RTEMS_UNSATISFIED;
+}
+
+rtems_status_code bsp_interrupt_get_priority(
+  rtems_vector_number vector,
+  uint32_t *priority
+)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+  bsp_interrupt_assert(priority != NULL);
+  return RTEMS_UNSATISFIED;
+}
+
 void bsp_interrupt_facility_initialize(void)
 {
   int i;
diff --git a/bsps/arm/csb336/irq/irq.c b/bsps/arm/csb336/irq/irq.c
index 2834eaf1f7..4ba8bd4ac4 100644
--- a/bsps/arm/csb336/irq/irq.c
+++ b/bsps/arm/csb336/irq/irq.c
@@ -88,6 +88,25 @@ rtems_status_code 
bsp_interrupt_vector_disable(rtems_vector_number vector)
   return RTEMS_SUCCESSFUL;
 }
 
+rtems_status_code bsp_interrupt_set_priority(
+  

Re: GCC 14: Some warnings are now errors

[Sebastian Huber]

On 09.04.24 14:41, Joel Sherrill wrote:
Is 14 the version for RTEMS 7 tools? If so, that makes it easier to 
address the issues.


I don't have time to update the RTEMS 7 tools currently.

--
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Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

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GCC 14: Some warnings are now errors

[Sebastian Huber]

Hello,

I did some tests with GCC 14 and it turned out that this release turns a 
couple of warnings into errors:


https://gcc.gnu.org/gcc-14/porting_to.html

It will be a bit of work to get RTEMS compile clean for GCC 14.

--
embedded brains GmbH & Co. KG
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
https://embedded-brains.de/datenschutzerklaerung/
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[PATCH] validation: Fix powerpc in test case

[Sebastian Huber]

The powerpc context switch restores the interrupt state.

Update #4955.
---
 testsuites/validation/tc-score-isr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/testsuites/validation/tc-score-isr.c 
b/testsuites/validation/tc-score-isr.c
index 9891829a84..b178541e72 100644
--- a/testsuites/validation/tc-score-isr.c
+++ b/testsuites/validation/tc-score-isr.c
@@ -221,7 +221,7 @@ static void ISRHandler( void *arg )
 
   (void) arg;
 
-#if defined(RTEMS_SMP)
+#if defined(RTEMS_SMP) && !(defined(__PPC__) || (__powerpc64__))
   Per_CPU_Control *cpu_self;
 
   cpu_self = _Per_CPU_Get();
-- 
2.35.3

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[PATCH] score: Improve C/C++ standard compatibility

[Sebastian Huber]

The processor mask implementation uses flsl() from  which is
only BSD visible.  Move the implementation to a separate header file to
hide it from the API level.  This fixes build errors with GCC 14.
---
 cpukit/include/rtems/score/processormask.h| 379 +--
 .../include/rtems/score/processormaskimpl.h   | 437 ++
 cpukit/include/rtems/score/smpimpl.h  |   2 +-
 cpukit/score/src/processormaskcopy.c  |   2 +-
 4 files changed, 440 insertions(+), 380 deletions(-)
 create mode 100644 cpukit/include/rtems/score/processormaskimpl.h

diff --git a/cpukit/include/rtems/score/processormask.h 
b/cpukit/include/rtems/score/processormask.h
index ce23f6c10d..71ed37cd0e 100644
--- a/cpukit/include/rtems/score/processormask.h
+++ b/cpukit/include/rtems/score/processormask.h
@@ -39,9 +39,7 @@
 
 #include 
 
-#include 
-
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
@@ -123,381 +121,6 @@ extern "C" {
  */
 typedef __BITSET_DEFINE( Processor_mask, CPU_MAXIMUM_PROCESSORS ) 
Processor_mask;
 
-/**
- * @brief Sets the bits of the mask to zero, also considers 
CPU_MAXIMUM_PROCESSORS.
- *
- * @param[out] mask The mask to set to zero.
- */
-static inline void _Processor_mask_Zero( Processor_mask *mask )
-{
-  __BIT_ZERO( CPU_MAXIMUM_PROCESSORS, mask );
-}
-
-/**
- * @brief Checks if the mask is zero, also considers CPU_MAXIMUM_PROCESSORS.
- *
- * @param mask The mask to check whether is is zero
- *
- * @retval true The mask is zero.
- * @retval false The mask is not zero.
- */
-static inline bool _Processor_mask_Is_zero( const Processor_mask *mask )
-{
-  return __BIT_EMPTY( CPU_MAXIMUM_PROCESSORS, mask );
-}
-
-/**
- * @brief Fills the mask, also considers CPU_MAXIMUM_PROCESSORS.
- *
- * @param[out] mask The mask to fill
- */
-static inline void _Processor_mask_Fill( Processor_mask *mask )
-{
-  __BIT_FILL( CPU_MAXIMUM_PROCESSORS, mask );
-}
-
-/**
- * @brief Copies the mask to another mask, also considers 
CPU_MAXIMUM_PROCESSORS.
- *
- * @param[out] dst The mask to copy @a src to.
- * @param src The mask to copy to @a dst.
- */
-static inline void _Processor_mask_Assign(
-  Processor_mask *dst, const Processor_mask *src
-)
-{
-  __BIT_COPY( CPU_MAXIMUM_PROCESSORS, src, dst );
-}
-
-/**
- * @brief Sets the specified index bit of the mask.
- *
- * @param[out] mask The mask to set the bit of.
- * @param index The index of the bit that shall be set.
- */
-static inline void _Processor_mask_Set(
-  Processor_mask *mask,
-  uint32_tindex
-)
-{
-  __BIT_SET( CPU_MAXIMUM_PROCESSORS, index, mask );
-}
-
-/**
- * @brief Clears the specified index bit of the mask.
- *
- * @param[out] mask The mask to clear the bit of.
- * @param index The index of the bit that shall be cleared.
- */
-static inline void _Processor_mask_Clear(
-  Processor_mask *mask,
-  uint32_tindex
-)
-{
-  __BIT_CLR( CPU_MAXIMUM_PROCESSORS, index, mask );
-}
-
-/**
- * @brief Checks if the specified index bit of the mask is set.
- *
- * @param mask The mask to check if the specified bit is set.
- * @param index The index of the bit that is checked.
- *
- * @retval true The specified index bit is set.
- * @retval false The specified index bit is not set.
- */
-static inline bool _Processor_mask_Is_set(
-  const Processor_mask *mask,
-  uint32_t  index
-)
-{
-  return __BIT_ISSET( CPU_MAXIMUM_PROCESSORS, index, mask );
-}
-
-/**
- * @brief Checks if the processor sets a and b are equal.
- *
- * @param a The first processor set.
- * @param b The seconde processor set.
- *
- * @retval true The processor sets a and b are equal.
- * @retval false The processor sets a and b are not equal.
- */
-static inline bool _Processor_mask_Is_equal(
-  const Processor_mask *a,
-  const Processor_mask *b
-)
-{
-  return !__BIT_CMP( CPU_MAXIMUM_PROCESSORS, a, b );
-}
-
-/**
- * @brief Checks if the intersection of the processor sets a and b is
- * non-empty.
- *
- * @param a The first processor set.
- * @param b The second processor set.
- *
- * @retval true The intersection of the processor sets a and b is non-empty.
- * @retval false The intersection of the processor sets a and b is empty.
- */
-static inline bool _Processor_mask_Has_overlap(
-  const Processor_mask *a,
-  const Processor_mask *b
-)
-{
-  return __BIT_OVERLAP( CPU_MAXIMUM_PROCESSORS, a, b );
-}
-
-/**
- * @brief Checks if the processor set small is a subset of processor set
- * big.
- *
- * @param big The bigger processor set.
- * @param small The smaller processor set.
- *
- * @retval true @a small is a subset of @a big.
- * @retval false @a small is not a subset of @a big.
- */
-static inline bool _Processor_mask_Is_subset(
-  const Processor_mask *big,
-  const Processor_mask *small
-)
-{
-  return __BIT_SUBSET( CPU_MAXIMUM_PROCESSORS, big, small );
-}
-
-/**
- * @brief Performs a bitwise a = b & c.
- *
- * @param[out] a The processor mask that is set by this operation.
- * @param b The first parameter of the AND-operation.
- * @param 

[PATCH] bsps/arm: Improve GICv2 support

[Sebastian Huber]

In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.

Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.
---
 bsps/aarch64/include/dev/irq/arm-gic-arch.h | 12 ++
 bsps/arm/include/dev/irq/arm-gic-arch.h | 10 +
 bsps/shared/dev/irq/arm-gicv2.c | 25 -
 3 files changed, 34 insertions(+), 13 deletions(-)

diff --git a/bsps/aarch64/include/dev/irq/arm-gic-arch.h 
b/bsps/aarch64/include/dev/irq/arm-gic-arch.h
index f1b6fdc03d..94b832c2c5 100644
--- a/bsps/aarch64/include/dev/irq/arm-gic-arch.h
+++ b/bsps/aarch64/include/dev/irq/arm-gic-arch.h
@@ -46,14 +46,18 @@
 extern "C" {
 #endif
 
-static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector)
+static inline uint32_t arm_interrupt_enable_interrupts(void)
 {
-  uint32_t interrupt_level = _CPU_ISR_Get_level();
+  uint32_t status = _CPU_ISR_Get_level();
   /* Enable interrupts for nesting */
   _CPU_ISR_Set_level(0);
-  bsp_interrupt_handler_dispatch(vector);
+  return status;
+}
+
+static inline void arm_interrupt_restore_interrupts(uint32_t status)
+{
   /* Restore interrupts to previous level */
-  _CPU_ISR_Set_level(interrupt_level);
+  _CPU_ISR_Set_level(status);
 }
 
 static inline void arm_interrupt_facility_set_exception_handler(void)
diff --git a/bsps/arm/include/dev/irq/arm-gic-arch.h 
b/bsps/arm/include/dev/irq/arm-gic-arch.h
index c9931be61a..f2ea76f22f 100644
--- a/bsps/arm/include/dev/irq/arm-gic-arch.h
+++ b/bsps/arm/include/dev/irq/arm-gic-arch.h
@@ -44,12 +44,14 @@
 extern "C" {
 #endif
 
-static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector)
+static inline uint32_t arm_interrupt_enable_interrupts(void)
 {
-  uint32_t psr = _ARMV4_Status_irq_enable();
-  bsp_interrupt_handler_dispatch(vector);
+  return _ARMV4_Status_irq_enable();
+}
 
-  _ARMV4_Status_restore(psr);
+static inline void arm_interrupt_restore_interrupts(uint32_t status)
+{
+  _ARMV4_Status_restore(status);
 }
 
 static inline void arm_interrupt_facility_set_exception_handler(void)
diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c
index f1730cc2ea..48423c9e08 100644
--- a/bsps/shared/dev/irq/arm-gicv2.c
+++ b/bsps/shared/dev/irq/arm-gicv2.c
@@ -41,6 +41,14 @@
 #include 
 #include 
 
+/*
+ * The GIC architecture reserves interrupt ID numbers 1020 to 1023 for special
+ * purposes.
+ */
+#if BSP_INTERRUPT_VECTOR_COUNT >= 1020
+#error "BSP_INTERRUPT_VECTOR_COUNT is too large"
+#endif
+
 #define GIC_CPUIF ((volatile gic_cpuif *) BSP_ARM_GIC_CPUIF_BASE)
 
 #define PRIORITY_DEFAULT 127
@@ -75,12 +83,19 @@
 void bsp_interrupt_dispatch(void)
 {
   volatile gic_cpuif *cpuif = GIC_CPUIF;
-  uint32_t icciar = cpuif->icciar;
-  rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
-  rtems_vector_number spurious = 1023;
 
-  if (vector != spurious) {
-arm_interrupt_handler_dispatch(vector);
+  while (true) {
+uint32_t icciar = cpuif->icciar;
+rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
+uint32_t status;
+
+if (!bsp_interrupt_is_valid_vector(vector)) {
+  break;
+}
+
+status = arm_interrupt_enable_interrupts();
+bsp_interrupt_handler_dispatch_unchecked(vector);
+arm_interrupt_restore_interrupts(status);
 
 cpuif->icceoir = icciar;
   }
-- 
2.35.3

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[PATCH] testsuites/unit: Add tests for compiler builtins

[Sebastian Huber]

On the arm target, __udivmoddi4() cannot be fully tested through normal
integer divisions.

Update #3716.
---
 testsuites/unit/tc-compiler-builtins.c | 221 +++--
 1 file changed, 207 insertions(+), 14 deletions(-)

diff --git a/testsuites/unit/tc-compiler-builtins.c 
b/testsuites/unit/tc-compiler-builtins.c
index 3beebe06fa..7a470b6632 100644
--- a/testsuites/unit/tc-compiler-builtins.c
+++ b/testsuites/unit/tc-compiler-builtins.c
@@ -130,6 +130,16 @@
 uint64_t __udivmoddi4( uint64_t n, uint64_t d, uint64_t *r );
 #endif
 
+#if defined(TEST_UDIVMODDI4) && defined(__arm__)
+/*
+ * Here __aeabi_uldivmod() may be used to carry out integer division
+ * operations even though the reminder is unused.  This function is
+ * implemented by __udivmoddi4() which may never get called without a
+ * reminder for compiler generated code.
+ */
+#define TEST_UDIVMODDI4_WITHOUT_REMINDER
+#endif
+
 static bool do_longjmp;
 
 static jmp_buf exception_return_context;
@@ -174,6 +184,9 @@ static void CompilerUnitBuiltins_Action_0( void )
 {
   volatile unsigned int n;
 
+  n = 0;
+  RTEMS_OBFUSCATE_VARIABLE( n );
+
   n = 1U;
   T_eq_int( __builtin_clz( n ), 31 );
 
@@ -192,6 +205,9 @@ static void CompilerUnitBuiltins_Action_1( void )
 {
   volatile unsigned long long n;
 
+  n = 0;
+  RTEMS_OBFUSCATE_VARIABLE( n );
+
   n = 1ULL;
   T_eq_int( __builtin_clzll( n ), 63 );
 
@@ -215,6 +231,9 @@ static void CompilerUnitBuiltins_Action_2( void )
 {
   volatile unsigned int n;
 
+  n = 0;
+  RTEMS_OBFUSCATE_VARIABLE( n );
+
   n = 1U;
   T_eq_int( __builtin_ctz( n ), 0 );
 
@@ -233,6 +252,9 @@ static void CompilerUnitBuiltins_Action_3( void )
 {
   volatile unsigned long long n;
 
+  n = 0;
+  RTEMS_OBFUSCATE_VARIABLE( n );
+
   n = 1ULL;
   T_eq_int( __builtin_ctzll( n ), 0 );
 
@@ -256,6 +278,9 @@ static void CompilerUnitBuiltins_Action_4( void )
 {
   volatile unsigned int n;
 
+  n = 0;
+  RTEMS_OBFUSCATE_VARIABLE( n );
+
   n = 1U;
   T_eq_int( __builtin_ffs( n ), 1 );
 
@@ -274,6 +299,9 @@ static void CompilerUnitBuiltins_Action_5( void )
 {
   volatile unsigned long long n;
 
+  n = 0;
+  RTEMS_OBFUSCATE_VARIABLE( n );
+
   n = 1ULL;
   T_eq_int( __builtin_ffsll( n ), 1 );
 
@@ -298,6 +326,9 @@ static void CompilerUnitBuiltins_Action_6( void )
 {
   volatile unsigned int n;
 
+  n = 0;
+  RTEMS_OBFUSCATE_VARIABLE( n );
+
   n = 1U;
   T_eq_int( __builtin_parity( n ), 1 );
 
@@ -313,6 +344,9 @@ static void CompilerUnitBuiltins_Action_7( void )
 {
   volatile unsigned long long n;
 
+  n = 0;
+  RTEMS_OBFUSCATE_VARIABLE( n );
+
   n = 1ULL;
   T_eq_int( __builtin_parityll( n ), 1 );
 
@@ -328,6 +362,9 @@ static void CompilerUnitBuiltins_Action_8( void )
 {
   volatile unsigned int n;
 
+  n = 0;
+  RTEMS_OBFUSCATE_VARIABLE( n );
+
   n = 0U;
   T_eq_int( __builtin_popcount( n ), 0 );
 
@@ -346,6 +383,9 @@ static void CompilerUnitBuiltins_Action_9( void )
 {
   volatile unsigned long long n;
 
+  n = 0;
+  RTEMS_OBFUSCATE_VARIABLE( n );
+
   n = 0ULL;
   T_eq_int( __builtin_popcountll( n ), 0 );
 
@@ -364,6 +404,9 @@ static void CompilerUnitBuiltins_Action_10( void )
 {
   volatile uint32_t n;
 
+  n = 0;
+  RTEMS_OBFUSCATE_VARIABLE( n );
+
   n = UINT32_C( 0 );
   T_eq_u32( __builtin_bswap32( n ), n );
 
@@ -385,6 +428,9 @@ static void CompilerUnitBuiltins_Action_11( void )
 {
   volatile uint64_t n;
 
+  n = 0;
+  RTEMS_OBFUSCATE_VARIABLE( n );
+
   n = UINT64_C( 0 );
   T_eq_u64( __builtin_bswap64( n ), n );
 
@@ -406,6 +452,11 @@ static void CompilerUnitBuiltins_Action_12( void )
   volatile int64_t a;
   volatile int64_t b;
 
+  a = 0;
+  RTEMS_OBFUSCATE_VARIABLE( a );
+  b = 0;
+  RTEMS_OBFUSCATE_VARIABLE( b );
+
   a = INT64_C( 0 );
   b = INT64_C( 0 );
   T_false( a < b );
@@ -431,6 +482,11 @@ static void CompilerUnitBuiltins_Action_13( void )
   volatile uint64_t a;
   volatile uint64_t b;
 
+  a = 0;
+  RTEMS_OBFUSCATE_VARIABLE( a );
+  b = 0;
+  RTEMS_OBFUSCATE_VARIABLE( b );
+
   a = UINT64_C( 0 );
   b = UINT64_C( 0 );
   T_false( a < b );
@@ -456,6 +512,11 @@ static void CompilerUnitBuiltins_Action_14( void )
   volatile int64_t i;
   volatile int s;
 
+  i = 0;
+  RTEMS_OBFUSCATE_VARIABLE( i );
+  s = 0;
+  RTEMS_OBFUSCATE_VARIABLE( s );
+
   i = INT64_C( 1 );
   s = 0;
   T_eq_i64( i << s, INT64_C( 1 ) );
@@ -482,6 +543,11 @@ static void CompilerUnitBuiltins_Action_15( void )
   volatile int64_t i;
   volatile int s;
 
+  i = 0;
+  RTEMS_OBFUSCATE_VARIABLE( i );
+  s = 0;
+  RTEMS_OBFUSCATE_VARIABLE( s );
+
   i = INT64_C( 1 );
   s = 0;
   T_eq_i64( i >> s, INT64_C( 1 ) );
@@ -507,6 +573,11 @@ static void CompilerUnitBuiltins_Action_16( void )
   volatile uint64_t i;
   volatile int s;
 
+  i = 0;
+  RTEMS_OBFUSCATE_VARIABLE( i );
+  s = 0;
+  RTEMS_OBFUSCATE_VARIABLE( s );
+
   i = UINT64_C( 1 );
   s = 0;
   T_eq_u64( i >> s, UINT64_C( 1 ) );
@@ -532,6 +603,11 @@ static void CompilerUnitBuiltins_Action_17( void )
   volatile int64_t a;
   volatile int64_t b;
 
+  a = 0;
+  

[PATCH] smptests/smpipi01: Fix sporadic test failure

[Sebastian Huber]

Make sure that the last IPI is processed before the next test case is
carried out.
---
 testsuites/smptests/smpipi01/init.c | 48 +
 1 file changed, 42 insertions(+), 6 deletions(-)

diff --git a/testsuites/smptests/smpipi01/init.c 
b/testsuites/smptests/smpipi01/init.c
index 290d13775f..f8172fed96 100644
--- a/testsuites/smptests/smpipi01/init.c
+++ b/testsuites/smptests/smpipi01/init.c
@@ -198,6 +198,43 @@ static const Per_CPU_Job_context counter_1_job_context = {
   .arg = _instance
 };
 
+static void sync_handler(void *arg)
+{
+  test_context *ctx = arg;
+  SMP_barrier_State *bs = >worker_barrier_state;
+
+  /* (E) */
+  barrier(ctx, bs);
+}
+
+static const Per_CPU_Job_context sync_context = {
+  .handler = sync_handler,
+  .arg = _instance
+};
+
+static void wait_for_ipi_done(test_context *ctx, Per_CPU_Control *cpu)
+{
+  Per_CPU_Job job;
+  unsigned long done;
+
+  job.context = _context;
+  _Per_CPU_Submit_job(cpu, );
+
+  while (cpu->isr_nest_level == 0) {
+RTEMS_COMPILER_MEMORY_BARRIER();
+  }
+
+  /* (E) */
+  barrier(ctx, >main_barrier_state);
+
+  while (cpu->isr_nest_level != 0) {
+RTEMS_COMPILER_MEMORY_BARRIER();
+  }
+
+  done = _Atomic_Load_ulong( , ATOMIC_ORDER_ACQUIRE );
+  rtems_test_assert( done == PER_CPU_JOB_DONE );
+}
+
 static void test_send_message_flood(
   test_context *ctx,
   uint32_t cpu_count
@@ -211,20 +248,15 @@ static void test_send_message_flood(
 
 ctx->jobs[cpu_index][0].context = _0_job_context;
 ctx->jobs[cpu_index][1].context = _1_job_context;
-_Per_CPU_Submit_job(cpu, >jobs[cpu_index][0]);
+_Per_CPU_Add_job(cpu, >jobs[cpu_index][0]);
   }
 
   for (cpu_index = 0; cpu_index < cpu_count; ++cpu_index) {
 Per_CPU_Control *cpu;
-Per_CPU_Control *cpu_self;
 uint32_t i;
 
 cpu = _Per_CPU_Get_by_index(cpu_index);
 
-cpu_self = _Thread_Dispatch_disable();
-_SMP_Synchronize();
-_Thread_Dispatch_enable(cpu_self);
-
 for (i = 0; i < cpu_count; ++i) {
   if (i != cpu_index) {
 ctx->copy_counters[i] = ctx->counters[i].value;
@@ -235,6 +267,10 @@ static void test_send_message_flood(
   _SMP_Send_message(cpu, SMP_MESSAGE_PERFORM_JOBS);
 }
 
+if (cpu_index != cpu_index_self) {
+  wait_for_ipi_done(ctx, cpu);
+}
+
 for (i = 0; i < cpu_count; ++i) {
   if (i != cpu_index) {
 rtems_test_assert(ctx->copy_counters[i] == ctx->counters[i].value);
-- 
2.35.3

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[PATCH] rtems: Add get/set interrupt priorities

[Sebastian Huber]

Add directives to get and set the priority of an interrupt vector.

Update #5002.
---
 cpukit/include/rtems/rtems/intr.h | 154 +-
 1 file changed, 153 insertions(+), 1 deletion(-)

diff --git a/cpukit/include/rtems/rtems/intr.h 
b/cpukit/include/rtems/rtems/intr.h
index f8809015e4..68fd7e6c45 100644
--- a/cpukit/include/rtems/rtems/intr.h
+++ b/cpukit/include/rtems/rtems/intr.h
@@ -9,7 +9,7 @@
  */
 
 /*
- * Copyright (C) 2008, 2022 embedded brains GmbH & Co. KG
+ * Copyright (C) 2008, 2024 embedded brains GmbH & Co. KG
  * Copyright (C) 1988, 2008 On-Line Applications Research Corporation (OAR)
  *
  * Redistribution and use in source and binary forms, with or without
@@ -1743,6 +1743,135 @@ rtems_status_code rtems_interrupt_raise_on(
  */
 rtems_status_code rtems_interrupt_clear( rtems_vector_number vector );
 
+/* Generated from spec:/rtems/intr/if/get-priority */
+
+/**
+ * @ingroup RTEMSAPIClassicIntr
+ *
+ * @brief Gets the priority of the interrupt vector.
+ *
+ * @param vector is the interrupt vector number.
+ *
+ * @param[out] priority is the pointer to an uint32_t object.  When the
+ *   directive call is successful, the priority of the interrupt vector will be
+ *   stored in this object.
+ *
+ * @retval ::RTEMS_SUCCESSFUL The requested operation was successful.
+ *
+ * @retval ::RTEMS_INVALID_ADDRESS The ``priority`` parameter was NULL.
+ *
+ * @retval ::RTEMS_INVALID_ID There was no interrupt vector associated with the
+ *   number specified by ``vector``.
+ *
+ * @retval ::RTEMS_UNSATISFIED There is no priority associated with the
+ *   interrupt vector.
+ *
+ * @par Notes
+ * The rtems_interrupt_set_priority() directive may be used to set the priority
+ * associated with an interrupt vector.
+ *
+ * @par Constraints
+ * @parblock
+ * The following constraints apply to this directive:
+ *
+ * * The directive may be called from within interrupt context.
+ *
+ * * The directive may be called from within device driver initialization
+ *   context.
+ *
+ * * The directive may be called from within task context.
+ *
+ * * The directive will not cause the calling task to be preempted.
+ * @endparblock
+ */
+rtems_status_code rtems_interrupt_get_priority(
+  rtems_vector_number vector,
+  uint32_t   *priority
+);
+
+/* Generated from spec:/rtems/intr/if/set-priority */
+
+/**
+ * @ingroup RTEMSAPIClassicIntr
+ *
+ * @brief Sets the priority of the interrupt vector.
+ *
+ * @param vector is the interrupt vector number.
+ *
+ * @param priority is the new priority for the interrupt vector.
+ *
+ * @retval ::RTEMS_SUCCESSFUL The requested operation was successful.
+ *
+ * @retval ::RTEMS_INVALID_ID There was no interrupt vector associated with the
+ *   number specified by ``vector``.
+ *
+ * @retval ::RTEMS_INVALID_PRIORITY The priority specified by ``priority`` was
+ *   not a valid new priority for the interrupt vector.
+ *
+ * @retval ::RTEMS_UNSATISFIED The request to set the priority of the interrupt
+ *   vector has not been satisfied.
+ *
+ * @par Notes
+ * @parblock
+ * The rtems_interrupt_get_priority() directive may be used to get the priority
+ * associated with an interrupt vector.
+ *
+ * The interrupt prioritization support depends on the interrupt controller of
+ * the target.  It is strongly recommended to read the relevant hardware
+ * documentation.  What happens when the priority of a pending or active
+ * interrupt is changed, depends on the interrupt controller.  In general, you
+ * should set the interrupt priority of an interrupt vector before a handler is
+ * installed.
+ *
+ * For the ARM Generic Interrupt Controller (GIC), an 8-bit priority value is
+ * supported.  The granularity of the priority levels depends on the interrupt
+ * controller configuration.  Some low-order bits of a priority value may be
+ * read-as-zero (RAZ) and writes are ignored (WI).  Where group 0 (FIQ) and
+ * group 1 (IRQ) interrupts are used, it is recommended to use the lower half
+ * of the supported priority value range for the group 0 interrupts and the
+ * upper half for group 1 interrupts.  This ensures that group 1 interrupts
+ * cannot preempt group 0 interrupts.
+ *
+ * For the Armv7-M Nested Vector Interrupt Controller (NVIC), an 8-bit priority
+ * value is supported.  The granularity of the priority levels depends on the
+ * interrupt controller configuration.  Some lower bits of a priority value may
+ * be read-as-zero (RAZ) and writes are ignored (WI).  Interrupts with a
+ * priority value less than 128 are not disabled by the RTEMS interrupt disable
+ * directives.  Such interrupts shall not use operating system services.
+ *
+ * For the RISC-V Platform-Level Interrupt Controller (PLIC), all priority
+ * values from 0 to the maximum priority value of the platform are supported.
+ * Please note that for this directive in contrast to the PLIC, a higher
+ * priority value is associated with a lower importance.  The maximum priority
+ * value (mapped to 

Re: [PATCH v2 2/3] dev/serial: Add ZYNQ_UART_[01]_BASE_ADDR

[Sebastian Huber]

On 28.03.24 16:48, Kinsey Moore wrote:
This patch set looks good to me. I'd suggest a different file for the 
versal unless there's a good name that can easily cover both.


The versal BSP doesn't use this driver and seems to have a different 
hardware UART interface. It uses a BSP-specific driver:


./bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart-regs.h
./bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart.h
./bsps/aarch64/xilinx-versal/dev/serial/versal-uart-polled.c
./bsps/aarch64/xilinx-versal/dev/serial/versal-uart.c

I don't think we should mix these two currently independent drivers.

--
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Herr Sebastian HUBER
Dornierstr. 4
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Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
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[PATCH v2 3/3] dev/serial: Add Zynq UART kernel I/O support

[Sebastian Huber]

Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new
BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR.  Move the kernel I/O support to a
shared file.
---
 bsps/aarch64/xilinx-zynqmp/console/console.c  | 41 ++
 bsps/arm/xilinx-zynq/console/console-config.c | 50 -
 bsps/arm/xilinx-zynq/console/console-init.c   | 20 ++-
 bsps/arm/xilinx-zynq/include/bsp.h|  3 --
 bsps/arm/xilinx-zynq/start/bspreset.c |  6 ++-
 .../console/console-config.c  | 40 ++
 .../xilinx-zynqmp/console/console-config.c| 40 ++
 .../dev/serial/zynq-uart-kernel-io.c} | 53 +++
 spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml |  2 -
 spec/build/bsps/arm/xilinx-zynq/grp.yml   |  2 -
 spec/build/bsps/arm/xilinx-zynq/obj.yml   |  2 -
 spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml |  2 -
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  2 -
 spec/build/bsps/objdevserialzynq.yml  |  5 +-
 spec/build/bsps/optconminor.yml   | 21 
 spec/build/bsps/optzynquartkernbase.yml   | 22 
 16 files changed, 90 insertions(+), 221 deletions(-)
 delete mode 100644 bsps/arm/xilinx-zynq/console/console-config.c
 rename bsps/{arm/xilinx-zynq/console/debug-console.c => 
shared/dev/serial/zynq-uart-kernel-io.c} (60%)
 delete mode 100644 spec/build/bsps/optconminor.yml
 create mode 100644 spec/build/bsps/optzynquartkernbase.yml

diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c 
b/bsps/aarch64/xilinx-zynqmp/console/console.c
index ce031a914e..4023d5c6f3 100644
--- a/bsps/aarch64/xilinx-zynqmp/console/console.c
+++ b/bsps/aarch64/xilinx-zynqmp/console/console.c
@@ -35,7 +35,6 @@
  */
 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -208,6 +207,7 @@ rtems_status_code console_initialize(
   rtems_termios_initialize();
 
   for (i = 0; i < RTEMS_ARRAY_SIZE(zynqmp_uart_instances); ++i) {
+zynq_uart_context *ctx = _uart_instances[i];
 char uart[] = "/dev/ttySX";
 
 uart[sizeof(uart) - 2] = (char) ('0' + i);
@@ -215,10 +215,10 @@ rtems_status_code console_initialize(
   [0],
   _uart_handler,
   NULL,
-  _uart_instances[i].base
+  >base
 );
 
-if (i == BSP_CONSOLE_MINOR) {
+if (ctx->regs == (zynq_uart *) ZYNQ_UART_KERNEL_IO_BASE_ADDR) {
   link([0], CONSOLE_DEVICE_NAME);
 }
   }
@@ -237,38 +237,5 @@ rtems_status_code console_initialize(
 
 void zynqmp_debug_console_flush(void)
 {
-  zynq_uart_reset_tx_flush(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
+  zynq_uart_reset_tx_flush((zynq_uart *) ZYNQ_UART_KERNEL_IO_BASE_ADDR);
 }
-
-static void zynqmp_debug_console_out(char c)
-{
-  zynq_uart_write_char_polled(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs, 
c);
-}
-
-static void zynqmp_debug_console_init(void)
-{
-  zynq_uart_initialize(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
-  BSP_output_char = zynqmp_debug_console_out;
-}
-
-static void zynqmp_debug_console_early_init(char c)
-{
-  zynq_uart_initialize(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
-  BSP_output_char = zynqmp_debug_console_out;
-  zynqmp_debug_console_out(c);
-}
-
-static int zynqmp_debug_console_in(void)
-{
-  return 
zynq_uart_read_char_polled(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
-}
-
-BSP_output_char_function_type BSP_output_char = 
zynqmp_debug_console_early_init;
-
-BSP_polling_getchar_function_type BSP_poll_char = zynqmp_debug_console_in;
-
-RTEMS_SYSINIT_ITEM(
-  zynqmp_debug_console_init,
-  RTEMS_SYSINIT_BSP_START,
-  RTEMS_SYSINIT_ORDER_LAST_BUT_5
-);
diff --git a/bsps/arm/xilinx-zynq/console/console-config.c 
b/bsps/arm/xilinx-zynq/console/console-config.c
deleted file mode 100644
index 42e64ee4dd..00
--- a/bsps/arm/xilinx-zynq/console/console-config.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMZynq
- *
- * @brief This source file contains the definition of ::zynq_uart_instances.
- */
-
-/*
- * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *notice, this list of conditions and the following disclaimer in the
- *documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 

[PATCH v2 2/3] dev/serial: Add ZYNQ_UART_[01]_BASE_ADDR

[Sebastian Huber]

This helps to provide a shared implementation of the kernel I/O support.
---
 bsps/aarch64/xilinx-zynqmp/console/console.c  |  4 +-
 bsps/aarch64/xilinx-zynqmp/include/bsp.h  |  2 +
 bsps/arm/xilinx-zynq/console/console-config.c |  5 +-
 bsps/arm/xilinx-zynq/include/bsp.h|  1 +
 .../console/console-config.c  |  4 +-
 bsps/arm/xilinx-zynqmp-rpu/include/bsp.h  |  2 +
 .../xilinx-zynqmp/console/console-config.c|  4 +-
 bsps/arm/xilinx-zynqmp/include/bsp.h  |  2 +
 bsps/include/dev/serial/zynq-uart-zynq.h  | 66 +++
 bsps/include/dev/serial/zynq-uart-zynqmp.h| 66 +++
 10 files changed, 148 insertions(+), 8 deletions(-)
 create mode 100644 bsps/include/dev/serial/zynq-uart-zynq.h
 create mode 100644 bsps/include/dev/serial/zynq-uart-zynqmp.h

diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c 
b/bsps/aarch64/xilinx-zynqmp/console/console.c
index 1e5df997e8..ce031a914e 100644
--- a/bsps/aarch64/xilinx-zynqmp/console/console.c
+++ b/bsps/aarch64/xilinx-zynqmp/console/console.c
@@ -188,11 +188,11 @@ RTEMS_SYSINIT_ITEM(
 static zynq_uart_context zynqmp_uart_instances[2] = {
   {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-.regs = (volatile struct zynq_uart *) 0xff00,
+.regs = (volatile zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
 .irq = ZYNQMP_IRQ_UART_0
   }, {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-.regs = (volatile struct zynq_uart *) 0xff01,
+.regs = (volatile zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
 .irq = ZYNQMP_IRQ_UART_1
   }
 };
diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp.h 
b/bsps/aarch64/xilinx-zynqmp/include/bsp.h
index 0ccca8b196..38a9fad768 100644
--- a/bsps/aarch64/xilinx-zynqmp/include/bsp.h
+++ b/bsps/aarch64/xilinx-zynqmp/include/bsp.h
@@ -55,6 +55,8 @@
 #include 
 #include 
 
+#include 
+
 #ifdef __cplusplus
 extern "C" {
 #endif /* __cplusplus */
diff --git a/bsps/arm/xilinx-zynq/console/console-config.c 
b/bsps/arm/xilinx-zynq/console/console-config.c
index d22ceb557d..42e64ee4dd 100644
--- a/bsps/arm/xilinx-zynq/console/console-config.c
+++ b/bsps/arm/xilinx-zynq/console/console-config.c
@@ -35,15 +35,16 @@
 
 #include 
 #include 
+#include 
 
 zynq_uart_context zynq_uart_instances[2] = {
   {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-.regs = (volatile struct zynq_uart *) 0xe000,
+.regs = (volatile zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
 .irq = ZYNQ_IRQ_UART_0
   }, {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-.regs = (volatile struct zynq_uart *) 0xe0001000,
+.regs = (volatile zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
 .irq = ZYNQ_IRQ_UART_1
   }
 };
diff --git a/bsps/arm/xilinx-zynq/include/bsp.h 
b/bsps/arm/xilinx-zynq/include/bsp.h
index 3311a99b50..5ffd5f573a 100644
--- a/bsps/arm/xilinx-zynq/include/bsp.h
+++ b/bsps/arm/xilinx-zynq/include/bsp.h
@@ -55,6 +55,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c 
b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
index eacf6ddcce..13eaa269c5 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
@@ -44,11 +44,11 @@
 static zynq_uart_context zynqmp_uart_instances[2] = {
   {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-.regs = (volatile struct zynq_uart *) 0xff00,
+.regs = (volatile zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
 .irq = ZYNQMP_IRQ_UART_0
   }, {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-.regs = (volatile struct zynq_uart *) 0xff01,
+.regs = (volatile zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
 .irq = ZYNQMP_IRQ_UART_1
   }
 };
diff --git a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h 
b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
index e386bd4b26..d80cedbd0d 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
+++ b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
@@ -61,6 +61,8 @@
 #include 
 #include 
 
+#include 
+
 #ifdef __cplusplus
 extern "C" {
 #endif /* __cplusplus */
diff --git a/bsps/arm/xilinx-zynqmp/console/console-config.c 
b/bsps/arm/xilinx-zynqmp/console/console-config.c
index ea148836a5..787ee05dd6 100644
--- a/bsps/arm/xilinx-zynqmp/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp/console/console-config.c
@@ -44,11 +44,11 @@
 static zynq_uart_context zynqmp_uart_instances[2] = {
   {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-.regs = (volatile struct zynq_uart *) 0xff00,
+.regs = (volatile struct zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
 .irq = ZYNQMP_IRQ_UART_0
   }, {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-.regs = (volatile struct zynq_uart *) 0xff01,
+.regs = (volatile struct zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
 .irq = 

[PATCH v2 1/3] dev/serial: Simplify some Zynq UART functions

[Sebastian Huber]

Make the initialization and polled functions independent of the Termios
context.  This helps to implement the kernel I/O support without a dependency
on the Termios framework.
---
 bsps/aarch64/xilinx-zynqmp/console/console.c  | 23 ---
 bsps/arm/xilinx-zynq/console/debug-console.c  | 15 ++
 .../console/console-config.c  | 23 ---
 .../xilinx-zynqmp/console/console-config.c| 23 ---
 bsps/include/dev/serial/zynq-uart-regs.h  | 20 +
 bsps/include/dev/serial/zynq-uart.h   | 23 ---
 bsps/shared/dev/serial/zynq-uart-polled.c | 28 ++-
 bsps/shared/dev/serial/zynq-uart.c| 18 
 8 files changed, 62 insertions(+), 111 deletions(-)

diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c 
b/bsps/aarch64/xilinx-zynqmp/console/console.c
index 9ce0b1da63..1e5df997e8 100644
--- a/bsps/aarch64/xilinx-zynqmp/console/console.c
+++ b/bsps/aarch64/xilinx-zynqmp/console/console.c
@@ -45,6 +45,7 @@
 #include 
 
 #include 
+#include 
 
 #include 
 #include 
@@ -236,42 +237,30 @@ rtems_status_code console_initialize(
 
 void zynqmp_debug_console_flush(void)
 {
-  zynq_uart_reset_tx_flush(_uart_instances[BSP_CONSOLE_MINOR]);
+  zynq_uart_reset_tx_flush(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
 }
 
 static void zynqmp_debug_console_out(char c)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  zynq_uart_write_polled(base, c);
+  zynq_uart_write_char_polled(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs, 
c);
 }
 
 static void zynqmp_debug_console_init(void)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  zynq_uart_initialize(base);
+  zynq_uart_initialize(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
   BSP_output_char = zynqmp_debug_console_out;
 }
 
 static void zynqmp_debug_console_early_init(char c)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  zynq_uart_initialize(base);
+  zynq_uart_initialize(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
   BSP_output_char = zynqmp_debug_console_out;
   zynqmp_debug_console_out(c);
 }
 
 static int zynqmp_debug_console_in(void)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  return zynq_uart_read_polled(base);
+  return 
zynq_uart_read_char_polled(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
 }
 
 BSP_output_char_function_type BSP_output_char = 
zynqmp_debug_console_early_init;
diff --git a/bsps/arm/xilinx-zynq/console/debug-console.c 
b/bsps/arm/xilinx-zynq/console/debug-console.c
index d398ca7988..4c636038af 100644
--- a/bsps/arm/xilinx-zynq/console/debug-console.c
+++ b/bsps/arm/xilinx-zynq/console/debug-console.c
@@ -44,24 +44,18 @@
 
 static void zynq_debug_console_out(char c)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  zynq_uart_write_polled(base, c);
+  zynq_uart_write_char_polled(zynq_uart_instances[BSP_CONSOLE_MINOR].regs, c);
 }
 
 static void zynq_debug_console_early_init(char c);
 
 static void zynq_debug_console_init(void)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
   if (BSP_output_char != zynq_debug_console_early_init) {
 return;
   }
 
-  zynq_uart_initialize(base);
+  zynq_uart_initialize(zynq_uart_instances[BSP_CONSOLE_MINOR].regs);
   BSP_output_char = zynq_debug_console_out;
 }
 
@@ -73,10 +67,7 @@ static void zynq_debug_console_early_init(char c)
 
 static int zynq_debug_console_in(void)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  return zynq_uart_read_polled(base);
+  return 
zynq_uart_read_char_polled(zynq_uart_instances[BSP_CONSOLE_MINOR].regs);
 }
 
 BSP_output_char_function_type BSP_output_char = zynq_debug_console_early_init;
diff --git a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c 
b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
index f52e008f2b..eacf6ddcce 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
@@ -37,6 +37,7 @@
 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -81,41 +82,29 @@ rtems_status_code console_initialize(
 
 void zynqmp_debug_console_flush(void)
 {
-  zynq_uart_reset_tx_flush(_uart_instances[BSP_CONSOLE_MINOR]);
+  zynq_uart_reset_tx_flush(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
 }
 
 static void zynqmp_debug_console_out(char c)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  zynq_uart_write_polled(base, c);
+  zynq_uart_write_char_polled(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs, 
c);
 }
 
 static void zynqmp_debug_console_init(void)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  zynq_uart_initialize(base);
+  

Re: [PATCH] bsps/xilinx-zynqmp-rpu: Avoid constant UART reinit

[Sebastian Huber]

On 27.03.24 18:34, Kinsey Moore wrote:

Constant reinitializations for BSP_output_char causes loss of output
data on QEMU. This change only initializes the UART once.


This is also fixed by my recent UART patch set. I would prefer to clean 
up this copy and paste nightmare.


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Re: [PATCH rtems6] Fix: type-cast to wrong type

[Sebastian Huber]

On 25.03.24 21:44, berndmoessne...@gmail.com wrote:

From: Bernd Moessner 

---
  bsps/include/bsp/irq-generic.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bsps/include/bsp/irq-generic.h b/bsps/include/bsp/irq-generic.h
index 5ed9cac688..31f345486f 100644
--- a/bsps/include/bsp/irq-generic.h
+++ b/bsps/include/bsp/irq-generic.h
@@ -417,7 +417,7 @@ static inline void bsp_interrupt_entry_store_release(
  #if defined(RTEMS_SMP)
_Atomic_Store_uintptr(
  (Atomic_Uintptr *) ptr,
-(Atomic_Uintptr) value,
+(uintptr_t) value,
  ATOMIC_ORDER_RELEASE
);
  #else


Thanks, I checked it in.

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phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

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Re: Xilinx header files installed by BSP

[Sebastian Huber]

On 25.03.24 21:36, Bernd Moessner wrote:


On 25.03.2024 13:26, Sebastian Huber wrote:

Hello,

the BSPs for the Xilinx Zynq/ZynqMP/Versal platforms use code from 
Xilinx. They also install some header files from Xilinx in the 
top-level include directory of the BSP, for example:


sleep.h  xbasic_types.h  xil_assert.h  xil_cache.h xil_exception.h 
xil_io.h  xil_mem.h  xil_printf.h  xil_smc.h xil_types.h xparameters.h 
 xpseudo_asm_gcc.h  xpseudo_asm.h xreg_cortexa53.h xstatus.h


This can lead to conflicts if I would like to build software from

https://github.com/Xilinx/embeddedsw

because now some header files are duplicated and available through 
different include paths. Why do we install these header files? I think 
they should be only used internally to build the BSP provided drivers. 
The RTEMS drivers should expose their interfaces not through the 
Xilinx header files.


Any objections to remove the installation of the Xilinx header files?


Dear Sebastian,

Zynq 7000 is not using them. Rtems-lwip requires some of the headers. I 
provided a patch which added "objxilinxsupport.yml" to the Zynq 7000 
configurations. After a discussion on Discord my patch was rolled back 
(which I think was a good decision).


Chris and Kinsey, please correct me if I misunderstood something, but as 
far as I understood it the headers will be removed from the kernel. 
Afaik, there are some drivers for the ZU require them. Thus, it will 
require some time / planning to overwork the drivers and move the 
required headers to rtems-lwip.


Long story short, Chris and Kinsey should be able to give some more 
detailed information on the strategy and timeline.


Maybe one option is to install the BSP-provided Xilinx headers in bsp/, 
for example:


#include 

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[PATCH v2] RTEMS: Add multilib configuration for aarch64

[Sebastian Huber]

Add a multilib with workarounds for Cortex-A53 errata.

gcc/ChangeLog:

* config.gcc (aarch64-*-rtems*): Add target makefile fragment
t-aarch64-rtems.
* config/aarch64/t-aarch64-rtems: New file.
---
 gcc/config.gcc |  1 +
 gcc/config/aarch64/t-aarch64-rtems | 42 ++
 2 files changed, 43 insertions(+)
 create mode 100644 gcc/config/aarch64/t-aarch64-rtems

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 648b3dc2110..c3b73d05eb7 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -1139,6 +1139,7 @@ aarch64*-*-elf | aarch64*-*-fuchsia* | aarch64*-*-rtems*)
 ;;
aarch64-*-rtems*)
tm_file="${tm_file} aarch64/rtems.h rtems.h"
+   tmake_file="${tmake_file} aarch64/t-aarch64-rtems"
;;
esac
case $target in
diff --git a/gcc/config/aarch64/t-aarch64-rtems 
b/gcc/config/aarch64/t-aarch64-rtems
new file mode 100644
index 000..11f8c380222
--- /dev/null
+++ b/gcc/config/aarch64/t-aarch64-rtems
@@ -0,0 +1,42 @@
+# Machine description for AArch64 architecture.
+#  Copyright (C) 2024 Free Software Foundation, Inc.
+#
+#  This file is part of GCC.
+#
+#  GCC is free software; you can redistribute it and/or modify it
+#  under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; either version 3, or (at your option)
+#  any later version.
+#
+#  GCC is distributed in the hope that it will be useful, but
+#  WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+#  General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with GCC; see the file COPYING3.  If not see
+#  .
+
+MULTILIB_OPTIONS  =
+MULTILIB_DIRNAMES =
+
+MULTILIB_OPTIONS  += mabi=ilp32
+MULTILIB_DIRNAMES += ilp32
+
+MULTILIB_OPTIONS  += mno-outline-atomics
+MULTILIB_DIRNAMES += nooa
+
+MULTILIB_OPTIONS  += mcpu=cortex-a53
+MULTILIB_DIRNAMES += a53
+
+MULTILIB_OPTIONS  += mfix-cortex-a53-835769
+MULTILIB_DIRNAMES += fix835769
+
+MULTILIB_OPTIONS  += mfix-cortex-a53-843419
+MULTILIB_DIRNAMES += fix843419
+
+MULTILIB_REQUIRED =
+
+MULTILIB_REQUIRED += mabi=ilp32
+MULTILIB_REQUIRED += 
mabi=ilp32/mno-outline-atomics/mcpu=cortex-a53/mfix-cortex-a53-835769/mfix-cortex-a53-843419
+MULTILIB_REQUIRED += 
mno-outline-atomics/mcpu=cortex-a53/mfix-cortex-a53-835769/mfix-cortex-a53-843419
-- 
2.35.3

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Xilinx header files installed by BSP

[Sebastian Huber]

Hello,

the BSPs for the Xilinx Zynq/ZynqMP/Versal platforms use code from 
Xilinx. They also install some header files from Xilinx in the top-level 
include directory of the BSP, for example:


sleep.h  xbasic_types.h  xil_assert.h  xil_cache.h  xil_exception.h 
xil_io.h  xil_mem.h  xil_printf.h  xil_smc.h  xil_types.h  xparameters.h 
 xpseudo_asm_gcc.h  xpseudo_asm.h  xreg_cortexa53.h  xstatus.h


This can lead to conflicts if I would like to build software from

https://github.com/Xilinx/embeddedsw

because now some header files are duplicated and available through 
different include paths. Why do we install these header files? I think 
they should be only used internally to build the BSP provided drivers. 
The RTEMS drivers should expose their interfaces not through the Xilinx 
header files.


Any objections to remove the installation of the Xilinx header files?

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[GCC] RTEMS: Add multilib configuration for aarch64

[Sebastian Huber]

gcc/ChangeLog:

* config.gcc (aarch64-*-rtems*): Add target makefile fragment
t-aarch64-rtems.
* config/aarch64/t-aarch64-rtems: New file.
---
 gcc/config.gcc |  1 +
 gcc/config/aarch64/t-aarch64-rtems | 41 ++
 2 files changed, 42 insertions(+)
 create mode 100644 gcc/config/aarch64/t-aarch64-rtems

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 648b3dc2110..c3b73d05eb7 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -1139,6 +1139,7 @@ aarch64*-*-elf | aarch64*-*-fuchsia* | aarch64*-*-rtems*)
 ;;
aarch64-*-rtems*)
tm_file="${tm_file} aarch64/rtems.h rtems.h"
+   tmake_file="${tmake_file} aarch64/t-aarch64-rtems"
;;
esac
case $target in
diff --git a/gcc/config/aarch64/t-aarch64-rtems 
b/gcc/config/aarch64/t-aarch64-rtems
new file mode 100644
index 000..88e07f54551
--- /dev/null
+++ b/gcc/config/aarch64/t-aarch64-rtems
@@ -0,0 +1,41 @@
+# Machine description for AArch64 architecture.
+#  Copyright (C) 2024 Free Software Foundation, Inc.
+#
+#  This file is part of GCC.
+#
+#  GCC is free software; you can redistribute it and/or modify it
+#  under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; either version 3, or (at your option)
+#  any later version.
+#
+#  GCC is distributed in the hope that it will be useful, but
+#  WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+#  General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with GCC; see the file COPYING3.  If not see
+#  .
+
+MULTILIB_OPTIONS  =
+MULTILIB_DIRNAMES =
+
+MULTILIB_OPTIONS  += mabi=ilp32
+MULTILIB_DIRNAMES += ilp32
+
+MULTILIB_OPTIONS  += mno-outline-atomics
+MULTILIB_DIRNAMES += nooa
+
+MULTILIB_OPTIONS  += mcpu=cortex-a53
+MULTILIB_DIRNAMES += a53
+
+MULTILIB_OPTIONS  += mfix-cortex-a53-835769
+MULTILIB_DIRNAMES += fix835769
+
+MULTILIB_OPTIONS  += mfix-cortex-a53-843419
+MULTILIB_DIRNAMES += fix843419
+
+MULTILIB_REQUIRED =
+
+MULTILIB_REQUIRED += mabi=ilp32
+MULTILIB_REQUIRED += 
mno-outline-atomics/mcpu=cortex-a53/mfix-cortex-a53-835769/mfix-cortex-a53-843419
-- 
2.35.3

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aarch64: -mno-outline-atomics

[Sebastian Huber]

Hello,

I noticed that the aarch64/xilinx-zynqmp BSPs use -mno-outline-atomics. 
However, we don't have a corresponding multilib for this. So for 
example, the C++ standard library still uses -moutline-atomics. I 
suggest to add this option to a Cortex-A53 specific multilib. See also:


http://devel.rtems.org/ticket/5003

Do we need an ILP32 multilib for Cortex-A53?

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Re: RFC: Add API to get and set interrupt priorities for interrupt vectors

[Sebastian Huber]

On 21.03.24 20:28, Gedare Bloom wrote:

Two basic questions:

Does the priority field type need to be Architecture- or BSP-defined
or is uint32_t always going to be fine.


In theory, the priority range depends on the interrupt controller 
implementation. However, an uint32_t should be more than enough. The 
maximum priority value defines also the maximum interrupt nesting depth. 
So, even 256 interrupt priority levels would be quite a lot.




Does changing (increasing) the priority of a vector from within
interrupt context possibly cause a pending interrupt to post that was
previously at a lower priority than the currently masked priority
level? In that case, it would cause a preemption to occur. I'm
guessing this behavior could be architecture-specific.


This behaviour is entirely interrupt-controller specific. Changing the 
priority while an interrupt is active is usually a bad idea since this 
can confuse the hardware interrupt priority stack. I guess we have to 
add some interrupt-controller specific information to the notes, for 
example:


For the Armv7-M NVIC, there are 256 priority levels supported.  The 
granularity of the priority levels depends on the interrupt controller 
configuration.  Some lower bits of a priority value may be read-as-zero. 
Interrupts with a priority value less than 128 are not disabled by the 
RTEMS interrupt disable directive. Such interrupts shall not use 
operating system services.


For the Arm GICv2, ...

For the Arm GICv3, ...



I added those questions to the ticket also.
Gedare

On Wed, Mar 20, 2024 at 2:59 AM Sebastian Huber
 wrote:


Hello,

I added a ticket for a proposal for an API to get and set interrupt
priorities for interrupt vectors:

https://devel.rtems.org/ticket/5002

I would like to implement this API at least for the BSPs using the
ARM/AArch64 GIC.

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Re: [PATCH 2/3] dev/serial: Add ZYNQ_UART_[01]_BASE_ADDR

[Sebastian Huber]

On 22.03.24 16:10, Kinsey Moore wrote:
Putting these UART addresses in BSP options suggests that they're 
user-configurable when they aren't. ZynqMP can use the ZYNQMP_UART0/1 
from bsps/include/peripheral_maps/xilinx_zynqmp.h, but Zynq would need 
its own peripheral map to reference.


This UART support is used by four BSP families. Currently a lot of copy 
and past is involved. Defining the two UART base addresses though a BSP 
option was the easiest approach I found to do this. I would remove the 
xilinx_zynqmp.h header file since normally you use the xparameters.h for 
your application depending on the system configuration.


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Re: [PATCH 5/5] bsps: Add xilinx_zynqmp_lp64_a53 BSP variant

[Sebastian Huber]

On 22.03.24 20:57, Gedare Bloom wrote:

In some other architectures we have had "generic" BSP targets. It
would be good to have something following the lp64 part.  I'm not
quite clear on what the purpose of this generic BSP target is here.


For this platform, there is no need for having specific BSPs. The 
customization can be done through BSP options and a device tree. The 
only thing we need are the right compiler options.


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Re: [PATCH 5/5] bsps: Add xilinx_zynqmp_lp64_a53 BSP variant

[Sebastian Huber]

On 22.03.24 16:48, Kinsey Moore wrote:
This patch looks good. I would suggest dropping the a53 from the BSP 
name since all AArch64 ZynqMP BSPs will run on the A53 cores.


We should keep this name. Maybe Xilinx provides a Zynq variant with 
other cores in the future and for the Cortex-A53 we have to enable some 
errata workarounds:


https://devel.rtems.org/ticket/5003

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[PATCH] rtems: Avoid -Wundef warnings in API header

[Sebastian Huber]

---
 cpukit/include/rtems/score/basedefs.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/cpukit/include/rtems/score/basedefs.h 
b/cpukit/include/rtems/score/basedefs.h
index 4f28e6a525..010728d795 100644
--- a/cpukit/include/rtems/score/basedefs.h
+++ b/cpukit/include/rtems/score/basedefs.h
@@ -168,9 +168,9 @@ extern "C" {
  *
  * @return Returns the alignment requirement of the type.
  */
-#if __cplusplus >= 201103L
+#if defined( __cplusplus ) && __cplusplus >= 201103L
   #define RTEMS_ALIGNOF( _type_name ) alignof( _type_name )
-#elif __STDC_VERSION__ >= 201112L
+#elif defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L
   #define RTEMS_ALIGNOF( _type_name ) _Alignof( _type_name )
 #else
   #define RTEMS_ALIGNOF( _type_name ) sizeof( _type_name )
@@ -376,9 +376,9 @@ extern "C" {
  * @brief Tells the compiler in a function declaration that this function does
  *   not return.
  */
-#if __cplusplus >= 201103L
+#if defined( __cplusplus ) && __cplusplus >= 201103L
   #define RTEMS_NO_RETURN [[noreturn]]
-#elif __STDC_VERSION__ >= 201112L
+#elif defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L
   #define RTEMS_NO_RETURN _Noreturn
 #elif defined(__GNUC__)
   #define RTEMS_NO_RETURN __attribute__(( __noreturn__ ))
@@ -833,9 +833,9 @@ extern "C" {
  *
  * @param _msg is the error message in case the static assertion fails.
  */
-#if __cplusplus >= 201103L
+#if defined( __cplusplus ) && __cplusplus >= 201103L
   #define RTEMS_STATIC_ASSERT( _cond, _msg ) static_assert( _cond, # _msg )
-#elif __STDC_VERSION__ >= 201112L
+#elif defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L
   #define RTEMS_STATIC_ASSERT( _cond, _msg ) _Static_assert( _cond, # _msg )
 #else
   #define RTEMS_STATIC_ASSERT( _cond, _msg ) \
-- 
2.35.3

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[PATCH 1/3] dev/serial: Simplify some Zynq UART functions

[Sebastian Huber]

Make the initialization and polled functions independent of the Termios
context.  This helps to implement the kernel I/O support without a dependency
on the Termios framework.
---
 bsps/aarch64/xilinx-zynqmp/console/console.c  | 23 ---
 bsps/arm/xilinx-zynq/console/debug-console.c  | 15 ++
 .../console/console-config.c  | 23 ---
 .../xilinx-zynqmp/console/console-config.c| 23 ---
 bsps/include/dev/serial/zynq-uart-regs.h  | 20 +
 bsps/include/dev/serial/zynq-uart.h   | 23 ---
 bsps/shared/dev/serial/zynq-uart-polled.c | 28 ++-
 bsps/shared/dev/serial/zynq-uart.c| 18 
 8 files changed, 62 insertions(+), 111 deletions(-)

diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c 
b/bsps/aarch64/xilinx-zynqmp/console/console.c
index 9ce0b1da63..1e5df997e8 100644
--- a/bsps/aarch64/xilinx-zynqmp/console/console.c
+++ b/bsps/aarch64/xilinx-zynqmp/console/console.c
@@ -45,6 +45,7 @@
 #include 
 
 #include 
+#include 
 
 #include 
 #include 
@@ -236,42 +237,30 @@ rtems_status_code console_initialize(
 
 void zynqmp_debug_console_flush(void)
 {
-  zynq_uart_reset_tx_flush(_uart_instances[BSP_CONSOLE_MINOR]);
+  zynq_uart_reset_tx_flush(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
 }
 
 static void zynqmp_debug_console_out(char c)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  zynq_uart_write_polled(base, c);
+  zynq_uart_write_char_polled(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs, 
c);
 }
 
 static void zynqmp_debug_console_init(void)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  zynq_uart_initialize(base);
+  zynq_uart_initialize(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
   BSP_output_char = zynqmp_debug_console_out;
 }
 
 static void zynqmp_debug_console_early_init(char c)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  zynq_uart_initialize(base);
+  zynq_uart_initialize(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
   BSP_output_char = zynqmp_debug_console_out;
   zynqmp_debug_console_out(c);
 }
 
 static int zynqmp_debug_console_in(void)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  return zynq_uart_read_polled(base);
+  return 
zynq_uart_read_char_polled(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
 }
 
 BSP_output_char_function_type BSP_output_char = 
zynqmp_debug_console_early_init;
diff --git a/bsps/arm/xilinx-zynq/console/debug-console.c 
b/bsps/arm/xilinx-zynq/console/debug-console.c
index d398ca7988..4c636038af 100644
--- a/bsps/arm/xilinx-zynq/console/debug-console.c
+++ b/bsps/arm/xilinx-zynq/console/debug-console.c
@@ -44,24 +44,18 @@
 
 static void zynq_debug_console_out(char c)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  zynq_uart_write_polled(base, c);
+  zynq_uart_write_char_polled(zynq_uart_instances[BSP_CONSOLE_MINOR].regs, c);
 }
 
 static void zynq_debug_console_early_init(char c);
 
 static void zynq_debug_console_init(void)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
   if (BSP_output_char != zynq_debug_console_early_init) {
 return;
   }
 
-  zynq_uart_initialize(base);
+  zynq_uart_initialize(zynq_uart_instances[BSP_CONSOLE_MINOR].regs);
   BSP_output_char = zynq_debug_console_out;
 }
 
@@ -73,10 +67,7 @@ static void zynq_debug_console_early_init(char c)
 
 static int zynq_debug_console_in(void)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  return zynq_uart_read_polled(base);
+  return 
zynq_uart_read_char_polled(zynq_uart_instances[BSP_CONSOLE_MINOR].regs);
 }
 
 BSP_output_char_function_type BSP_output_char = zynq_debug_console_early_init;
diff --git a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c 
b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
index f52e008f2b..eacf6ddcce 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
@@ -37,6 +37,7 @@
 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -81,41 +82,29 @@ rtems_status_code console_initialize(
 
 void zynqmp_debug_console_flush(void)
 {
-  zynq_uart_reset_tx_flush(_uart_instances[BSP_CONSOLE_MINOR]);
+  zynq_uart_reset_tx_flush(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
 }
 
 static void zynqmp_debug_console_out(char c)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  zynq_uart_write_polled(base, c);
+  zynq_uart_write_char_polled(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs, 
c);
 }
 
 static void zynqmp_debug_console_init(void)
 {
-  rtems_termios_device_context *base =
-_uart_instances[BSP_CONSOLE_MINOR].base;
-
-  zynq_uart_initialize(base);
+  

[PATCH 3/3] dev/serial: Add Zynq UART kernel I/O support

[Sebastian Huber]

Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new
BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR.  Move the kernel I/O support to a
shared file.
---
 bsps/aarch64/xilinx-zynqmp/console/console.c  | 41 ++
 bsps/arm/xilinx-zynq/console/console-config.c | 50 -
 bsps/arm/xilinx-zynq/console/console-init.c   | 20 ++-
 bsps/arm/xilinx-zynq/include/bsp.h|  3 --
 bsps/arm/xilinx-zynq/start/bspreset.c |  6 ++-
 .../console/console-config.c  | 40 ++
 .../xilinx-zynqmp/console/console-config.c| 40 ++
 .../dev/serial/zynq-uart-kernel-io.c} | 53 +++
 spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml |  2 -
 spec/build/bsps/arm/xilinx-zynq/grp.yml   |  2 -
 spec/build/bsps/arm/xilinx-zynq/obj.yml   |  2 -
 spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml |  2 -
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  2 -
 spec/build/bsps/objdevserialzynq.yml  |  3 ++
 spec/build/bsps/optconminor.yml   | 21 
 spec/build/bsps/optzynquartkernbase.yml   | 22 
 16 files changed, 89 insertions(+), 220 deletions(-)
 delete mode 100644 bsps/arm/xilinx-zynq/console/console-config.c
 rename bsps/{arm/xilinx-zynq/console/debug-console.c => 
shared/dev/serial/zynq-uart-kernel-io.c} (60%)
 delete mode 100644 spec/build/bsps/optconminor.yml
 create mode 100644 spec/build/bsps/optzynquartkernbase.yml

diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c 
b/bsps/aarch64/xilinx-zynqmp/console/console.c
index ce031a914e..4023d5c6f3 100644
--- a/bsps/aarch64/xilinx-zynqmp/console/console.c
+++ b/bsps/aarch64/xilinx-zynqmp/console/console.c
@@ -35,7 +35,6 @@
  */
 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -208,6 +207,7 @@ rtems_status_code console_initialize(
   rtems_termios_initialize();
 
   for (i = 0; i < RTEMS_ARRAY_SIZE(zynqmp_uart_instances); ++i) {
+zynq_uart_context *ctx = _uart_instances[i];
 char uart[] = "/dev/ttySX";
 
 uart[sizeof(uart) - 2] = (char) ('0' + i);
@@ -215,10 +215,10 @@ rtems_status_code console_initialize(
   [0],
   _uart_handler,
   NULL,
-  _uart_instances[i].base
+  >base
 );
 
-if (i == BSP_CONSOLE_MINOR) {
+if (ctx->regs == (zynq_uart *) ZYNQ_UART_KERNEL_IO_BASE_ADDR) {
   link([0], CONSOLE_DEVICE_NAME);
 }
   }
@@ -237,38 +237,5 @@ rtems_status_code console_initialize(
 
 void zynqmp_debug_console_flush(void)
 {
-  zynq_uart_reset_tx_flush(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
+  zynq_uart_reset_tx_flush((zynq_uart *) ZYNQ_UART_KERNEL_IO_BASE_ADDR);
 }
-
-static void zynqmp_debug_console_out(char c)
-{
-  zynq_uart_write_char_polled(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs, 
c);
-}
-
-static void zynqmp_debug_console_init(void)
-{
-  zynq_uart_initialize(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
-  BSP_output_char = zynqmp_debug_console_out;
-}
-
-static void zynqmp_debug_console_early_init(char c)
-{
-  zynq_uart_initialize(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
-  BSP_output_char = zynqmp_debug_console_out;
-  zynqmp_debug_console_out(c);
-}
-
-static int zynqmp_debug_console_in(void)
-{
-  return 
zynq_uart_read_char_polled(zynqmp_uart_instances[BSP_CONSOLE_MINOR].regs);
-}
-
-BSP_output_char_function_type BSP_output_char = 
zynqmp_debug_console_early_init;
-
-BSP_polling_getchar_function_type BSP_poll_char = zynqmp_debug_console_in;
-
-RTEMS_SYSINIT_ITEM(
-  zynqmp_debug_console_init,
-  RTEMS_SYSINIT_BSP_START,
-  RTEMS_SYSINIT_ORDER_LAST_BUT_5
-);
diff --git a/bsps/arm/xilinx-zynq/console/console-config.c 
b/bsps/arm/xilinx-zynq/console/console-config.c
deleted file mode 100644
index 42e64ee4dd..00
--- a/bsps/arm/xilinx-zynq/console/console-config.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMZynq
- *
- * @brief This source file contains the definition of ::zynq_uart_instances.
- */
-
-/*
- * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *notice, this list of conditions and the following disclaimer in the
- *documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 

[PATCH 2/3] dev/serial: Add ZYNQ_UART_[01]_BASE_ADDR

[Sebastian Huber]

This helps to provide a shared implementation of the kernel I/O support.
---
 bsps/aarch64/xilinx-zynqmp/console/console.c  |  4 ++--
 bsps/arm/xilinx-zynq/console/console-config.c |  5 +++--
 .../console/console-config.c  |  4 ++--
 .../xilinx-zynqmp/console/console-config.c|  4 ++--
 spec/build/bsps/objdevserialzynq.yml  |  6 +-
 spec/build/bsps/optzynquart0base.yml  | 19 +++
 spec/build/bsps/optzynquart1base.yml  | 19 +++
 7 files changed, 52 insertions(+), 9 deletions(-)
 create mode 100644 spec/build/bsps/optzynquart0base.yml
 create mode 100644 spec/build/bsps/optzynquart1base.yml

diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c 
b/bsps/aarch64/xilinx-zynqmp/console/console.c
index 1e5df997e8..ce031a914e 100644
--- a/bsps/aarch64/xilinx-zynqmp/console/console.c
+++ b/bsps/aarch64/xilinx-zynqmp/console/console.c
@@ -188,11 +188,11 @@ RTEMS_SYSINIT_ITEM(
 static zynq_uart_context zynqmp_uart_instances[2] = {
   {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-.regs = (volatile struct zynq_uart *) 0xff00,
+.regs = (volatile zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
 .irq = ZYNQMP_IRQ_UART_0
   }, {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-.regs = (volatile struct zynq_uart *) 0xff01,
+.regs = (volatile zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
 .irq = ZYNQMP_IRQ_UART_1
   }
 };
diff --git a/bsps/arm/xilinx-zynq/console/console-config.c 
b/bsps/arm/xilinx-zynq/console/console-config.c
index d22ceb557d..42e64ee4dd 100644
--- a/bsps/arm/xilinx-zynq/console/console-config.c
+++ b/bsps/arm/xilinx-zynq/console/console-config.c
@@ -35,15 +35,16 @@
 
 #include 
 #include 
+#include 
 
 zynq_uart_context zynq_uart_instances[2] = {
   {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-.regs = (volatile struct zynq_uart *) 0xe000,
+.regs = (volatile zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
 .irq = ZYNQ_IRQ_UART_0
   }, {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-.regs = (volatile struct zynq_uart *) 0xe0001000,
+.regs = (volatile zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
 .irq = ZYNQ_IRQ_UART_1
   }
 };
diff --git a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c 
b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
index eacf6ddcce..13eaa269c5 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
@@ -44,11 +44,11 @@
 static zynq_uart_context zynqmp_uart_instances[2] = {
   {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-.regs = (volatile struct zynq_uart *) 0xff00,
+.regs = (volatile zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
 .irq = ZYNQMP_IRQ_UART_0
   }, {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-.regs = (volatile struct zynq_uart *) 0xff01,
+.regs = (volatile zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
 .irq = ZYNQMP_IRQ_UART_1
   }
 };
diff --git a/bsps/arm/xilinx-zynqmp/console/console-config.c 
b/bsps/arm/xilinx-zynqmp/console/console-config.c
index ea148836a5..787ee05dd6 100644
--- a/bsps/arm/xilinx-zynqmp/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp/console/console-config.c
@@ -44,11 +44,11 @@
 static zynq_uart_context zynqmp_uart_instances[2] = {
   {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-.regs = (volatile struct zynq_uart *) 0xff00,
+.regs = (volatile struct zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
 .irq = ZYNQMP_IRQ_UART_0
   }, {
 .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-.regs = (volatile struct zynq_uart *) 0xff01,
+.regs = (volatile struct zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
 .irq = ZYNQMP_IRQ_UART_1
   }
 };
diff --git a/spec/build/bsps/objdevserialzynq.yml 
b/spec/build/bsps/objdevserialzynq.yml
index deb3c83a33..ec61f7f545 100644
--- a/spec/build/bsps/objdevserialzynq.yml
+++ b/spec/build/bsps/objdevserialzynq.yml
@@ -12,7 +12,11 @@ install:
   source:
   - bsps/include/dev/serial/zynq-uart-regs.h
   - bsps/include/dev/serial/zynq-uart.h
-links: []
+links:
+- role: build-dependency
+  uid: optzynquart0base
+- role: build-dependency
+  uid: optzynquart1base
 source:
 - bsps/shared/dev/serial/zynq-uart-polled.c
 - bsps/shared/dev/serial/zynq-uart.c
diff --git a/spec/build/bsps/optzynquart0base.yml 
b/spec/build/bsps/optzynquart0base.yml
new file mode 100644
index 00..1da4e2d1ea
--- /dev/null
+++ b/spec/build/bsps/optzynquart0base.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: bsps/arm/xilinx-zynq
+  value: 0xe000
+- enabled-by: true
+  value: 0xff00
+description: |
+  This option defines the Xilinx Zynq 

[PATCH 0/3] Add shared Zynq UART kernel I/O support

[Sebastian Huber]

Sebastian Huber (3):
  dev/serial: Simplify some Zynq UART functions
  dev/serial: Add ZYNQ_UART_[01]_BASE_ADDR
  dev/serial: Add Zynq UART kernel I/O support

 bsps/aarch64/xilinx-zynqmp/console/console.c  | 58 +++
 bsps/arm/xilinx-zynq/console/console-config.c | 49 
 bsps/arm/xilinx-zynq/console/console-init.c   | 20 ++-
 bsps/arm/xilinx-zynq/include/bsp.h|  3 -
 bsps/arm/xilinx-zynq/start/bspreset.c |  6 +-
 .../console/console-config.c  | 57 +++---
 .../xilinx-zynqmp/console/console-config.c| 57 +++---
 bsps/include/dev/serial/zynq-uart-regs.h  | 20 +++
 bsps/include/dev/serial/zynq-uart.h   | 23 
 .../dev/serial/zynq-uart-kernel-io.c} | 58 +--
 bsps/shared/dev/serial/zynq-uart-polled.c | 28 +++--
 bsps/shared/dev/serial/zynq-uart.c| 18 --
 spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml |  2 -
 spec/build/bsps/arm/xilinx-zynq/grp.yml   |  2 -
 spec/build/bsps/arm/xilinx-zynq/obj.yml   |  2 -
 spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml |  2 -
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  2 -
 spec/build/bsps/objdevserialzynq.yml  |  9 ++-
 spec/build/bsps/optconminor.yml   | 21 ---
 spec/build/bsps/optzynquart0base.yml  | 19 ++
 spec/build/bsps/optzynquart1base.yml  | 19 ++
 spec/build/bsps/optzynquartkernbase.yml   | 22 +++
 22 files changed, 180 insertions(+), 317 deletions(-)
 delete mode 100644 bsps/arm/xilinx-zynq/console/console-config.c
 rename bsps/{arm/xilinx-zynq/console/debug-console.c => 
shared/dev/serial/zynq-uart-kernel-io.c} (61%)
 delete mode 100644 spec/build/bsps/optconminor.yml
 create mode 100644 spec/build/bsps/optzynquart0base.yml
 create mode 100644 spec/build/bsps/optzynquart1base.yml
 create mode 100644 spec/build/bsps/optzynquartkernbase.yml

-- 
2.35.3

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[PATCH] bsp-howto: Document clock driver arg parameter

[Sebastian Huber]

Update #4862.
---
 bsp-howto/clock.rst | 34 ++
 1 file changed, 22 insertions(+), 12 deletions(-)

diff --git a/bsp-howto/clock.rst b/bsp-howto/clock.rst
index 043083f..ed83472 100644
--- a/bsp-howto/clock.rst
+++ b/bsp-howto/clock.rst
@@ -139,6 +139,9 @@ Simple Timecounter Variant
 
 For an example see the `ERC32 clock driver
 `_.
+The argument parameter of ``Clock_driver_timecounter_tick( arg )`` is the
+argument used to install the clock interrupt handler.  Device drivers may use
+this argument to access their control state.
 
 .. code-block:: c
 
@@ -165,9 +168,9 @@ For an example see the `ERC32 clock driver
   );
 }
 
-static void some_tc_tick( void )
+static void some_tc_tick( rtems_timecounter_simple *tc )
 {
-  rtems_timecounter_simple_downcounter_tick( _tc, some_tc_get );
+  rtems_timecounter_simple_downcounter_tick( tc, some_tc_get );
 }
 
 static void some_support_initialize_hardware( void )
@@ -193,8 +196,8 @@ For an example see the `ERC32 clock driver
 
 #define Clock_driver_support_initialize_hardware() \
   some_support_initialize_hardware()
-#define Clock_driver_timecounter_tick() \
-  some_tc_tick()
+#define Clock_driver_timecounter_tick( arg ) \
+  some_tc_tick( arg )
 
 #include "../../../shared/dev/clock/clockimpl.h"
 
@@ -224,15 +227,20 @@ Install Clock Tick Interrupt Service Routine
 
 
 The clock driver may provide a function to install the clock tick interrupt
-service routine via ``Clock_driver_support_install_isr()``.  The clock tick
-interrupt service routine is passed as the one and only parameter to this
-macro.  The default implementation will do nothing.
+service routine via ``Clock_driver_support_install_isr( isr )``.  The clock
+tick interrupt service routine is passed as the one and only parameter to this
+macro.  The default implementation will do nothing.  The argument parameter (in
+the code below ``_instance``) for the installed interrupt handler is
+available in the ``Clock_driver_support_at_tick( arg )`` and
+``Clock_driver_support_initialize_hardware( arg )`` customization macros.
 
 .. code-block:: c
 
 #include 
 #include 
 
+static some_control some_instance;
+
 static void some_support_install_isr( rtems_interrupt_handler isr )
 {
   rtems_status_code sc;
@@ -241,7 +249,7 @@ macro.  The default implementation will do nothing.
 "Clock",
 RTEMS_INTERRUPT_UNIQUE,
 isr,
-NULL
+_instance
   );
   if ( sc != RTEMS_SUCCESSFUL ) {
 bsp_fatal( SOME_FATAL_IRQ_INSTALL );
@@ -257,17 +265,19 @@ Support At Tick
 ===
 
 The hardware-specific support at tick is specified by
-``Clock_driver_support_at_tick()``.
+``Clock_driver_support_at_tick( arg )``.  The ``arg`` is the argument used to
+install the clock interrupt handler.  Device drivers may use this argument to
+access their control state.
 
 .. code-block:: c
 
-static void some_support_at_tick( void )
+static void some_support_at_tick( some_control *arg )
 {
   /* Clear interrupt */
 }
 
-#define Clock_driver_support_at_tick() \
-  some_support_at_tick()
+#define Clock_driver_support_at_tick( arg ) \
+  some_support_at_tick( arg )
 
 #include "../../../shared/dev/clock/clockimpl.h"
 
-- 
2.35.3

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Re: [Docs] c-user: Clarify CONFIGURE_TICKS_PER_TIMESLICE

[Sebastian Huber]

On 21.03.24 15:05, Joel Sherrill wrote:

Isn't this content generated from rtems-central?


Yes, it is generated.



Shouldn't there also be a change there?


It should be there:

Module:rtems-central
Branch:master
Commit:f5e42e5d9fae95e50f41a2ed71ee94e9908612c0
Changeset: 
http://git.rtems.org/rtems-central/commit/?id=f5e42e5d9fae95e50f41a2ed71ee94e9908612c0


Author:Sebastian Huber 
Date:  Thu Mar 21 11:55:22 2024 +0100

spec: Fix CONFIGURE_TICKS_PER_TIMESLICE constraint

Update #4986.

--
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Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

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Registernummer: HRB 157899
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Re: [PATCH v2] bsps: Add BSP_FLUSH_KERNEL_CHAR_OUTPUT BSP option

[Sebastian Huber]

On 21.03.24 00:28, Chris Johns wrote:

On 21/3/2024 2:11 am, Sebastian Huber wrote:

On 19.03.24 18:44, Chris Johns wrote:

On 20/3/2024 2:03 am, Sebastian Huber wrote:

On 19.03.24 14:50, Kinsey Moore wrote:

The xilinx-zynqmp-rpu bsp_reset() is modified, but not included in the spec
file for the new option. Its family differs from the arm/xilinx-zynqmp BSP
family with a -rpu suffix.

Yes, but this BSP is quite new. I would prefer to let it not flush anything by
default to carry out a reset.


I'd be fine with this being enabled for the AArch64 BSPs as well, but I
imagine that's better as a separate patch.

Why should it be enabled by default? The arm/xilinx-zynq and arm/xilinx-zynqmp
BSPs were the only ones doing an UART flush in the general termination
procedure. It probably was done to address a specific use case (maybe test
runs).

Is the issue the flush is before an infinite loop which means the UART FIFO
should drain?


What is the issue you are wanting to solve removing the flush?


The bsp_reset() function should reset the system and do nothing more. 
Doing additional things like flushing an UART device may not make sense 
for all applications. Some applications may not use the UART device, so 
it may not be initialized and powered off.  Some applications may use it 
with an application-specific protocol which doesn't like the additional 
four '\r' during reset. Doing a UART flush takes some time and some 
applications may prefer a fast reset time. The bsp_reset() is the wrong 
place to do add specific cleanup functions. Applications can customize 
the termination procedure with their own fatal error extension, 
destructors, and exit handlers.


--
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Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
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[PATCH] bsps: Move declarations to

[Sebastian Huber]

Move declarations of bsp_interrupt_get_affinity() and
bsp_interrupt_set_affinity() to .  Canonicalize the
 includes.

Implement bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if
needed (usually RTEMS_SMP).

Provide stub implementations for i386 to fix build errors.
---
 bsps/aarch64/raspberrypi/include/bsp/irq.h | 28 
 bsps/arm/raspberrypi/include/bsp/irq.h | 28 
 bsps/arm/raspberrypi/irq/irq.c | 23 +-
 bsps/i386/shared/irq/irq.c | 33 ++
 bsps/include/bsp/irq-generic.h | 52 +-
 bsps/include/dev/irq/arm-gic-irq.h | 11 -
 bsps/powerpc/qoriq/clock/clock-config.c|  2 +-
 bsps/powerpc/qoriq/include/bsp/irq.h   | 11 -
 bsps/powerpc/qoriq/irq/irq.c   |  1 -
 bsps/powerpc/t32mppc/include/bsp/irq.h | 23 --
 bsps/powerpc/t32mppc/irq/irq.c | 22 +
 bsps/riscv/griscv/clock/clockdrv.c |  2 +-
 bsps/riscv/griscv/include/bsp/irq.h| 13 --
 bsps/riscv/griscv/irq/irq.c|  1 -
 bsps/riscv/noel/include/bsp/irq.h  | 13 --
 bsps/riscv/riscv/include/bsp/irq.h | 13 --
 bsps/riscv/riscv/irq/irq.c |  1 -
 bsps/shared/dev/irq/arm-gicv2.c|  3 +-
 bsps/shared/dev/irq/arm-gicv3.c|  3 +-
 bsps/shared/irq/irq-affinity.c |  1 -
 bsps/sparc/erc32/include/bsp/irq.h | 22 +
 bsps/sparc/leon3/clock/ckinit.c|  3 +-
 bsps/sparc/leon3/include/bsp/irq.h | 11 -
 bsps/sparc/leon3/include/tm27.h|  2 +-
 bsps/sparc/leon3/start/bspsmp.c|  2 +-
 bsps/sparc/leon3/start/eirq.c  |  1 -
 bsps/sparc/shared/irq/irq-shared.c | 22 +
 27 files changed, 160 insertions(+), 187 deletions(-)

diff --git a/bsps/aarch64/raspberrypi/include/bsp/irq.h 
b/bsps/aarch64/raspberrypi/include/bsp/irq.h
index effec1b040..1ff6ae80de 100644
--- a/bsps/aarch64/raspberrypi/include/bsp/irq.h
+++ b/bsps/aarch64/raspberrypi/include/bsp/irq.h
@@ -23,14 +23,8 @@
 #ifndef ASM
 
 #include 
-#include 
-#include 
 #include 
 
-#if defined(RTEMS_SMP)
-#include 
-#endif
-
 /**
  * @defgroup raspberrypi_interrupt Interrrupt Support
  *
@@ -83,27 +77,5 @@
 
 #define BSP_IRQ_COUNT   (BCM2835_INTC_TOTAL_IRQ)
 
-#if defined(RTEMS_SMP)
-static inline rtems_status_code bsp_interrupt_set_affinity(
-  rtems_vector_number   vector,
-  const Processor_mask *affinity
-)
-{
-  (void) vector;
-  (void) affinity;
-  return RTEMS_UNSATISFIED;
-}
-
-static inline rtems_status_code bsp_interrupt_get_affinity(
-  rtems_vector_number  vector,
-  Processor_mask  *affinity
-)
-{
-  (void) vector;
-  _Processor_mask_From_index( affinity, 0 );
-  return RTEMS_UNSATISFIED;
-}
-#endif
-
 #endif /* ASM */
 #endif /* LIBBSP_ARM_RASPBERRYPI_IRQ_H */
diff --git a/bsps/arm/raspberrypi/include/bsp/irq.h 
b/bsps/arm/raspberrypi/include/bsp/irq.h
index 6801b01d84..895b268dfe 100644
--- a/bsps/arm/raspberrypi/include/bsp/irq.h
+++ b/bsps/arm/raspberrypi/include/bsp/irq.h
@@ -22,12 +22,6 @@
 #ifndef ASM
 
 #include 
-#include 
-#include 
-
-#if defined(RTEMS_SMP)
-#include 
-#endif
 
 /**
  * @defgroup raspberrypi_interrupt Interrrupt Support
@@ -78,27 +72,5 @@
 
 #define BSP_IRQ_COUNT   (BCM2835_INTC_TOTAL_IRQ)
 
-#if defined(RTEMS_SMP)
-static inline rtems_status_code bsp_interrupt_set_affinity(
-  rtems_vector_number   vector,
-  const Processor_mask *affinity
-)
-{
-  (void) vector;
-  (void) affinity;
-  return RTEMS_UNSATISFIED;
-}
-
-static inline rtems_status_code bsp_interrupt_get_affinity(
-  rtems_vector_number  vector,
-  Processor_mask  *affinity
-)
-{
-  (void) vector;
-  _Processor_mask_From_index( affinity, 0 );
-  return RTEMS_UNSATISFIED;
-}
-#endif
-
 #endif /* ASM */
 #endif /* LIBBSP_ARM_RASPBERRYPI_IRQ_H */
diff --git a/bsps/arm/raspberrypi/irq/irq.c b/bsps/arm/raspberrypi/irq/irq.c
index 30e10e5aec..7177cd2c05 100644
--- a/bsps/arm/raspberrypi/irq/irq.c
+++ b/bsps/arm/raspberrypi/irq/irq.c
@@ -19,7 +19,6 @@
 #include 
 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -207,6 +206,28 @@ rtems_status_code 
bsp_interrupt_vector_disable(rtems_vector_number vector)
   return RTEMS_SUCCESSFUL;
 }
 
+#if defined(RTEMS_SMP)
+rtems_status_code bsp_interrupt_get_affinity(
+  rtems_vector_number  vector,
+  Processor_mask  *affinity
+)
+{
+  (void) vector;
+  _Processor_mask_From_index( affinity, 0 );
+  return RTEMS_UNSATISFIED;
+}
+
+rtems_status_code bsp_interrupt_set_affinity(
+  rtems_vector_number   vector,
+  const Processor_mask *affinity
+)
+{
+  (void) vector;
+  (void) affinity;
+  return RTEMS_UNSATISFIED;
+}
+#endif
+
 void bsp_interrupt_handler_default(rtems_vector_number vector)
 {
 printk("spurious interrupt: %" PRIdrtems_vector_number "\n", vector);
diff --git a/bsps/i386/shared/irq/irq.c b/bsps/i386/shared/irq/irq.c
index fe43bc1d7c..57753c2f77 100644
--- 

[PATCH] Mark parameters as intentionally unused

[Sebastian Huber]

The parameters are unused due to API constraints.  The functions are
used through function pointers.  Alternative implementations may use the
parameters.

Close #4862.
---
 bsps/sparc/leon3/start/bspclean.c   | 1 +
 cpukit/score/src/threadchangepriority.c | 1 +
 cpukit/score/src/threadq.c  | 2 ++
 cpukit/score/src/threadqenqueue.c   | 1 +
 cpukit/score/src/threadqops.c   | 2 ++
 cpukit/score/src/threadqtimeout.c   | 1 +
 cpukit/score/src/threadrestart.c| 1 +
 cpukit/score/src/userextiterate.c   | 2 ++
 8 files changed, 11 insertions(+)

diff --git a/bsps/sparc/leon3/start/bspclean.c 
b/bsps/sparc/leon3/start/bspclean.c
index 0324c45326..d624ec74c8 100644
--- a/bsps/sparc/leon3/start/bspclean.c
+++ b/bsps/sparc/leon3/start/bspclean.c
@@ -46,6 +46,7 @@ void bsp_fatal_extension(
 {
   rtems_interrupt_level level;
 
+  (void) always_set_to_false;
   rtems_interrupt_local_disable(level);
   (void) level;
 
diff --git a/cpukit/score/src/threadchangepriority.c 
b/cpukit/score/src/threadchangepriority.c
index ca49f6f417..78291b7798 100644
--- a/cpukit/score/src/threadchangepriority.c
+++ b/cpukit/score/src/threadchangepriority.c
@@ -111,6 +111,7 @@ static void _Thread_Priority_action_change(
   void *arg
 )
 {
+  (void) arg;
   _Thread_Set_scheduler_node_priority(
 priority_aggregation,
 priority_group_order
diff --git a/cpukit/score/src/threadq.c b/cpukit/score/src/threadq.c
index e694029a46..3c6d72bd14 100644
--- a/cpukit/score/src/threadq.c
+++ b/cpukit/score/src/threadq.c
@@ -179,5 +179,7 @@ void _Thread_queue_MP_callout_do_nothing(
 )
 {
   /* Do nothing */
+  (void) the_proxy;
+  (void) mp_id;
 }
 #endif
diff --git a/cpukit/score/src/threadqenqueue.c 
b/cpukit/score/src/threadqenqueue.c
index e43efd925b..038c483f65 100644
--- a/cpukit/score/src/threadqenqueue.c
+++ b/cpukit/score/src/threadqenqueue.c
@@ -400,6 +400,7 @@ void _Thread_queue_Deadlock_status( Thread_Control 
*the_thread )
 
 void _Thread_queue_Deadlock_fatal( Thread_Control *the_thread )
 {
+  (void) the_thread;
   _Internal_error( INTERNAL_ERROR_THREAD_QUEUE_DEADLOCK );
 }
 
diff --git a/cpukit/score/src/threadqops.c b/cpukit/score/src/threadqops.c
index 511d1e4d00..9a09b4c442 100644
--- a/cpukit/score/src/threadqops.c
+++ b/cpukit/score/src/threadqops.c
@@ -156,6 +156,8 @@ static void _Thread_queue_FIFO_do_initialize(
 {
   Scheduler_Node *scheduler_node;
 
+  (void) queue;
+  (void) queue_context;
   scheduler_node = _Thread_Scheduler_get_home_node( the_thread );
 
   _Chain_Initialize_node( _node->Wait.Priority.Node.Node.Chain );
diff --git a/cpukit/score/src/threadqtimeout.c 
b/cpukit/score/src/threadqtimeout.c
index acb3c1d048..e30a2ffded 100644
--- a/cpukit/score/src/threadqtimeout.c
+++ b/cpukit/score/src/threadqtimeout.c
@@ -53,6 +53,7 @@ void _Thread_queue_Add_timeout_ticks(
 {
   Watchdog_Interval ticks;
 
+  (void) queue;
   ticks = queue_context->Timeout.ticks;
 
   if ( ticks != WATCHDOG_NO_TIMEOUT ) {
diff --git a/cpukit/score/src/threadrestart.c b/cpukit/score/src/threadrestart.c
index d1c4b283fb..72326682ca 100644
--- a/cpukit/score/src/threadrestart.c
+++ b/cpukit/score/src/threadrestart.c
@@ -83,6 +83,7 @@ static Thread_Control *_Thread_Join_flush_filter(
 {
   Thread_Join_context *join_context;
 
+  (void) queue;
   join_context = (Thread_Join_context *) queue_context;
 
   the_thread->Wait.return_argument = join_context->exit_value;
diff --git a/cpukit/score/src/userextiterate.c 
b/cpukit/score/src/userextiterate.c
index 6f6790082a..cae76d173c 100644
--- a/cpukit/score/src/userextiterate.c
+++ b/cpukit/score/src/userextiterate.c
@@ -118,6 +118,8 @@ void _User_extensions_Thread_begin_visitor(
 {
   User_extensions_thread_begin_extension callout = callouts->thread_begin;
 
+  (void) arg;
+
   if ( callout != NULL ) {
 (*callout)( executing );
   }
-- 
2.35.3

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Re: [PATCH v2] bsps: Add BSP_FLUSH_KERNEL_CHAR_OUTPUT BSP option

[Sebastian Huber]

On 19.03.24 18:44, Chris Johns wrote:

On 20/3/2024 2:03 am, Sebastian Huber wrote:

On 19.03.24 14:50, Kinsey Moore wrote:

The xilinx-zynqmp-rpu bsp_reset() is modified, but not included in the spec
file for the new option. Its family differs from the arm/xilinx-zynqmp BSP
family with a -rpu suffix.

Yes, but this BSP is quite new. I would prefer to let it not flush anything by
default to carry out a reset.


I'd be fine with this being enabled for the AArch64 BSPs as well, but I
imagine that's better as a separate patch.

Why should it be enabled by default? The arm/xilinx-zynq and arm/xilinx-zynqmp
BSPs were the only ones doing an UART flush in the general termination
procedure. It probably was done to address a specific use case (maybe test 
runs).

Is the issue the flush is before an infinite loop which means the UART FIFO
should drain?


I don't really like the new bsp_flush_kernel_char_output() function. Another
approach could be an API change of

/**
  * @ingroup RTEMSAPIKernelCharIO
  *
  * @brief Polled character output functions shall have this type.
  */
typedef void ( *BSP_output_char_function_type )( char );

to something like this

typedef int ( *BSP_output_char_function_type )( int action );

If action in {0, ..., 255}, then print out the character. If 0x100 is set, then
flush the output device. If 0x200 is set, then do Y... The return value could be
used to give a status indication.

This could then be use for example by test runs, to flush the test output after
the end of the test.

This also requires a code change so is a flush function that bad an option?


You can change the character output handler since this is only a global 
variable (BSP_output_char). So, this bsp_flush_kernel_char_output() may 
not flush the device used by BSP_output_char. Doing a flush through the 
output handler lets you do the flush for the currently used device.


If we change the function type to

typedef int ( *BSP_output_char_function_type )( int action );

then we can add more features later if needed. Another feature which 
could be useful is: Output char immediately if possible and return 0, 
otherwise do nothing and return -1. This can be used to implement a 
full-duplex transfer in polling mode for the kernel I/O stream.


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[PATCH] bsps: Avoid unused argument in clock interrupt

[Sebastian Huber]

Pass the parameter of the clock interrupt handler to
Clock_driver_support_at_tick() and Clock_driver_timecounter_tick().  This makes
it possible to use the interrupt handler argument in clock drivers.

Use the interrupt handler provided by Clock_driver_support_install_isr() to
avoid local delarations of Clock_isr().

Update #4862.
---
 bsps/arm/beagle/clock/clock.c |  2 +-
 bsps/arm/csb336/clock/clockdrv.c  |  2 +-
 bsps/arm/csb337/clock/clock.c |  2 +-
 bsps/arm/edb7312/clock/clockdrv.c |  6 +--
 bsps/arm/gumstix/clock/clock.c|  2 +-
 bsps/arm/raspberrypi/clock/clockdrv.c | 27 +-
 bsps/arm/rtl22xx/clock/clockdrv.c |  2 +-
 bsps/arm/shared/clock/clock-a9mpcore.c| 28 ++
 bsps/arm/shared/clock/clock-nxp-lpc.c | 17 -
 bsps/arm/smdk2410/clock/clockdrv.c|  2 +-
 bsps/arm/tms570/clock/clock.c | 20 +-
 bsps/i386/pc386/clock/ckinit.c|  2 +-
 bsps/lm32/shared/clock/ckinit.c   |  2 +-
 bsps/lm32/shared/milkymist_clock/ckinit.c |  2 +-
 bsps/m68k/av5282/clock/clock.c|  2 +-
 bsps/m68k/gen68360/clock/clock.c  |  2 +-
 bsps/m68k/genmcf548x/clock/clock.c|  2 +-
 bsps/m68k/mcf52235/clock/clock.c  |  2 +-
 bsps/m68k/mcf5225x/clock/clock.c  |  2 +-
 bsps/m68k/mcf5235/clock/clock.c   |  2 +-
 bsps/m68k/mcf5329/clock/clock.c   |  2 +-
 bsps/m68k/mrm332/btimer/btimer.c  |  2 -
 bsps/m68k/uC5282/clock/clock.c|  2 +-
 bsps/microblaze/microblaze_fpga/clock/clock.c |  8 ++--
 bsps/mips/csb350/clock/clockdrv.c |  4 +-
 bsps/mips/rbtx4925/clock/clockdrv.c   |  2 +-
 bsps/mips/rbtx4938/clock/clockdrv.c   |  2 +-
 bsps/mips/shared/clock/clockdrv.c |  2 +-
 bsps/nios2/nios2_iss/clock/clock.c|  2 +-
 bsps/or1k/generic_or1k/clock/clockdrv.c   |  2 +-
 bsps/powerpc/mpc55xxevb/clock/clock-config.c  | 24 ++--
 bsps/powerpc/qoriq/clock/clock-config.c   | 14 +++
 bsps/riscv/griscv/clock/clockdrv.c|  2 +-
 bsps/riscv/riscv/clock/clockdrv.c | 13 +++
 bsps/shared/dev/clock/arm-generic-timer.c | 19 --
 bsps/shared/dev/clock/clockimpl.h | 37 +--
 bsps/shared/dev/clock/xil-ttc.c   | 32 ++--
 bsps/shared/grlib/btimer/tlib_ckinit.c|  4 +-
 bsps/sparc/erc32/clock/ckinit.c   |  8 ++--
 bsps/sparc/leon2/clock/ckinit.c   |  2 +-
 bsps/sparc/leon3/clock/ckinit.c   |  2 +-
 bsps/sparc64/shared/clock/ckinit.c|  2 +-
 42 files changed, 137 insertions(+), 178 deletions(-)

diff --git a/bsps/arm/beagle/clock/clock.c b/bsps/arm/beagle/clock/clock.c
index d42b051c98..a32dde86bf 100644
--- a/bsps/arm/beagle/clock/clock.c
+++ b/bsps/arm/beagle/clock/clock.c
@@ -290,7 +290,7 @@ static void 
beagle_clock_handler_install(rtems_interrupt_handler isr)
   clock_isr = isr;
 }
 
-#define Clock_driver_support_at_tick() beagle_clock_at_tick()
+#define Clock_driver_support_at_tick(arg) beagle_clock_at_tick()
 #define Clock_driver_support_initialize_hardware() beagle_clock_initialize()
 #define Clock_driver_support_install_isr(isr) \
   beagle_clock_handler_install(isr)
diff --git a/bsps/arm/csb336/clock/clockdrv.c b/bsps/arm/csb336/clock/clockdrv.c
index 58f98d87be..6af507a877 100644
--- a/bsps/arm/csb336/clock/clockdrv.c
+++ b/bsps/arm/csb336/clock/clockdrv.c
@@ -38,7 +38,7 @@ rtems_irq_connect_data clock_isr_data = {
  *- clear the interrupt bit?
  *- restart the timer?
  */
-#define Clock_driver_support_at_tick()   \
+#define Clock_driver_support_at_tick(arg)\
   do {   \
 uint32_t reg;\
  \
diff --git a/bsps/arm/csb337/clock/clock.c b/bsps/arm/csb337/clock/clock.c
index 69a3dafd81..ee05387baa 100644
--- a/bsps/arm/csb337/clock/clock.c
+++ b/bsps/arm/csb337/clock/clock.c
@@ -94,7 +94,7 @@ static void Clock_driver_support_initialize_hardware(void)
   ST_REG(ST_PIMR) = value;
 }
 
-#define Clock_driver_support_at_tick() \
+#define Clock_driver_support_at_tick(arg) \
   do { \
 uint32_t st_str; \
 \
diff --git a/bsps/arm/edb7312/clock/clockdrv.c 
b/bsps/arm/edb7312/clock/clockdrv.c
index 8c7cc4f26a..79289366da 100644
--- a/bsps/arm/edb7312/clock/clockdrv.c
+++ b/bsps/arm/edb7312/clock/clockdrv.c
@@ -18,9 +18,7 @@
   #define CLOCK_DRIVER_USE_FAST_IDLE 1
 #endif
 
-void Clock_isr(void * arg);
-
-#define Clock_driver_support_at_tick()\
+#define Clock_driver_support_at_tick(arg) \
   do {\
 *EP7312_TC1EOI = 0x;  \
   } while(0)
@@ -32,7 +30,7 @@ void Clock_isr(void 

[Docs] c-user: Clarify CONFIGURE_TICKS_PER_TIMESLICE

[Sebastian Huber]

Close #4986.
---
 c-user/config/general.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/c-user/config/general.rst b/c-user/config/general.rst
index 5ff79e7..61bfa1e 100644
--- a/c-user/config/general.rst
+++ b/c-user/config/general.rst
@@ -1017,7 +1017,7 @@ configured, see 
:ref:`CONFIGURE_APPLICATION_DOES_NOT_NEED_CLOCK_DRIVER`.
 
 The following constraints apply to this configuration option:
 
-* The value of the configuration option shall be greater than or equal to zero.
+* The value of the configuration option shall be greater than or equal to one.
 
 * The value of the configuration option shall be less than or equal to
   `UINT32_MAX `_.
-- 
2.35.3

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Re: [PATCH] Do not define CONFIGURE_TICKS_PER_TIMESLICE to 0

[Sebastian Huber]

On 20.03.24 15:14, Joel Sherrill wrote:
This is generally ok but it contradicts the documented behavior 
for CONFIGURE_TICKS_PER_TIMESLICE which states "The value of the 
configuration option shall be greater than or equal to zero."


This is the problem of the referenced ticket:

https://devel.rtems.org/ticket/4986



If zero is to be an error, then that needs to change.


This is what the patch does.



Further, this series of changes has made me realize that 
CONFIGURE_TICKS_PER_TIMESLICE and CONFIGURE_MICROSECONDS_PER_TICK should 
not be defined if the application has not defined 
CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER. Currently the documentation 
just says it has no effect.


This is a different topic. I would like to first fix the undefined 
behaviour if some uses:


#define CONFIGURE_TICKS_PER_TIMESLICE 0



Also the formatting of the text in the description is inconsistent. 
Could a ref be used for all of this?


The application shall define exactly one of the following configuration 
options


* :ref:`CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER`,
* ``CONFIGURE_APPLICATION_DOES_NOT_NEED_CLOCK_DRIVER``, or
* :ref:`CONFIGURE_APPLICATION_NEEDS_TIMER_DRIVER`,


Sorry, were is this in the patch?

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RFC: Add API to get and set interrupt priorities for interrupt vectors

[Sebastian Huber]

Hello,

I added a ticket for a proposal for an API to get and set interrupt 
priorities for interrupt vectors:


https://devel.rtems.org/ticket/5002

I would like to implement this API at least for the BSPs using the 
ARM/AArch64 GIC.


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[PATCH] Do not define CONFIGURE_TICKS_PER_TIMESLICE to 0

[Sebastian Huber]

Unconditionally make a CONFIGURE_TICKS_PER_TIMESLICE value less than or equal
to zero an error.

Update #4986.
---
 cpukit/doxygen/appl-config.h  | 2 +-
 cpukit/include/rtems/confdefs/clock.h | 3 +--
 testsuites/ada/tmtests/tm01/init.c| 1 -
 testsuites/ada/tmtests/tm02/init.c| 1 -
 testsuites/ada/tmtests/tm03/init.c| 1 -
 testsuites/ada/tmtests/tm04/init.c| 1 -
 testsuites/ada/tmtests/tm05/init.c| 1 -
 testsuites/ada/tmtests/tm06/init.c| 1 -
 testsuites/ada/tmtests/tm07/init.c| 1 -
 testsuites/ada/tmtests/tm08/init.c| 1 -
 testsuites/ada/tmtests/tm09/init.c| 1 -
 testsuites/ada/tmtests/tm10/init.c| 1 -
 testsuites/ada/tmtests/tm11/init.c| 1 -
 testsuites/ada/tmtests/tm12/init.c| 1 -
 testsuites/ada/tmtests/tm13/init.c| 1 -
 testsuites/ada/tmtests/tm14/init.c| 1 -
 testsuites/ada/tmtests/tm15/init.c| 1 -
 testsuites/ada/tmtests/tm16/init.c| 1 -
 testsuites/ada/tmtests/tm17/init.c| 1 -
 testsuites/ada/tmtests/tm18/init.c| 1 -
 testsuites/ada/tmtests/tm19/init.c| 1 -
 testsuites/ada/tmtests/tm20/init.c| 1 -
 testsuites/ada/tmtests/tm21/init.c| 1 -
 testsuites/ada/tmtests/tm22/init.c| 1 -
 testsuites/ada/tmtests/tm23/init.c| 1 -
 testsuites/ada/tmtests/tm24/init.c| 1 -
 testsuites/ada/tmtests/tm25/init.c| 1 -
 testsuites/ada/tmtests/tm28/init.c| 1 -
 testsuites/ada/tmtests/tm29/init.c| 1 -
 testsuites/ada/tmtests/tmck/init.c| 1 -
 testsuites/rhealstone/rhdeadlockbrk/deadlockbrk.c | 1 -
 testsuites/rhealstone/rhilatency/ilatency.c   | 1 -
 testsuites/rhealstone/rhmlatency/mlatency.c   | 1 -
 testsuites/rhealstone/rhtaskpreempt/taskpreempt.c | 1 -
 testsuites/rhealstone/rhtaskswitch/taskswitch.c   | 1 -
 testsuites/tmtests/tm01/system.h  | 1 -
 testsuites/tmtests/tm02/system.h  | 1 -
 testsuites/tmtests/tm03/system.h  | 1 -
 testsuites/tmtests/tm04/system.h  | 1 -
 testsuites/tmtests/tm05/system.h  | 1 -
 testsuites/tmtests/tm06/system.h  | 1 -
 testsuites/tmtests/tm07/system.h  | 1 -
 testsuites/tmtests/tm08/system.h  | 1 -
 testsuites/tmtests/tm09/system.h  | 1 -
 testsuites/tmtests/tm10/system.h  | 1 -
 testsuites/tmtests/tm11/system.h  | 1 -
 testsuites/tmtests/tm12/system.h  | 1 -
 testsuites/tmtests/tm13/system.h  | 1 -
 testsuites/tmtests/tm14/system.h  | 1 -
 testsuites/tmtests/tm15/system.h  | 1 -
 testsuites/tmtests/tm16/system.h  | 1 -
 testsuites/tmtests/tm17/system.h  | 1 -
 testsuites/tmtests/tm18/system.h  | 1 -
 testsuites/tmtests/tm19/system.h  | 1 -
 testsuites/tmtests/tm20/system.h  | 1 -
 testsuites/tmtests/tm21/system.h  | 1 -
 testsuites/tmtests/tm22/system.h  | 1 -
 testsuites/tmtests/tm23/system.h  | 1 -
 testsuites/tmtests/tm24/system.h  | 1 -
 testsuites/tmtests/tm25/system.h  | 1 -
 testsuites/tmtests/tm26/system.h  | 1 -
 testsuites/tmtests/tm27/system.h  | 1 -
 testsuites/tmtests/tm28/system.h  | 1 -
 testsuites/tmtests/tm29/system.h  | 1 -
 testsuites/tmtests/tmck/system.h  | 1 -
 65 files changed, 2 insertions(+), 66 deletions(-)

diff --git a/cpukit/doxygen/appl-config.h b/cpukit/doxygen/appl-config.h
index 77c89dabf3..81150af066 100644
--- a/cpukit/doxygen/appl-config.h
+++ b/cpukit/doxygen/appl-config.h
@@ -3685,7 +3685,7 @@
  * The following constraints apply to this configuration option:
  *
  * * The value of the configuration option shall be greater than or equal to
- *   zero.
+ *   one.
  *
  * * The value of the configuration option shall be less than or equal to https://en.cppreference.com/w/c/types/integer;>UINT32_MAX.
diff --git a/cpukit/include/rtems/confdefs/clock.h 
b/cpukit/include/rtems/confdefs/clock.h
index d35757561d..e57daa899b 100644
--- a/cpukit/include/rtems/confdefs/clock.h
+++ b/cpukit/include/rtems/confdefs/clock.h
@@ -70,8 +70,7 @@
   #warning "The clock ticks per second is not an integer"
 #endif
 
-#if defined(CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER) \
-  && defined(CONFIGURE_TICKS_PER_TIMESLICE) \
+#if defined(CONFIGURE_TICKS_PER_TIMESLICE) \
   && CONFIGURE_TICKS_PER_TIMESLICE <= 0
   #error "CONFIGURE_TICKS_PER_TIMESLICE shall be greater than zero"
 #endif
diff --git 

Re: [PATCH 1/5] bsps: Use bsps/aarch64/xilinx-zynqmp

[Sebastian Huber]

On 19.03.24 18:34, Chris Johns wrote:

I will build the BSPs for each commit today.

Thanks. The reason I raised this is GitLab can squash merges to `main` and the
reason is always being able to bisect `main` so it is an issue being considered.
This patch set made me wonder what we do now?


I would definitely not squash commits when they are merged. This would 
make the history more difficult to review and would also complicate 
things if a specific commit breaks something. The more commits you have 
the easier it is to single out the trouble maker.


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[PATCH] dev/irq: Optional arm_gic_irq_processor_count()

[Sebastian Huber]

Provide arm_gic_irq_processor_count() only in SMP configurations.
---
 bsps/include/dev/irq/arm-gic-irq.h | 2 ++
 bsps/shared/dev/irq/arm-gicv2.c| 2 ++
 bsps/shared/dev/irq/arm-gicv3.c| 2 ++
 3 files changed, 6 insertions(+)

diff --git a/bsps/include/dev/irq/arm-gic-irq.h 
b/bsps/include/dev/irq/arm-gic-irq.h
index 3c875917df..b3487176f6 100644
--- a/bsps/include/dev/irq/arm-gic-irq.h
+++ b/bsps/include/dev/irq/arm-gic-irq.h
@@ -113,9 +113,11 @@ static inline rtems_status_code 
arm_gic_irq_generate_software_irq(
   return sc;
 }
 
+#ifdef RTEMS_SMP
 uint32_t arm_gic_irq_processor_count(void);
 
 void arm_gic_irq_initialize_secondary_cpu(void);
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c
index 49d6e60634..e0abf4c96d 100644
--- a/bsps/shared/dev/irq/arm-gicv2.c
+++ b/bsps/shared/dev/irq/arm-gicv2.c
@@ -402,9 +402,11 @@ void arm_gic_trigger_sgi(rtems_vector_number vector, 
uint32_t targets)
 | GIC_DIST_ICDSGIR_SGIINTID(vector);
 }
 
+#ifdef RTEMS_SMP
 uint32_t arm_gic_irq_processor_count(void)
 {
   volatile gic_dist *dist = ARM_GIC_DIST;
 
   return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1;
 }
+#endif
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index 4772ff5db4..108d64348a 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -280,6 +280,7 @@ void arm_gic_trigger_sgi(rtems_vector_number vector, 
uint32_t targets)
   gicv3_trigger_sgi(vector, targets);
 }
 
+#ifdef RTEMS_SMP
 uint32_t arm_gic_irq_processor_count(void)
 {
   volatile gic_dist *dist = ARM_GIC_DIST;
@@ -306,3 +307,4 @@ uint32_t arm_gic_irq_processor_count(void)
 
   return cpu_count;
 }
+#endif
-- 
2.35.3

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Re: [PATCH v2] bsps: Add BSP_FLUSH_KERNEL_CHAR_OUTPUT BSP option

[Sebastian Huber]

On 19.03.24 14:50, Kinsey Moore wrote:
The xilinx-zynqmp-rpu bsp_reset() is modified, but not included in the 
spec file for the new option. Its family differs from the 
arm/xilinx-zynqmp BSP family with a -rpu suffix.


Yes, but this BSP is quite new. I would prefer to let it not flush 
anything by default to carry out a reset.


I'd be fine with this 
being enabled for the AArch64 BSPs as well, but I imagine that's better 
as a separate patch.


Why should it be enabled by default? The arm/xilinx-zynq and 
arm/xilinx-zynqmp BSPs were the only ones doing an UART flush in the 
general termination procedure. It probably was done to address a 
specific use case (maybe test runs).


I don't really like the new bsp_flush_kernel_char_output() function. 
Another approach could be an API change of


/**
 * @ingroup RTEMSAPIKernelCharIO
 *
 * @brief Polled character output functions shall have this type.
 */
typedef void ( *BSP_output_char_function_type )( char );

to something like this

typedef int ( *BSP_output_char_function_type )( int action );

If action in {0, ..., 255}, then print out the character. If 0x100 is 
set, then flush the output device. If 0x200 is set, then do Y... The 
return value could be used to give a status indication.


This could then be use for example by test runs, to flush the test 
output after the end of the test.


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Re: bsps: xilinx-zynqmp-rpu: fix the integer truncation in Triple Timer Counter clock driver

[Sebastian Huber]

Hello Stanislav,

that is a nice coincidence. I started to work with this BSP last week 
and I also fixed this issue, but I had some other patches in the queue. 
I reworked this driver a bit. I will check in your patch first.


On 19.03.24 10:54, Stanislav Pankevich wrote:

Dear RTEMS developers,

Here is a follow-up patch to our previous work on the Zynq US+ RPU BSP.

In fact, we had fixed this issue a few months ago but didn't find a good 
time to upstream it since then.


P.S. It is great to see that the migration to GitLab is happening.

Thanks,
Stanislav

---

Author: Stanislav Pankevich 
Date:   Tue Mar 19 10:34:57 2024 +0100

     bsps: xilinx-zynqmp-rpu: fix the integer truncation in Triple Timer 
Counter clock driver
     We observed a strange behavior of the 1Hz timer when running cFS on 
Zynq RPU. After some investigation, we reduced the error to the 
truncation issue. This patch fixes the issue.


diff --git a/bsps/shared/dev/clock/xil-ttc.c 
b/bsps/shared/dev/clock/xil-ttc.c

index 2c47684045..5121773a6f 100644
--- a/bsps/shared/dev/clock/xil-ttc.c
+++ b/bsps/shared/dev/clock/xil-ttc.c
@@ -126,7 +126,7 @@ static void 
zynqmp_ttc_clock_driver_support_initialize_hardware(void)

    /* Setup match register to generate tick IRQ */
    ttc_clock_instance.irq_match_interval =
-    (uint32_t) ((frequency * microsec_per_tick) / 100);
+    (uint32_t) (((uint64_t)frequency * microsec_per_tick) / 100);
    XTtcPs_WriteReg(BSP_SELECTED_TTC_ADDR, XTTCPS_MATCH_0_OFFSET,
                    ttc_clock_instance.irq_match_interval);
    /* Clear interupts (clear on read) */


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[PATCH v2] bsps: Add BSP_FLUSH_KERNEL_CHAR_OUTPUT BSP option

[Sebastian Huber]

Make the kernel I/O output character device flushing configurable.  The
bsp_reset() function should reset the unit and do nothing else.

The arm/xilinx-zynq and arm/xilinx-zynqmp BSPs were the only ones doing an UART
flush in bsp_reset().  The bsp_reset() function should reset the system and do
nothing more.  Doing additional things like flushing an UART device may not
make sense for all applications.  Some applications may not use the UART
device, so it may not be initialized and powered off.  Some applications may
use it with an application-specific protocol which doesn't like the additional
four '\r' during reset.  Doing a UART flush takes some time and some
applications may prefer a fast reset cycle.  The bsp_reset() is the wrong place
to do specific cleanup functions.

Flushing the kernel I/O output character device is now optionally done in
bsp_fatal_extension() depending on the new BSP option
BSP_FLUSH_KERNEL_CHAR_OUTPUT.
---
 bsps/aarch64/xilinx-zynqmp/console/console.c  |  3 ++-
 bsps/aarch64/xilinx-zynqmp/include/bsp.h  |  2 --
 bsps/arm/xilinx-zynq/console/debug-console.c  | 10 +
 bsps/arm/xilinx-zynq/start/bspreset.c |  4 
 .../console/console-config.c  |  3 ++-
 bsps/arm/xilinx-zynqmp-rpu/include/bsp.h  |  2 --
 bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c   |  3 ---
 .../xilinx-zynqmp/console/console-config.c|  2 +-
 bsps/arm/xilinx-zynqmp/include/bsp.h  |  2 --
 bsps/arm/xilinx-zynqmp/start/bspreset.c   |  4 +---
 bsps/include/bsp/bootcard.h   |  5 +
 bsps/shared/start/bspfatal-default.c  |  4 
 spec/build/bsps/bspopts.yml   |  2 ++
 spec/build/bsps/optflushkerncharout.yml   | 22 +++
 14 files changed, 49 insertions(+), 19 deletions(-)
 create mode 100644 spec/build/bsps/optflushkerncharout.yml

diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c 
b/bsps/aarch64/xilinx-zynqmp/console/console.c
index 9ce0b1da63..d1b2850952 100644
--- a/bsps/aarch64/xilinx-zynqmp/console/console.c
+++ b/bsps/aarch64/xilinx-zynqmp/console/console.c
@@ -41,6 +41,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 
@@ -234,7 +235,7 @@ rtems_status_code console_initialize(
   return RTEMS_SUCCESSFUL;
 }
 
-void zynqmp_debug_console_flush(void)
+void bsp_flush_kernel_char_output(void)
 {
   zynq_uart_reset_tx_flush(_uart_instances[BSP_CONSOLE_MINOR]);
 }
diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp.h 
b/bsps/aarch64/xilinx-zynqmp/include/bsp.h
index 0ccca8b196..d36abde415 100644
--- a/bsps/aarch64/xilinx-zynqmp/include/bsp.h
+++ b/bsps/aarch64/xilinx-zynqmp/include/bsp.h
@@ -86,8 +86,6 @@ BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
  */
 BSP_START_TEXT_SECTION void zynqmp_setup_secondary_cpu_mmu_and_cache( void );
 
-void zynqmp_debug_console_flush(void);
-
 uint32_t zynqmp_clock_i2c0(void);
 
 uint32_t zynqmp_clock_i2c1(void);
diff --git a/bsps/arm/xilinx-zynq/console/debug-console.c 
b/bsps/arm/xilinx-zynq/console/debug-console.c
index d398ca7988..67fcbdf4a1 100644
--- a/bsps/arm/xilinx-zynq/console/debug-console.c
+++ b/bsps/arm/xilinx-zynq/console/debug-console.c
@@ -38,10 +38,20 @@
 #include 
 
 #include 
+#include 
 #include 
+#include 
 
 #include 
 
+void bsp_flush_kernel_char_output(void)
+{
+  rtems_termios_device_context *base =
+_uart_instances[BSP_CONSOLE_MINOR].base;
+
+  zynq_uart_reset_tx_flush(base);
+}
+
 static void zynq_debug_console_out(char c)
 {
   rtems_termios_device_context *base =
diff --git a/bsps/arm/xilinx-zynq/start/bspreset.c 
b/bsps/arm/xilinx-zynq/start/bspreset.c
index f8cc3b6999..fcdb1b8ded 100644
--- a/bsps/arm/xilinx-zynq/start/bspreset.c
+++ b/bsps/arm/xilinx-zynq/start/bspreset.c
@@ -33,17 +33,13 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include 
 #include 
-#include 
 
 void bsp_reset(void)
 {
   volatile uint32_t *slcr_unlock = (volatile uint32_t *) 0xf808;
   volatile uint32_t *pss_rst_ctrl = (volatile uint32_t *) 0xf8000200;
 
-  zynq_uart_reset_tx_flush(_uart_instances[BSP_CONSOLE_MINOR]);
-
   while (true) {
 *slcr_unlock = 0xdf0d;
 *pss_rst_ctrl = 0x1;
diff --git a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c 
b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
index f52e008f2b..196b2dec58 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
@@ -35,6 +35,7 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
 
@@ -79,7 +80,7 @@ rtems_status_code console_initialize(
   return RTEMS_SUCCESSFUL;
 }
 
-void zynqmp_debug_console_flush(void)
+void bsp_flush_kernel_char_output(void)
 {
   zynq_uart_reset_tx_flush(_uart_instances[BSP_CONSOLE_MINOR]);
 }
diff --git a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h 
b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
index e386bd4b26..060147967c 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
+++ b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
@@ -83,8 +83,6 @@ extern "C" {
 

Re: [PATCH 1/5] bsps: Use bsps/aarch64/xilinx-zynqmp

[Sebastian Huber]

On 19.03.24 03:21, Chris Johns wrote:

Does this patch series build at the per commit level?


I used

./waf bspdefaults > a.txt
apply patch
./waf bspdefaults > b.txt
diff a.txt b.txt

to check that the defaults don't change. I will build the BSPs for each 
commit today.


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Re: [PATCH] improved error checking in ticks per timeslice

[Sebastian Huber]

On 18.03.24 21:31, Kinsey Moore wrote:
Sorry, I didn't realize I had tests turned off in my local build when I 
checked this. The test is now gated behind NEEDS_CLOCK_DRIVER as well.


This is fine for fixing the build, but I would rather fix the tests. 
Applications may have there own clock driver for example.


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Re: [PATCH 3/5] xilinx-zynqmp-rpu: Remove URLs from copyrights

[Sebastian Huber]

On 19.03.24 03:20, Chris Johns wrote:

On 19/3/2024 3:30 am, Sebastian Huber wrote:

---
  spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml| 2 +-
  spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml  | 2 +-
  spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml   | 2 +-
  spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml | 2 +-
  4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml 
b/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml
index ba70c44d7d..06795eb416 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml
@@ -5,7 +5,7 @@ actions:
  - env-append: null
  build-type: option
  copyrights:
-- Copyright (C) 2023 Reflex Aerospace GmbH (https://www.reflexaerospace.com/  )
+- Copyright (C) 2023 Reflex Aerospace GmbH

Why this change?


When I updated our company name to embedded brains GmbH & Co. KG, I 
removed the URLs from our copyright statements since we were basically 
the only ones doing this. If you don't have an issue with the URLs, then 
I will discuss internally if we would like to add them again to our 
copyright statements.


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Re: [PATCH] bsps: Add BSP_FLUSH_KERNEL_CHAR_OUTPUT option

[Sebastian Huber]

On 19.03.24 03:16, Chris Johns wrote:

On 19/3/2024 3:49 am, Sebastian Huber wrote:

Make the kernel I/O output character device flushing configurable.  The
bsp_reset() function should reset the unit and do nothing else.
---
  bsps/aarch64/xilinx-zynqmp/console/console.c  |  3 ++-
  bsps/aarch64/xilinx-zynqmp/include/bsp.h  |  2 --
  .../console/console-config.c  |  3 ++-
  bsps/arm/xilinx-zynqmp-rpu/include/bsp.h  |  2 --
  bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c   |  3 ---
  .../xilinx-zynqmp/console/console-config.c|  2 +-
  bsps/arm/xilinx-zynqmp/include/bsp.h  |  2 --
  bsps/arm/xilinx-zynqmp/start/bspreset.c   |  4 +---
  bsps/include/bsp/bootcard.h   |  5 +
  bsps/shared/start/bspfatal-default.c  |  4 
  spec/build/bsps/bspopts.yml   |  2 ++
  spec/build/bsps/optflushkerncharout.yml   | 20 +++
  12 files changed, 37 insertions(+), 15 deletions(-)
  create mode 100644 spec/build/bsps/optflushkerncharout.yml

diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c 
b/bsps/aarch64/xilinx-zynqmp/console/console.c
index 9ce0b1da63..d1b2850952 100644
--- a/bsps/aarch64/xilinx-zynqmp/console/console.c
+++ b/bsps/aarch64/xilinx-zynqmp/console/console.c
@@ -41,6 +41,7 @@
  #include 
  
  #include 

+#include 
  #include 
  #include 
  
@@ -234,7 +235,7 @@ rtems_status_code console_initialize(

return RTEMS_SUCCESSFUL;
  }
  
-void zynqmp_debug_console_flush(void)

+void bsp_flush_kernel_char_output(void)
  {
zynq_uart_reset_tx_flush(_uart_instances[BSP_CONSOLE_MINOR]);
  }
diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp.h 
b/bsps/aarch64/xilinx-zynqmp/include/bsp.h
index 0ccca8b196..d36abde415 100644
--- a/bsps/aarch64/xilinx-zynqmp/include/bsp.h
+++ b/bsps/aarch64/xilinx-zynqmp/include/bsp.h
@@ -86,8 +86,6 @@ BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
   */
  BSP_START_TEXT_SECTION void zynqmp_setup_secondary_cpu_mmu_and_cache( void );
  
-void zynqmp_debug_console_flush(void);

-
  uint32_t zynqmp_clock_i2c0(void);
  
  uint32_t zynqmp_clock_i2c1(void);

diff --git a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c 
b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
index f52e008f2b..196b2dec58 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
@@ -35,6 +35,7 @@
  #include 
  #include 
  
+#include 

  #include 
  #include 
  
@@ -79,7 +80,7 @@ rtems_status_code console_initialize(

return RTEMS_SUCCESSFUL;
  }
  
-void zynqmp_debug_console_flush(void)

+void bsp_flush_kernel_char_output(void)
  {
zynq_uart_reset_tx_flush(_uart_instances[BSP_CONSOLE_MINOR]);
  }
diff --git a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h 
b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
index e386bd4b26..060147967c 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
+++ b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
@@ -83,8 +83,6 @@ extern "C" {
   */
  BSP_START_TEXT_SECTION void zynqmp_setup_mpu_and_cache(void);
  
-void zynqmp_debug_console_flush(void);

-
  #ifdef __cplusplus
  }
  #endif /* __cplusplus */
diff --git a/bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c 
b/bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c
index eecb4da838..a894f55f6e 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c
+++ b/bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c
@@ -30,13 +30,10 @@
   * POSSIBILITY OF SUCH DAMAGE.
   */
  
-#include 

  #include 
  
  void bsp_reset(void)

  {
-  zynqmp_debug_console_flush();


Why remove the call here?


-
while (true) {
  /* Wait */
}


This BSP is rather new. Flushing the UART followed by an infinite loop 
doesn't really make sense. I did a full test run for this BSP and there 
are some more things to fix.



diff --git a/bsps/arm/xilinx-zynqmp/console/console-config.c 
b/bsps/arm/xilinx-zynqmp/console/console-config.c
index eadd7f11a2..360d193ba2 100644
--- a/bsps/arm/xilinx-zynqmp/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp/console/console-config.c
@@ -81,7 +81,7 @@ rtems_status_code console_initialize(
return RTEMS_SUCCESSFUL;
  }
  
-void zynqmp_debug_console_flush(void)

+void bsp_flush_kernel_char_output(void)
  {
zynq_uart_reset_tx_flush(_uart_instances[BSP_CONSOLE_MINOR]);
  }
diff --git a/bsps/arm/xilinx-zynqmp/include/bsp.h 
b/bsps/arm/xilinx-zynqmp/include/bsp.h
index a08a5feee9..2785e4c2e0 100644
--- a/bsps/arm/xilinx-zynqmp/include/bsp.h
+++ b/bsps/arm/xilinx-zynqmp/include/bsp.h
@@ -79,8 +79,6 @@ extern "C" {
   */
  BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
  
-void zynqmp_debug_console_flush(void);

-
  #ifdef __cplusplus
  }
  #endif /* __cplusplus */
diff --git a/bsps/arm/xilinx-zynqmp/start/bspreset.c 
b/bsps/arm/xilinx-zynqmp/start/bspreset.c
index b43b19b05f..ed2f4da83a 100644
--- a/bsps/arm/xilinx-zynqmp/start/bspreset.c
+++ b/bsps/arm/xilinx-zynqmp/start/bspreset.c
@@ -30,12 +30,10 @@
   * POSSIB

[PATCH] bsps: Add BSP_FLUSH_KERNEL_CHAR_OUTPUT option

[Sebastian Huber]

Make the kernel I/O output character device flushing configurable.  The
bsp_reset() function should reset the unit and do nothing else.
---
 bsps/aarch64/xilinx-zynqmp/console/console.c  |  3 ++-
 bsps/aarch64/xilinx-zynqmp/include/bsp.h  |  2 --
 .../console/console-config.c  |  3 ++-
 bsps/arm/xilinx-zynqmp-rpu/include/bsp.h  |  2 --
 bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c   |  3 ---
 .../xilinx-zynqmp/console/console-config.c|  2 +-
 bsps/arm/xilinx-zynqmp/include/bsp.h  |  2 --
 bsps/arm/xilinx-zynqmp/start/bspreset.c   |  4 +---
 bsps/include/bsp/bootcard.h   |  5 +
 bsps/shared/start/bspfatal-default.c  |  4 
 spec/build/bsps/bspopts.yml   |  2 ++
 spec/build/bsps/optflushkerncharout.yml   | 20 +++
 12 files changed, 37 insertions(+), 15 deletions(-)
 create mode 100644 spec/build/bsps/optflushkerncharout.yml

diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c 
b/bsps/aarch64/xilinx-zynqmp/console/console.c
index 9ce0b1da63..d1b2850952 100644
--- a/bsps/aarch64/xilinx-zynqmp/console/console.c
+++ b/bsps/aarch64/xilinx-zynqmp/console/console.c
@@ -41,6 +41,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 
@@ -234,7 +235,7 @@ rtems_status_code console_initialize(
   return RTEMS_SUCCESSFUL;
 }
 
-void zynqmp_debug_console_flush(void)
+void bsp_flush_kernel_char_output(void)
 {
   zynq_uart_reset_tx_flush(_uart_instances[BSP_CONSOLE_MINOR]);
 }
diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp.h 
b/bsps/aarch64/xilinx-zynqmp/include/bsp.h
index 0ccca8b196..d36abde415 100644
--- a/bsps/aarch64/xilinx-zynqmp/include/bsp.h
+++ b/bsps/aarch64/xilinx-zynqmp/include/bsp.h
@@ -86,8 +86,6 @@ BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
  */
 BSP_START_TEXT_SECTION void zynqmp_setup_secondary_cpu_mmu_and_cache( void );
 
-void zynqmp_debug_console_flush(void);
-
 uint32_t zynqmp_clock_i2c0(void);
 
 uint32_t zynqmp_clock_i2c1(void);
diff --git a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c 
b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
index f52e008f2b..196b2dec58 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
@@ -35,6 +35,7 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
 
@@ -79,7 +80,7 @@ rtems_status_code console_initialize(
   return RTEMS_SUCCESSFUL;
 }
 
-void zynqmp_debug_console_flush(void)
+void bsp_flush_kernel_char_output(void)
 {
   zynq_uart_reset_tx_flush(_uart_instances[BSP_CONSOLE_MINOR]);
 }
diff --git a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h 
b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
index e386bd4b26..060147967c 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
+++ b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
@@ -83,8 +83,6 @@ extern "C" {
  */
 BSP_START_TEXT_SECTION void zynqmp_setup_mpu_and_cache(void);
 
-void zynqmp_debug_console_flush(void);
-
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
diff --git a/bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c 
b/bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c
index eecb4da838..a894f55f6e 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c
+++ b/bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c
@@ -30,13 +30,10 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include 
 #include 
 
 void bsp_reset(void)
 {
-  zynqmp_debug_console_flush();
-
   while (true) {
 /* Wait */
   }
diff --git a/bsps/arm/xilinx-zynqmp/console/console-config.c 
b/bsps/arm/xilinx-zynqmp/console/console-config.c
index eadd7f11a2..360d193ba2 100644
--- a/bsps/arm/xilinx-zynqmp/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp/console/console-config.c
@@ -81,7 +81,7 @@ rtems_status_code console_initialize(
   return RTEMS_SUCCESSFUL;
 }
 
-void zynqmp_debug_console_flush(void)
+void bsp_flush_kernel_char_output(void)
 {
   zynq_uart_reset_tx_flush(_uart_instances[BSP_CONSOLE_MINOR]);
 }
diff --git a/bsps/arm/xilinx-zynqmp/include/bsp.h 
b/bsps/arm/xilinx-zynqmp/include/bsp.h
index a08a5feee9..2785e4c2e0 100644
--- a/bsps/arm/xilinx-zynqmp/include/bsp.h
+++ b/bsps/arm/xilinx-zynqmp/include/bsp.h
@@ -79,8 +79,6 @@ extern "C" {
  */
 BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
 
-void zynqmp_debug_console_flush(void);
-
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
diff --git a/bsps/arm/xilinx-zynqmp/start/bspreset.c 
b/bsps/arm/xilinx-zynqmp/start/bspreset.c
index b43b19b05f..ed2f4da83a 100644
--- a/bsps/arm/xilinx-zynqmp/start/bspreset.c
+++ b/bsps/arm/xilinx-zynqmp/start/bspreset.c
@@ -30,12 +30,10 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include 
+#include 
 
 void bsp_reset(void)
 {
-  zynqmp_debug_console_flush();
-
   while (true) {
 /* Wait */
   }
diff --git a/bsps/include/bsp/bootcard.h b/bsps/include/bsp/bootcard.h
index 5f339d65f8..dfdc3ae7e0 100644
--- a/bsps/include/bsp/bootcard.h
+++ b/bsps/include/bsp/bootcard.h
@@ -94,6 +94,11 @@ struct Per_CPU_Control;
  */
 void 

[PATCH] arm: Move _CPU_ISR_install_vector()

[Sebastian Huber]

The use of this function is optional. Newer BSPs do not use it.
---
 .../score/cpu/arm/armv4-isr-install-vector.c  | 75 +++
 cpukit/score/cpu/arm/cpu.c| 28 +--
 spec/build/cpukit/cpuarm.yml  |  1 +
 3 files changed, 77 insertions(+), 27 deletions(-)
 create mode 100644 cpukit/score/cpu/arm/armv4-isr-install-vector.c

diff --git a/cpukit/score/cpu/arm/armv4-isr-install-vector.c 
b/cpukit/score/cpu/arm/armv4-isr-install-vector.c
new file mode 100644
index 00..739b02f8bf
--- /dev/null
+++ b/cpukit/score/cpu/arm/armv4-isr-install-vector.c
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the ARM-specific _CPU_ISR_install_vector().
+ */
+
+/*
+ *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
+ *  Emmanuel Raguet, mailto:rag...@crf.canon.fr
+ *
+ *  Copyright (c) 2002 Advent Networks, Inc
+ *  Jay Monkman 
+ *
+ *  Copyright (C) 2009, 2017 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+
+#ifdef ARM_MULTILIB_ARCH_V4
+
+void _CPU_ISR_install_vector(
+  uint32_t vector,
+  CPU_ISR_handler  new_handler,
+  CPU_ISR_handler *old_handler
+)
+{
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Warray-bounds"
+  /* Redirection table starts at the end of the vector table */
+  CPU_ISR_handler volatile  *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4);
+
+  CPU_ISR_handler current_handler = table [vector];
+
+  /* The current handler is now the old one */
+  if (old_handler != NULL) {
+*old_handler = current_handler;
+  }
+
+  /* Write only if necessary to avoid writes to a maybe read-only memory */
+  if (current_handler != new_handler) {
+table [vector] = new_handler;
+  }
+#pragma GCC diagnostic pop
+}
+
+#endif /* ARM_MULTILIB_ARCH_V4 */
diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c
index 65f1ad2014..c27f4de9f9 100644
--- a/cpukit/score/cpu/arm/cpu.c
+++ b/cpukit/score/cpu/arm/cpu.c
@@ -8,8 +8,7 @@
  * @brief This source file contains static assertions to ensure the consistency
  *   of interfaces used in C and assembler and it contains the ARM-specific
  *   implementation of _CPU_Initialize(), _CPU_ISR_Get_level(),
- *   _CPU_ISR_Set_level(), _CPU_ISR_install_vector(),
- *   _CPU_Context_Initialize(), and _CPU_Fatal_halt().
+ *   _CPU_ISR_Set_level(), _CPU_Context_Initialize(), and _CPU_Fatal_halt().
  */
 
 /*
@@ -160,31 +159,6 @@ uint32_t _CPU_ISR_Get_level( void )
   return ( level & ARM_PSR_I ) != 0;
 }
 
-void _CPU_ISR_install_vector(
-  uint32_t vector,
-  CPU_ISR_handler  new_handler,
-  CPU_ISR_handler *old_handler
-)
-{
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Warray-bounds"
-  /* Redirection table starts at the end of the vector table */
-  CPU_ISR_handler volatile  *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4);
-
-  CPU_ISR_handler current_handler = table [vector];
-
-  /* The current handler is now the old one */
-  if (old_handler != NULL) {
-*old_handler = current_handler;
-  }
-
-  /* Write only if necessary to avoid writes to a maybe read-only memory */
-  if (current_handler != new_handler) {
-table [vector] = new_handler;
-  }
-#pragma GCC diagnostic pop
-}
-
 void _CPU_Initialize( void )
 {
   /* Do nothing */
diff --git a/spec/build/cpukit/cpuarm.yml b/spec/build/cpukit/cpuarm.yml
index 5b140e46bb..88f84fd361 100644
--- a/spec/build/cpukit/cpuarm.yml
+++ b/spec/build/cpukit/cpuarm.yml
@@ -41,6 +41,7 @@ source:
 - cpukit/score/cpu/arm/arm_exc_interrupt.S
 - 

[PATCH 4/5] bsps: Add xilinx_zynq_rpu BSP variant

[Sebastian Huber]

Add a BSP variant without a board-specific name.
---
 .../arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml   | 87 +--
 .../bsps/arm/xilinx-zynqmp-rpu/bsprpu.yml | 17 
 spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml | 69 +++
 spec/build/bsps/arm/xilinx-zynqmp-rpu/obj.yml | 42 +
 4 files changed, 132 insertions(+), 83 deletions(-)
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/bsprpu.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/obj.yml

diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml 
b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
index 3fa210d8e7..f6c228c79d 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
@@ -8,89 +8,10 @@ copyrights:
 cppflags: []
 enabled-by: true
 family: xilinx-zynqmp-rpu
-includes:
-- bsps/include/xil/
-- bsps/include/xil/${XIL_SUPPORT_PATH}/
-install:
-- destination: ${BSP_INCLUDEDIR}
-  source:
-  - bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
-- destination: ${BSP_INCLUDEDIR}/bsp
-  source:
-  - bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h
-- destination: ${BSP_INCLUDEDIR}/peripheral_maps
-  source:
-  - bsps/include/peripheral_maps/xilinx_zynqmp.h
+includes: []
+install: []
 links:
 - role: build-dependency
-  uid: ../grp
-- role: build-dependency
-  uid: ../start
-- role: build-dependency
-  uid: abi
-- role: build-dependency
-  uid: optclkfastidle
-- role: build-dependency
-  uid: optclkuart
-- role: build-dependency
-  uid: optconirq
-- role: build-dependency
-  uid: ../../optconminor
-- role: build-dependency
-  uid: optint0len
-- role: build-dependency
-  uid: optint0ori
-- role: build-dependency
-  uid: optint1len
-- role: build-dependency
-  uid: optint1ori
-- role: build-dependency
-  uid: optramlen
-- role: build-dependency
-  uid: optramori
-- role: build-dependency
-  uid: optresetvec
-- role: build-dependency
-  uid: optnocachelen
-- role: build-dependency
-  uid: ../../obj
-- role: build-dependency
-  uid: ../../objirq
-- role: build-dependency
-  uid: ../../objdevserialzynq
-- role: build-dependency
-  uid: ../../objdevspizynq
-- role: build-dependency
-  uid: ../../objdevspixil
-- role: build-dependency
-  uid: ../../objmem
-- role: build-dependency
-  uid: ../../opto0
-- role: build-dependency
-  uid: linkcmds
-- role: build-dependency
-  uid: ../../bspopts
-- role: build-dependency
-  uid: ../../objxilinxsupport
-source:
-- bsps/shared/cache/nocache.c
-- bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
-- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
-- bsps/arm/shared/start/bsp-start-memcpy.S
-- bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
-- bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c
-- bsps/arm/xilinx-zynqmp-rpu/start/bspstart.c
-- bsps/arm/xilinx-zynqmp-rpu/start/bspstarthooks.c
-- bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
-- bsps/shared/dev/clock/xil-ttc.c
-- bsps/shared/dev/btimer/btimer-cpucounter.c
-- bsps/shared/dev/getentropy/getentropy-cpucounter.c
-- bsps/shared/dev/irq/arm-gicv2.c
-- bsps/shared/dev/irq/arm-gicv2-zynqmp.c
-- bsps/shared/dev/serial/console-termios.c
-- bsps/shared/irq/irq-default-handler.c
-- bsps/shared/start/bspfatal-default.c
-- bsps/shared/start/gettargethash-default.c
-- bsps/shared/start/sbrk.c
-- bsps/shared/start/stackalloc.c
+  uid: grp
+source: []
 type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bsprpu.yml 
b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bsprpu.yml
new file mode 100644
index 00..d4073d8248
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bsprpu.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: xilinx_zynqmp_rpu
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH
+cppflags: []
+enabled-by: true
+family: xilinx-zynqmp-rpu
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+source: []
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml 
b/spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml
new file mode 100644
index 00..b886948d47
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml
@@ -0,0 +1,69 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: group
+cflags: []
+copyrights:
+- Copyright (C) 2023 Reflex Aerospace GmbH
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes:
+- bsps/include/xil
+- bsps/include/xil/${XIL_SUPPORT_PATH}
+install: []
+ldflags: []
+links:
+- role: build-dependency
+  uid: ../grp
+- role: build-dependency
+  uid: ../start
+- role: build-dependency
+  uid: abi
+- role: build-dependency
+  uid: optclkfastidle
+- role: build-dependency
+  uid: optclkuart
+- role: build-dependency
+  uid: optconirq
+- role: build-dependency
+  uid: ../../optconminor
+- role: build-dependency
+  uid: optint0len
+- role: build-dependency
+  uid: optint0ori
+- role: 

[PATCH 1/5] bsps: Use bsps/aarch64/xilinx-zynqmp

[Sebastian Huber]

---
 spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml| 6 +-
 spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml | 6 +-
 spec/build/cpukit/optsmp.yml  | 6 +-
 3 files changed, 3 insertions(+), 15 deletions(-)

diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml 
b/spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml
index 5338538de0..44d2671eb6 100644
--- a/spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml
@@ -15,11 +15,7 @@ default:
   - aarch64/xilinx_versal_aiedge
   - aarch64/xilinx_versal_qemu
   - aarch64/xilinx_versal_vck190
-  - aarch64/xilinx_zynqmp_ilp32_qemu
-  - aarch64/xilinx_zynqmp_ilp32_zu3eg
-  - aarch64/xilinx_zynqmp_lp64_cfc400x
-  - aarch64/xilinx_zynqmp_lp64_qemu
-  - aarch64/xilinx_zynqmp_lp64_zu3eg
+  - bsps/aarch64/xilinx-zynqmp
   value: null
 - enabled-by: true
   value: 0x0002
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml 
b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml
index fbc2dd9227..9b552c3f96 100644
--- a/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml
@@ -15,11 +15,7 @@ default:
   - aarch64/xilinx_versal_aiedge
   - aarch64/xilinx_versal_qemu
   - aarch64/xilinx_versal_vck190
-  - aarch64/xilinx_zynqmp_ilp32_qemu
-  - aarch64/xilinx_zynqmp_ilp32_zu3eg
-  - aarch64/xilinx_zynqmp_lp64_cfc400x
-  - aarch64/xilinx_zynqmp_lp64_qemu
-  - aarch64/xilinx_zynqmp_lp64_zu3eg
+  - bsps/aarch64/xilinx-zynqmp
   value: null
 - enabled-by: true
   value: 0x0001
diff --git a/spec/build/cpukit/optsmp.yml b/spec/build/cpukit/optsmp.yml
index 45d41299da..f78558d6eb 100644
--- a/spec/build/cpukit/optsmp.yml
+++ b/spec/build/cpukit/optsmp.yml
@@ -13,11 +13,6 @@ default:
 description: |
   Enable the Symmetric Multiprocessing (SMP) support
 enabled-by:
-- aarch64/xilinx_zynqmp_ilp32_qemu
-- aarch64/xilinx_zynqmp_ilp32_zu3eg
-- aarch64/xilinx_zynqmp_lp64_cfc400x
-- aarch64/xilinx_zynqmp_lp64_qemu
-- aarch64/xilinx_zynqmp_lp64_zu3eg
 - arm/altcycv_devkit
 - arm/fvp_cortex_r52
 - arm/imx7
@@ -33,6 +28,7 @@ enabled-by:
 - arm/xilinx_zynq_picozed
 - arm/xilinx_zynq_pynq
 - arm/xilinx_zynq_microzed
+- bsps/aarch64/xilinx-zynqmp
 - i386/pc386
 - i386/pc486
 - i386/pc586
-- 
2.35.3

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[PATCH 3/5] xilinx-zynqmp-rpu: Remove URLs from copyrights

[Sebastian Huber]

---
 spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml| 2 +-
 spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml  | 2 +-
 spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml   | 2 +-
 spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml 
b/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml
index ba70c44d7d..06795eb416 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml
@@ -5,7 +5,7 @@ actions:
 - env-append: null
 build-type: option
 copyrights:
-- Copyright (C) 2023 Reflex Aerospace GmbH ( https://www.reflexaerospace.com/ )
+- Copyright (C) 2023 Reflex Aerospace GmbH
 default:
 - enabled-by: true
   value:
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml 
b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
index d08f048060..3fa210d8e7 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
@@ -4,7 +4,7 @@ bsp: xilinx_zynqmp_mercuryxu5_rpu
 build-type: bsp
 cflags: []
 copyrights:
-- Copyright (C) 2023 Reflex Aerospace GmbH ( https://www.reflexaerospace.com/ )
+- Copyright (C) 2023 Reflex Aerospace GmbH
 cppflags: []
 enabled-by: true
 family: xilinx-zynqmp-rpu
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml 
b/spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml
index a3654f3f42..9c8a6d1cd6 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml
@@ -38,7 +38,7 @@ content: |
   _stack_end = bsp_section_stack_end;
   __undef_stack = bsp_section_stack_begin;
 copyrights:
-- Copyright (C) 2023 Reflex Aerospace GmbH ( https://www.reflexaerospace.com/ )
+- Copyright (C) 2023 Reflex Aerospace GmbH
 enabled-by: true
 install-path: ${BSP_LIBDIR}
 links: []
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml 
b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml
index 09a3965906..d684f5a06d 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml
@@ -4,7 +4,7 @@ actions:
 - define-condition: null
 build-type: option
 copyrights:
-- Copyright (C) 2023 Reflex Aerospace GmbH ( https://www.reflexaerospace.com/ )
+- Copyright (C) 2023 Reflex Aerospace GmbH
 default:
 - enabled-by: true
   value: true
-- 
2.35.3

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[PATCH 5/5] bsps: Add xilinx_zynqmp_lp64_a53 BSP variant

[Sebastian Huber]

Add a BSP variant without a board-specific name.
---
 .../bsps/aarch64/xilinx-zynqmp/bspa53lp64.yml | 21 +++
 .../bsps/aarch64/xilinx-zynqmp/optloadoff.yml |  1 +
 .../bsps/aarch64/xilinx-zynqmp/optramori.yml  |  1 +
 spec/build/bsps/objxilinxsupportlp64.yml  |  1 +
 spec/build/bsps/optxilsupportpath.yml |  1 +
 5 files changed, 25 insertions(+)
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/bspa53lp64.yml

diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/bspa53lp64.yml 
b/spec/build/bsps/aarch64/xilinx-zynqmp/bspa53lp64.yml
new file mode 100644
index 00..42316db4d3
--- /dev/null
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/bspa53lp64.yml
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: aarch64
+bsp: xilinx_zynqmp_lp64_a53
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH
+cppflags: []
+enabled-by: true
+family: xilinx-zynqmp
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+- role: build-dependency
+  uid: linkcmds_lp64
+- role: build-dependency
+  uid: objfdtzynqmp
+source: []
+type: build
diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/optloadoff.yml 
b/spec/build/bsps/aarch64/xilinx-zynqmp/optloadoff.yml
index 869181a95e..3a78b9af38 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/optloadoff.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/optloadoff.yml
@@ -9,6 +9,7 @@ copyrights:
 - Copyright (C) 2020 On-Line Applications Research (OAR)
 default:
 - enabled-by:
+  - aarch64/xilinx_zynqmp_lp64_a53
   - aarch64/xilinx_zynqmp_ilp32_zu3eg
   - aarch64/xilinx_zynqmp_lp64_cfc400x
   - aarch64/xilinx_zynqmp_lp64_zu3eg
diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/optramori.yml 
b/spec/build/bsps/aarch64/xilinx-zynqmp/optramori.yml
index c4d33094fb..33f0946532 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/optramori.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/optramori.yml
@@ -9,6 +9,7 @@ copyrights:
 - Copyright (C) 2020 On-Line Applications Research (OAR)
 default:
 - enabled-by:
+  - aarch64/xilinx_zynqmp_lp64_a53
   - aarch64/xilinx_zynqmp_ilp32_zu3eg
   - aarch64/xilinx_zynqmp_lp64_cfc400x
   - aarch64/xilinx_zynqmp_lp64_zu3eg
diff --git a/spec/build/bsps/objxilinxsupportlp64.yml 
b/spec/build/bsps/objxilinxsupportlp64.yml
index 330ffc34fd..252851a5aa 100644
--- a/spec/build/bsps/objxilinxsupportlp64.yml
+++ b/spec/build/bsps/objxilinxsupportlp64.yml
@@ -7,6 +7,7 @@ cppflags: []
 cxxflags: []
 enabled-by:
 - bsps/aarch64/xilinx_versal
+- aarch64/xilinx_zynqmp_lp64_a53
 - aarch64/xilinx_zynqmp_lp64_cfc400x
 - aarch64/xilinx_zynqmp_lp64_qemu
 - aarch64/xilinx_zynqmp_lp64_zu3eg
diff --git a/spec/build/bsps/optxilsupportpath.yml 
b/spec/build/bsps/optxilsupportpath.yml
index 298f9d5286..a90e6d3418 100644
--- a/spec/build/bsps/optxilsupportpath.yml
+++ b/spec/build/bsps/optxilsupportpath.yml
@@ -20,6 +20,7 @@ default:
   - aarch64/xilinx_zynqmp_ilp32_zu3eg
   value: arm/ARMv8/32bit
 - enabled-by:
+  - aarch64/xilinx_zynqmp_lp64_a53
   - aarch64/xilinx_zynqmp_lp64_cfc400x
   - aarch64/xilinx_zynqmp_lp64_qemu
   - aarch64/xilinx_zynqmp_lp64_zu3eg
-- 
2.35.3

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[PATCH 2/5] bsps: Use bsps/arm/xilinx-zynqmp-rpu

[Sebastian Huber]

---
 spec/build/bsps/objxilinxsupportr5.yml | 3 +--
 spec/build/bsps/optxilsupportpath.yml  | 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/spec/build/bsps/objxilinxsupportr5.yml 
b/spec/build/bsps/objxilinxsupportr5.yml
index d800b83247..25221c5e0d 100644
--- a/spec/build/bsps/objxilinxsupportr5.yml
+++ b/spec/build/bsps/objxilinxsupportr5.yml
@@ -5,8 +5,7 @@ copyrights:
 - Copyright (C) 2022 On-Line Applications Research (OAR)
 cppflags: []
 cxxflags: []
-enabled-by:
-- arm/xilinx_zynqmp_mercuryxu5_rpu
+enabled-by: bsps/arm/xilinx-zynqmp-rpu
 includes: []
 install:
 - destination: ${BSP_INCLUDEDIR}
diff --git a/spec/build/bsps/optxilsupportpath.yml 
b/spec/build/bsps/optxilsupportpath.yml
index 85bcc7e059..298f9d5286 100644
--- a/spec/build/bsps/optxilsupportpath.yml
+++ b/spec/build/bsps/optxilsupportpath.yml
@@ -7,7 +7,7 @@ copyrights:
 - Copyright (C) 2022 On-Line Applications Research (OAR)
 default:
 - enabled-by:
-  - arm/xilinx_zynqmp_mercuryxu5_rpu
+  - bsps/arm/xilinx-zynqmp-rpu
   value: arm/cortexr5
 - enabled-by: bsps/microblaze/microblaze_fpga
   value: microblaze
-- 
2.35.3

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