Re: [tools] tester: Remove hard coded time limits for SIS

On 7/5/22 12:45, Sebastian Huber wrote: On 05/07/2022 12:31, Chris Johns wrote: On 5 Jul 2022, at 6:23 pm, Sebastian Huber  wrote: On 05/07/2022 10:21, Chris Johns wrote: On 5/7/2022 4:29 pm, Sebastian Huber wrote: On 05/07/2022 08:23, Chris Johns wrote: On 5/7/2022 4:02 pm, Sebastian

Re: [tools] tester: Remove hard coded time limits for SIS

On 7/5/22 12:31, Chris Johns wrote: On 5 Jul 2022, at 6:23 pm, Sebastian Huber wrote: On 05/07/2022 10:21, Chris Johns wrote: On 5/7/2022 4:29 pm, Sebastian Huber wrote: On 05/07/2022 08:23, Chris Johns wrote: On 5/7/2022 4:02 pm, Sebastian Huber wrote: On 05/07/2022 07:14, Chris Johns

Re: Running SPARC/LEON3 in TSIM-LEON3 simulator

On 6/11/21 12:37 PM, Đức Anh wrote: Hi Sebastian, Thank you. I didn't notice that. I recompile with SMP enabled, and the application doesn't run successfully in the TSIM-LEON3 simulator. Below is the error message: Initializing and starting from 0x4000   CPU 0 in error mode

Re: [PATCH 5/5] bsps/sparc: Simplify memory initialization

On 6/8/21 4:14 PM, Sebastian Huber wrote: On 08/06/2021 16:03, Gedare Bloom wrote: I guess at some time, loading initialized data from the ROM was needed, but now it is not? I asked about this some time ago. I think these days the RTEMS application is always loaded by a boot loader

Fwd: How to debug on leon3 with sis and gdb

be set: --- $ ~/quick-start/rtems/6/bin/sparc-rtems6-sis -leon3 -m 4 ~/sis-quick-start/src/rtems/build/sparc/leon3/testsuites/smptests/smpschedstrongapa01.exe  SIS - SPARC/RISCV instruction simulator 2.26,  copyright Jiri Gaisler 2020  Bug-reports to j...@gais

[PATCH v3] smpfatal08: halt secondary processors if necessary

the test output. This patch stops the secondary cpus with a call to _CPU_Thread_Idle_body(). Tested on RISC-V and SPARC. >From 666fcbdb1fe8ef7d7988279d4da673de3cdd5d95 Mon Sep 17 00:00:00 2001 From: Jiri Gaisler Date: Sun, 11 Apr 2021 21:15:13 +0200 Subject: [PATCH] smpfatal08: block second

[PATCH v2] smpfatal08: halt secondary processors if necessary

: Jiri Gaisler Date: Sun, 11 Apr 2021 21:15:13 +0200 Subject: [PATCH] smpfatal08: block secondary processors * On some SMP platforms, all cpus are started by the boot-loader. We need to block the secondary cpus or they will clobber the test output. --- testsuites/smptests/smpfatal08/init.c | 3

Re: [PATCH] smpfatal08: halt secondary RISC-V processors

On 4/13/21 7:44 AM, Sebastian Huber wrote: On 12/04/2021 21:40, Jiri Gaisler wrote: I just realized that I can change the patch from an assembly WFI to a simple busy loop instead. This would work on any architecture without assembly. Should I provide a new patch with this cleaner solution

Re: [PATCH] smpfatal08: halt secondary RISC-V processors

provide a new patch with this cleaner solution? Jiri. On Sun, Apr 11, 2021 at 1:30 PM Jiri Gaisler wrote: smpfatal08 fails on SMP RISC-V systems because all cpus are started by the boot-loader and clobber the test output. This patch stops the secondary cpus with a WFI (wait-for-interrupt

[PATCH] smpfatal08: halt secondary RISC-V processors

722f8363fe131801ebb9f733f836d0bf6cd82c7a Mon Sep 17 00:00:00 2001 From: Jiri Gaisler Date: Sun, 11 Apr 2021 21:15:13 +0200 Subject: [PATCH] smpfatal08: halt secondary RISC-V processors * On most RISC-V platforms, all cpus are started by the boot-loader. We need to stop the secondary cpus or they will clobber the test

[PATCH] Open firmware: restore FDT in ofw01 to avoid test timeout

The ofw01 test will hang on RISC-V unless the real FDT is restored at the end of the test. This will allow the Sifive test module be found by _CPU_Fatal_halt() and avoid an infinite loop. From 7d285bb7b9d648bef2eb6bd39c5530c56beff287 Mon Sep 17 00:00:00 2001 From: Jiri Gaisler Date: Sun, 28

Fwd: [rtems-source-builder commit] devel/sis: Update to 2.26

: 0:04:48.685363 Forwarded Message Subject:[rtems-source-builder commit] devel/sis: Update to 2.26 Date: Sun, 20 Dec 2020 20:29:46 + From: Jiri Gaisler Reply-To: v...@rtems.org To: v...@rtems.org Module: rtems-source-builder Branch: master Commit

Re: MSYS2 build: header file missing

ilder --prefix=/opt/rtems/6 devel/sis Let me know if it builds OK for you and I will push the patch to the RSB tree... Jiri. > > Kind Regards > Robin > > > > On Fri, 18 Dec 2020 at 16:35, Jiri Gaisler <mailto:j...@gaisler.se>> wrote: > > > On 12/1

Re: MSYS2 build: header file missing

On 12/18/20 2:10 PM, Robin Müller wrote: > In case you're interested, this is the fail report for the SIS Cxc build on > Linux (failed both for i686 and x86_64). > > I think it fails because _WIN32_WINNT (windows version) is not defined, > causing winsock2.h to exclude requires sections. > >

Re: [PATCH v3 0/2] Add networking support for griscv bsp

Does anyone object to this patch? Otherwise I will go ahead and commit it... Jiri. On 11/1/20 4:46 PM, Jiri Gaisler wrote: > Third attempt. Needed to fix the waf build and add correct link address > for the griscv bsp. Tested with rtems-netdemos. > > Jiri Gaisler (2): > Add net

Re: Problems compiling rtems-libbsd

On 11/2/20 1:37 AM, Sebastian Huber wrote: Hello Jiri, it builds for me. I guess you installed the BSP before with RTEMS_NETWORKING == True and then again with RTEMS_NETWORKING == False. Please remove the BSP installation

Re: Problems compiling rtems-libbsd

I am a bit confused here - I was on RTEMS master and rtems-libbsd master which seems to be OK according to README.md. I switched to 6-freebsd12 for rtems-libbsd but the same errors occurred On Sun, Nov 1, 2020, 10:54 AM Jiri

Problems compiling rtems-libbsd

I am trying to build the rtems-libbsd package to test the new network stack. Configuration works fine, but compiling fails quickly. Log below, any ideas ...? jiri@carbon:~/ibm/src/rtems/rtems-libbsd$ python3 ./waf configure --rtems-bsps=sparc/leon3 --prefix=/opt/rtems/6

[PATCH v3 1/2] Add networking support for griscv bsp

* Only GRETH device supported for now * Fix endian problem in GRETH driver * Remove SPARC assembly from greth.c * Builds with both autoconf and waf --- bsps/riscv/griscv/console/console.c | 2 +- bsps/riscv/griscv/include/bsp.h | 14 +

[PATCH v3 0/2] Add networking support for griscv bsp

Third attempt. Needed to fix the waf build and add correct link address for the griscv bsp. Tested with rtems-netdemos. Jiri Gaisler (2): Add networking support for griscv bsp Add correct link address for griscv waf build bsps/riscv/griscv/console/console.c | 2 +- bsps/riscv

[PATCH v3 2/2] Add correct link address for griscv waf build

--- spec/build/bsps/riscv/optrambegin.yml | 3 +++ spec/build/bsps/riscv/optramsize.yml | 3 +++ 2 files changed, 6 insertions(+) diff --git a/spec/build/bsps/riscv/optrambegin.yml b/spec/build/bsps/riscv/optrambegin.yml index cf5d909562..2073926dac 100644 ---

[PATCH v2] Add networking support for griscv bsp

* Only GRETH device supported for now * Fix endian problem in GRETH driver * Remove SPARC assembly from greth.c * Builds with both autoconf and waf --- bsps/riscv/griscv/console/console.c | 2 +- bsps/riscv/griscv/include/bsp.h | 14 +

Re: AW: AW: [PATCH 1/3] Remove duplicate GRETH driver

On 10/28/20 8:57 AM, gabriel.moy...@dlr.de wrote: >> Hi Jiri, >> >> My understanding was that one driver version was meant to be used >> with drvmgr (greth.c) and the other without it (greth2.c). May I ask why do you've chosen to remove greth.c and not greth2.c?

Re: AW: [PATCH 1/3] Remove duplicate GRETH driver

On 10/28/20 2:44 AM, jan.som...@dlr.de wrote: > >> -Original Message- >> From: devel On Behalf Of Jiri Gaisler >> Sent: Tuesday, October 27, 2020 3:18 PM >> To: devel@rtems.org >> Subject: Re: AW: [PATCH 1/3] Remove duplicate GRETH driver >> >&g

Re: AW: [PATCH 1/3] Remove duplicate GRETH driver

On 10/26/20 8:52 AM, Jiri Gaisler wrote: > On 10/26/20 3:37 AM, gabriel.moy...@dlr.de wrote: >> Hi Jiri, >> >> My understanding was that one driver version was meant to be used with >> drvmgr (greth.c) and the other without it (greth2.c). May I ask why do >>

Re: AW: [PATCH 1/3] Remove duplicate GRETH driver

tical, but only greth,c seems to be maintained. PHY handling and multi-cast support are areas where the files have diverged. But this is an other discussion ... > > Thanks, > Gabriel > > -Ursprüngliche Nachricht- > Von: devel Im Auftrag von Jiri Gaisler > Gesen

[PATCH 2/3] Add networking support for griscv bsp

* Only GRETH device supported for now * Fix endian problem in GRETH driver --- bsps/riscv/griscv/include/bsp.h | 14 ++ bsps/riscv/griscv/net/leon_greth.c| 59 +++ bsps/shared/net/greth2.c | 6 ++-

[PATCH 0/3] RISC-V/griscv networking support

These patches add networking support to the RISC-V/griscv bsp. Also a seemingly redundant GRETH driver is removed. Feedback on the removal would be appreciated. Jiri Gaisler (3): Remove duplicate GRETH driver Add networking support for griscv bsp The leon3 bsp should define CPU_U32_FIX

[PATCH 1/3] Remove duplicate GRETH driver

* bsps/shared/net/greth2.c is being used instead --- bsps/shared/grlib-sources.am |4 - bsps/shared/grlib/net/README |7 - bsps/shared/grlib/net/greth.c | 1655 - bsps/shared/grlib/net/network_interface_add.c | 62

[PATCH 3/3] The leon3 bsp should define CPU_U32_FIX

* CPU_U32_FIX needed to avoid unaligned data access trap in network stack. --- bsps/sparc/leon3/include/bsp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/bsps/sparc/leon3/include/bsp.h b/bsps/sparc/leon3/include/bsp.h index 85730b5e20..a4060385c8 100644 ---

Updated network-demos ...?

Does anyone have more a updated version of network-demos than what is in https://git.rtems.org/network-demos/ ? This version does not compile fully with RTEMS-6 and seems to be rather outdated. If not, then I will try to fix the issues - just want to check if someone has already done this.

Re: dl06 fails to build for RISC-V (griscv bsp)

../riscv-rtems6/lib/rv32imafd/ilp32d/libm.a:lib_a-e_atan2.o@709534 Does this indicate that newlib must be build with -mno-relax? If so, maybe we should disable the dlxx tests for RISC-V ..? > > On Sun, 6 Sep 2020 at 19:50, Jiri Gaisler wrote: >> I re-applied your patch and dl06 bui

Re: [RTEMS Project] #4069: dl06 does not link on RISCV

On 9/6/20 11:12 PM, RTEMS trac wrote: > #4069: dl06 does not link on RISCV > -+- > Reporter: Chris Johns | Owner: Hesham Almatary > | > Type: defect | Status: closed >

Tftp patch to rtems-tools breaks compilation (on ubuntu 18.04 x64)

jiri@office:~/ibm/src/rtems/rtems-tools$ ./waf configure --prefix=/opt/rtems/6 Setting top to   : /home/jiri/ibm/src/rtems/rtems-tools Setting out to   : /home/jiri/ibm/src/rtems/rtems-tools/build Version  :

Re: dl06 fails to build for RISC-V (griscv bsp)

e what has changed since then. > > [1] https://lists.rtems.org/pipermail/devel/2020-August/061717.html > [2] > https://github.com/RTEMS/rtems-tools/commit/e6e610d262940b7651157597b6b1406aa806b4d1 > > On Sun, 6 Sep 2020 at 09:14, Chris Johns wrote: >> On 6/9/20 6:32 am,

dl06 fails to build for RISC-V (griscv bsp)

I have updated both RTEMS and RSB to git head, and dl06 now fails to build: riscv-rtems6-g++ -march=rv32imafd -mabi=ilp32d -O2 -g -ffunction-sections -fdata-sections -Wall  -Wl,--gc-sections  -march=rv32imafd -mabi=ilp32d  -B./../../lib/libbsp/riscv/griscv

Re: Need help to execute/debug smpschededf02.exe on leon3

ite with gdb running on sis. > > > > I started sis with the command: > > > --- > > > > $ ./sparc-rtems5-sis -leon3 -m 4 -gdb > > > >  SIS - SPARC/RISCV instruction simulator 2.21,

Re: Need help to execute/debug smpschededf02.exe on leon3

is it running into an infinite loop?(If I use nexti, it does not > run into an infinite loop as next does get inside functions, and Init > finishes successfully). The loop is not infinite, it just loops while waiting for the UART transmitter to send out a character. nexti puts a breakpoint a

Re: Need help to execute/debug smpschededf02.exe on leon3

/smptests/smpschededf02.exe > > SIS - SPARC/RISCV instruction simulator 2.21, copyright Jiri Gaisler 2019 > Bug-reports to j...@gaisler.se > > LEON3 emulation enabled, 4 cpus online, delta 50 clocks > > Loaded > /home/richi/quick-start/build/leon3/sparc-rtems5/c/leon3/test

Re: Unable to complete the Hello World program

On 3/1/20 9:56 AM, Denil Verghese wrote: > Hi, >     I'm Denil C Verghese and I like to be a part contribute to this > organization as well as participate in upcoming GSoC program. I have checked > the Wiki entries related to GSoC. But I'm facing some error in completing the > quick start

Re: Error in building rv32imac BSP

On 2/20/20 5:03 PM, Eshan Dhawan wrote: > > make[3]: Leaving directory > '/home/eshan/development/rtems/kernel/rtems/rv32imac/riscv-rtems5/c/rv32imac' > checking for RTEMS_CPU_MODEL... > checking for RTEMS_BSP_FAMILY... riscv > checking for CPU_CFLAGS... (cached) -march=rv32imac -mabi=ilp32 >

Re: Status of fenv.h header and floating point environment support in newlib

On 2/17/20 11:16 AM, Vaibhav Gupta wrote: > > > On Mon, Feb 17, 2020, 3:07 PM Ayush Dwivedi <21cencturyay...@gmail.com > > wrote: > > Hello Joel, > This is regarding the open project #2966 POSIX-Compliance #2971( Add > fenv.h to newlib). The task is

Re: [PATCH v2] doc/raspberrypi: Added instructions for raspberrypi

You should build devel/qemu4 with RSB, the older devel/qemu does not build on newer systems ... Jiri. On 1/12/20 4:48 PM, Niteesh wrote: > I can't build QEMU using RSB, there seems to be a problem with GLib(see > attachment) > but I had no problem building it from the source. Should I just

Re: Build FreeBSD: FAILED 6/rtems-sparc on x86_64-freebsd12.1 (sparc-rtems6-gdb-5085593976-x86_64-freebsd12.1-1)

On 12/5/19 8:38 AM, Sebastian Huber wrote: > On 04/12/2019 14:56, sebastian.hu...@embedded-brains.de wrote: >> ../../../sourceware-mirror-binutils-gdb-5085593976/sim/erc32/sis.c:36:10: >> fatal error: 'readline/readline.h' file not found >> #include "readline/readline.h" > > This is the GDB

Re: sparc-rtems-gdb doesn't recognize target "sim"

On 11/13/19 9:48 AM, Vaibhav Gupta wrote: > You can also use "sis" > > 1- Open Terminal 1 and write: > > $ sparc-rtems5-sis -gdb >         # It will print 'gdb: listening on port 1234'. >         # Note you can define port number with '-port' option. > > 2-Open Terminal 2 and write: > > $

Re: psxfenv01 fails to compile for RISCV

On 11/9/19 8:38 PM, Jiri Gaisler wrote: > > > On 11/9/19 7:57 PM, Joel Sherrill wrote: >> >> >> On Sat, Nov 9, 2019, 12:40 PM Jiri Gaisler > <mailto:j...@gaisler.se>> wrote: >> >> I get this error for psxfenv01 with the latest RTEMS and RSB b

Re: psxfenv01 fails to compile for RISCV

On 11/9/19 7:57 PM, Joel Sherrill wrote: > > > On Sat, Nov 9, 2019, 12:40 PM Jiri Gaisler <mailto:j...@gaisler.se>> wrote: > > I get this error for psxfenv01 with the latest RTEMS and RSB build: > > riscv-rtems5-gcc -DHAVE_CONFIG_H -I. > -I/ho

psxfenv01 fails to compile for RISCV

I get this error for psxfenv01 with the latest RTEMS and RSB build: riscv-rtems5-gcc -DHAVE_CONFIG_H -I. -I/home/jiri/ibm/src/rtems/rtems/c/src/../../testsuites/psxtests   -I. -I/home/jiri/src/rtems/riscvmp/riscv-rtems5/c/griscv/include -I/home/jiri/ibm/src/rtems/rtems/cpukit/include

Expired certificate on devel.rtems.org ...?

I cannot connect to devel.rtems.org this morning, firefox and chromium claims that the certificate has expired. Seems that the let's encrypt certificate was not auto-updated ... ___ devel mailing list devel@rtems.org

Re: RSB Qemu Leon3 patches error

On 10/25/19 4:01 PM, Joel Sherrill wrote: > Hi > > I am not sure what's up with the Leon patches but I am getting a checksum > error and wanted to see if Jiri or someone else knowledgeable could > investigate and fix. > > warning: checksum error: 0001-LEON3-Add-emulation-of-AMBA-plug-play.patch

Re: [PATCH] Update the help to match the available options.

Looks good to me - push ... On 10/21/19 2:48 PM, chr...@rtems.org wrote: > From: Chris Johns > > --- > help.c | 7 +-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/help.c b/help.c > index 2593d84..b3f5407 100644 > --- a/help.c > +++ b/help.c > @@ -25,8 +25,11 @@

Re: Problem running sparc-rtems5-gdb

On 9/22/19 6:30 AM, Niteesh wrote: > I was following the quick-start guide from > https://docs.rtems.org/branches/master/user/start/index.html > I followed the exact steps but still couldn't get the hello world > running. I face issues when running the GDB, when trying to set the > target to

[PATCH RSB] Add gdb-8.3 as default debugger

I suggest that we switch to gdb-8.3 for targets that currently use 8.2.1. The update is relatively minor but allows building without any patches. Tested for SPARC and RISC-V targets. Jiri. >From 5b12c03d184d6cea7019636fc134e06d25a94d9f Mon Sep 17 00:00:00 2001 From: Jiri Gaisler Date: Wed,

Re: [RSB PATCH] Added qemu 4.1.0 as bare target

On 8/20/19 12:44 AM, Chris Johns wrote: > On 20/8/19 6:53 am, Jiri Gaisler wrote: >> This patch will add QEMU-4.1.0 as RSB target devel/qemu4. > Looks good. > >> The current devel/qemu target will be preserved. > Should devel/qemu just point to qemu4? I am OK with this

[PATCH rtems-tools] leon3-qemu.ini for rtems-test needs custom parameters to work

The standard parameters for leon3-qemu bsp for rtems-test do not work - custom ones are needed. From fb2d18063958d26c016bed2a4880507c9d688d87 Mon Sep 17 00:00:00 2001 From: Jiri Gaisler Date: Mon, 19 Aug 2019 22:45:04 +0200 Subject: [PATCH] leon3-qemu.ini for rtems-test needs custom parameters

[RSB PATCH] Added qemu 4.1.0 as bare target

: 0 -- Total: 530 Average test time: 0:00:00.539311 Testing time : 0:04:45.834903 From 690cbb8023a42d57fea352ff45458dd87ec93bb3 Mon Sep 17 00:00:00 2001 From: Jiri Gaisler Date: Mon, 19 Aug 2019 22:12:26 +0200 Subject: [PATCH] Added qemu 4.1.0 as bare target

Re: Checksum Error on Leon3 Qemu patches

On 8/18/19 10:30 PM, Jiri Gaisler wrote: > > > On 8/17/19 8:23 PM, Joel Sherrill wrote: >> >> >> On Sat, Aug 17, 2019, 1:07 PM Jiri Gaisler > <mailto:j...@gaisler.se>> wrote: >> >> >> On 8/16/19 11:03 PM, Juan Rafael García Blanco

Re: Checksum Error on Leon3 Qemu patches

On 8/17/19 8:23 PM, Joel Sherrill wrote: > > > On Sat, Aug 17, 2019, 1:07 PM Jiri Gaisler <mailto:j...@gaisler.se>> wrote: > > > On 8/16/19 11:03 PM, Juan Rafael García Blanco wrote: >> Hi, >> >> AFAIK, the last qemu major version include

Re: Checksum Error on Leon3 Qemu patches

On 8/17/19 8:23 PM, Joel Sherrill wrote: > > > On Sat, Aug 17, 2019, 1:07 PM Jiri Gaisler <mailto:j...@gaisler.se>> wrote: > > > On 8/16/19 11:03 PM, Juan Rafael García Blanco wrote: >> Hi, >> >> AFAIK, the last qemu major version incl

Re: Checksum Error on Leon3 Qemu patches

es unpatched. Is there a reason why the qemu version built by RSB is from June 2015 ..? Jiri. > > Regards, > Juan. > > On Fri, Aug 16, 2019, 11:00 PM Jiri Gaisler <mailto:j...@gaisler.se>> wrote: > > > On 8/15/19 12:09 AM, Joel Sherrill wrote: > > On Wed, A

Re: Checksum Error on Leon3 Qemu patches

On 8/15/19 12:09 AM, Joel Sherrill wrote: > On Wed, Aug 14, 2019 at 4:42 PM Chris Johns wrote: >> On 15/8/19 12:46 am, Joel Sherrill wrote: >>> Qemu isn't building due to a checksum error. >>> >>> These patches are at gaisler.org. I don't know where to move them but >>> eventually they should

Re: fenv on RISC-V

Having said that, I will check if the generation of FP exception flag for RISC-V in sis are as accurate as for SPARC. Generating the wrong flags could cause the type of failures we are seeing ... On 8/14/19 10:42 PM, Jiri Gaisler wrote: > Interesting. I can confirm that the griscv bsp is us

Re: fenv on RISC-V

Interesting. I can confirm that the griscv bsp is using hard floats and doubles, it is compiled with -march=rv32imafd -mabi=ilp32d. The paranoia benchmark runs successfully and uses float instructions and registers. The sis simulator emulates all float and double instructions as define in the

Re: rtems-tester with griscv

You should probably use --rtems-bsp=griscv-sis . The griscv bsp uses the (now deleted) built-in sis in gdb... I am preparing a patch to purge the stale tester bsps ... Jiri. On 8/12/19 8:22 PM, Joel Sherrill wrote: > Hi > > Running riscv-rtems5-sis by hand, hello.exe runs. But when I try it

Re: Problem: RSB does no longer install stand-alone sis

On 8/11/19 2:35 AM, Chris Johns wrote: > On 10/8/19 11:17 pm, Jiri Gaisler wrote: >> The problem comes from a commit to source-builder/config/sis-2-1.cfg, >> made on July 23. > I am aware this is the problem and a revert may work for you but I seem to > remember it did a

Re: RISC-V Test Results

On 8/8/19 3:33 PM, Joel Sherrill wrote: > Hi > > If you are subscribed to the build@ mailing list, then you saw the > flurry of test > results from over night. I built every variant and ran the test suite > with RTEMS  > debug on and off.  Here are some observations: > > + rv64imafd only has one

Re: Problem: RSB does no longer install stand-alone sis

sses at the >> moment! >> > Thanks for taking the time to look. I must have broken something. I will take > a > look this weekend. Sorry about this. > > Chris >>> On Thu, Aug 8, 2019 at 3:43 PM Jiri Gaisler wrote: >>>> RSB does not lon

Re: sis/gdb on Cygwin

On 8/9/19 8:34 PM, Jiri Gaisler wrote: > > > On 8/9/19 3:24 PM, Joel Sherrill wrote: >> I thought I saw a patch pushed yesterday afternoon but a fresh build today >> shows the same >> breakage.  >> >> Jiri .. feel free to push a fix for this and I will te

Re: sis/gdb on Cygwin

Cygwin and termcap which is  > now not needed. Unfortunately, that same code is in > sis/configure.ac <http://configure.ac>.  > > Please and thank you. :) > > --joel > > > On Wed, Aug 7, 2019 at 8:37 PM Chris Johns <mailto:chr...@rtems.org>&g

Re: [RSB PATCH v2] Disable built-in sis in gdb.

rather than just a git repo * No support for data watchpoints in the gdb sim interface * Build problems for Cygwin I also like the simplicity of a built-in simulator, but a stand-alone sim is just so much easier to develop and maintain... > > On Thu, Aug 8, 2019, 4:47 PM Jiri Gaisle

[RSB PATCH v2] Disable built-in sis in gdb.

This time it also works on RISC-V ... :-) >From e5460e9ecb9995298319653460fab8852274c211 Mon Sep 17 00:00:00 2001 From: Jiri Gaisler Date: Thu, 8 Aug 2019 22:20:39 +0200 Subject: [PATCH] Disable built-in sis in gdb. * Avoid building problems on Cygwin et al. * Avoid mix-up with more rec

Problem: RSB does no longer install stand-alone sis

RSB does not longer install the stand-alone version of sis. Even though the RSB log claims is does, the binary is not copied to the install location: installing: sis-2.17-x86_64-linux-gnu-1 -> /opt/rtems/5    does nothing There has been a few commits that changes the RSB install scripts

Re: [RSB PATCH] Disable built-in sis in gdb.

OK, this patch kills building gdb for RISC-V - I will resubmit with a proper fix ... Jiri. On 8/8/19 10:45 PM, Jiri Gaisler wrote: > Small patch for RSB  to disable building sis inside gdb. > > I will follow up with a patch for rtems-tools to clean up rtems-test targets > for sis

[RSB PATCH] Disable built-in sis in gdb.

Small patch for RSB  to disable building sis inside gdb. I will follow up with a patch for rtems-tools to clean up rtems-test targets for sis ... Jiri. >From 9165334d3ffe9996276de9c7843998124890c3e3 Mon Sep 17 00:00:00 2001 From: Jiri Gaisler Date: Thu, 8 Aug 2019 22:20:39 +0200 Subj

Re: sis/gdb on Cygwin

On 8/7/19 8:22 PM, Joel Sherrill wrote: > Hi > > Looks like Cygwin has libncurses but doesn't install the libtermcap. > compatibility library. > > https://cygwin.com/ml/cygwin/2010-10/msg00018.html  says to link > against ncurses. > >  gdb-8.2.1/sim/sis/../.. `echo -Dsparc-rtems5 | sed

[RSB PATCH 1/2] Add bare target to build standalone sis (devel/sis)

--- bare/config/devel/sis-2-1.cfg | 18 + bare/config/devel/sis.bset| 8 source-builder/config/sis-2-1.cfg | 66 +++ 3 files changed, 92 insertions(+) create mode 100644 bare/config/devel/sis-2-1.cfg create mode 100644

[RSB PATCH 0/2] Add standalone SIS as build target

Two patches to add standalone SIS as bare target, and to build it for SPARC and RISC-V tool-chains. Jiri Gaisler (2): Add bare target to build standalone sis (devel/sis) Build standalone sis for SPARC and RISC-V targets bare/config/devel/sis-2-1.cfg | 18 + bare/config/devel

[RSB PATCH 2/2] Build standalone sis for SPARC and RISC-V targets

--- rtems/config/5/rtems-riscv.bset | 1 + rtems/config/5/rtems-sparc.bset | 2 ++ 2 files changed, 3 insertions(+) diff --git a/rtems/config/5/rtems-riscv.bset b/rtems/config/5/rtems-riscv.bset index 99f0754..6e9de99 100644 --- a/rtems/config/5/rtems-riscv.bset +++

Re: RSB SPARC gdb 8.2.1 Build Issue on MSYS2 (64-bit)

On 6/4/19 12:59 AM, Joel Sherrill wrote: > Hi > > I was trying to build the sparc tools on MSYS2 today. SIS was enabled > by default and failed to build.  > > Is it expected to build? > > Is it supposed to be disabled and the host is not properly detected by > the RSB? > > Not sure which way to

Re: Potential SIS or RTEMS/libbsd problem

On 6/3/19 4:14 AM, Chris Johns wrote: > On 1/6/19 6:58 am, Jiri Gaisler wrote: >> I have pushed a small patch to fix some build problems on Cygwin and >> FreeBSD. I don't know how fast we want to progress, but I could prepare a >> patch for RSB to use the new sis reposi

Re: Potential SIS or RTEMS/libbsd problem

On 5/31/19 7:06 AM, Sebastian Huber wrote: > On 27/05/2019 11:03, Jiri Gaisler wrote: >> On 5/23/19 1:47 PM, Sebastian Huber wrote: >>> On 22/05/2019 22:34, Jiri Gaisler wrote: >>>> Adding a pseudo-random delay of 0 - 15 clocks to each trap/interrupt >>&

Re: How important is Cygwin support for host tools?

On 5/30/19 2:46 PM, Joel Sherrill wrote: > > > On Thu, May 30, 2019, 7:41 AM Jiri Gaisler <mailto:j...@gaisler.se>> wrote: > > Does anyone still use Cygwin for RTEMS development? The reason I > ask is > that I have some portability issues for sis

How important is Cygwin support for host tools?

Does anyone still use Cygwin for RTEMS development? The reason I ask is that I have some portability issues for sis (no async I/O on sockets in Cygwin) and I would like to avoid some ugly workarounds if possible. In the age of virtualization and even WSL in Win 10, do we still need Cygwin ...?

Re: Potential SIS or RTEMS/libbsd problem

On 5/23/19 1:47 PM, Sebastian Huber wrote: > On 22/05/2019 22:34, Jiri Gaisler wrote: >> Adding a pseudo-random delay of 0 - 15 clocks to each trap/interrupt causes >> the test to pass on all cpu configurations with the default time slice >> (50)..! I am not sure what

Re: Potential SIS or RTEMS/libbsd problem

On 5/23/19 7:35 AM, Sebastian Huber wrote: > On 22/05/2019 22:34, Jiri Gaisler wrote: >> On 5/22/19 7:43 PM, Jiri Gaisler wrote: >>> On 5/22/19 9:49 AM, Sebastian Huber wrote: >>>> On 22/05/2019 09:39, Jiri Gaisler wrote: >>>>> On 5/22/19

Re: Potential SIS or RTEMS/libbsd problem

On 5/23/19 1:47 PM, Sebastian Huber wrote: > On 22/05/2019 22:34, Jiri Gaisler wrote: >> Adding a pseudo-random delay of 0 - 15 clocks to each trap/interrupt >> causes the test to pass on all cpu configurations with the default >> time slice (50)..! I am not sure what

Re: Potential SIS or RTEMS/libbsd problem

On 5/22/19 7:43 PM, Jiri Gaisler wrote: > On 5/22/19 9:49 AM, Sebastian Huber wrote: >> On 22/05/2019 09:39, Jiri Gaisler wrote: >>> On 5/22/19 8:03 AM, Sebastian Huber wrote: >>>> Hello, >>>> >>>> in the libbsd there is a test for the Ep

Re: Potential SIS or RTEMS/libbsd problem

On 5/22/19 9:49 AM, Sebastian Huber wrote: > On 22/05/2019 09:39, Jiri Gaisler wrote: >> On 5/22/19 8:03 AM, Sebastian Huber wrote: >>> Hello, >>> >>> in the libbsd there is a test for the Epoch Based Reclamation: >>> >>> https://git.rte

Re: Potential SIS or RTEMS/libbsd problem

o find time to look at it in more detail. A quick trace shows that all CPUs are stuck in a loop checking for a lock or similar: $ ./sis -leon3 ~/epoch01.exe -m 4 -d 1  SIS - SPARC/RISCV instruction simulator 2.14,  copyright Jiri Gaisler 2019  Bug-reports to j...@gaisler.se  LEON3 emulation ena

Re: TSIM coverage format?

From the TSIM manual: "The coverage data for each 32-bit word of memory consists of a 5-bit field, with bit0 (lsb) indicating that the word has been executed, bit1 indicating that the word has been written, and bit2 that the word has been read. Bit3 and bit4 indicates the presence of a branch

Re: [PATCH] leon2-sis.ini, leon3-sis.ini: Correct run arguments

I don't think this patch is necessary, the -r option is already present and does not need to be duplicated. Jiri. On 2019-03-14 14:21, Joel Sherrill wrote: --- tester/rtems/testing/bsps/leon2-sis.ini | 2 +- tester/rtems/testing/bsps/leon3-sis.ini | 2 +- 2 files changed, 2 insertions(+),

[PATCH] RSB: upgrade to sis 2.13 (was: Issue with sis and Leon3)

Sherrill wrote: > Thank you for being so responsive.  > > I suspected a missing flush but had no idea where to look. I hopedyou > would spot the missing line of code quickly and was right. :) > > --joel > > On Thu, Feb 28, 2019 at 1:01 PM Jiri Gaisler <mailto:j...@ga

Re: Issue with sis and Leon3

On 2/26/19 11:04 PM, Joel Sherrill wrote: > > > On Tue, Feb 26, 2019 at 2:06 PM Jiri Gaisler <mailto:j...@gaisler.se>> wrote: > > > On 2/26/19 8:49 PM, Joel Sherrill wrote: >> >> >> On Tue, Feb 26, 2019 at 1:28 PM Jiri Gaisler > <mailt

Re: Issue with sis and Leon3

On 2/26/19 8:49 PM, Joel Sherrill wrote: > > > On Tue, Feb 26, 2019 at 1:28 PM Jiri Gaisler <mailto:j...@gaisler.se>> wrote: > > > On 2/26/19 8:08 PM, Joel Sherrill wrote: > > Hi > > > > I think something is wrong with sis on th

Re: Issue with sis and Leon3

parc$ sparc-rtems5-sis  SIS - SPARC/RISCV instruction simulator 2.12,  copyright Jiri Gaisler 2019  Bug-reports to j...@gaisler.se  ERC32 emulation enabled sis> q Jiri. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

[PATCH] griscv: add additional cpu configurations

>From 568490a054b9bf27ddad99a6a186e363123dd432 Mon Sep 17 00:00:00 2001 From: Jiri Gaisler Date: Fri, 8 Feb 2019 12:40:45 +0100 Subject: [PATCH] griscv: add additional cpu configurations * Also switch default config to imafd as the C extension is not supported for code coverage --- b

Re: Break points with latest SIS

Hello Sebastian, here is a patch for RSB that improves sis debugging in gdb and on SMP systems: * Correct break-point handling in gdb * Detect and break on NULL pointer derefence (call/jump) * Single stepping (stepi) in gdb/sis keeps focus on debugged cpu * 'sim cpu' command shows active cpu

Re: Break points with latest SIS

On 2/7/19 12:53 PM, Jiri Gaisler wrote: > On 2/7/19 12:45 PM, Sebastian Huber wrote: >> On 07/02/2019 12:43, Jiri Gaisler wrote: >>> Works OK here: >>> >>> $ sparc-rtems5-sis -leon3 -nouartrx -r -tlim 200 s -m 4  >>> ./sparc-rtems5/c/leon3

Re: Break points with latest SIS

On 2/7/19 12:45 PM, Sebastian Huber wrote: > > > On 07/02/2019 12:43, Jiri Gaisler wrote: >> Works OK here: >> >> $ sparc-rtems5-sis -leon3 -nouartrx -r -tlim 200 s -m 4  >> ./sparc-rtems5/c/leon3/testsuites/smptests/smpswitchextension01.exe >> >>  

Re: Break points with latest SIS

Works OK here: $ sparc-rtems5-sis -leon3 -nouartrx -r -tlim 200 s -m 4  ./sparc-rtems5/c/leon3/testsuites/smptests/smpswitchextension01.exe  SIS - SPARC/RISCV instruction simulator 2.11,  copyright Jiri Gaisler 1995  Bug-reports to j...@gaisler.se  LEON3 emulation enabled, 4 cpus online, delta

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