Re: [PATCH v3 19/42] bsps/irq: Implement new directives for GICv2/3
On 23/07/2021 17:03, Gedare Bloom wrote:
@@ -195,15 +246,35 @@ rtems_status_code bsp_interrupt_raise_on(
uint32_tcpu_index
)
{
- bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
- return RTEMS_UNSATISFIED;
+ if (vector >= 16) {
Use (vector > ARM_GIC_IRQ_SGI_LAST) for clarity?
no need to repost for this change.
Ok, I will fix this. This part was older than the defines.
+return RTEMS_UNSATISFIED;
+ }
+
+ arm_gic_trigger_sgi(vector, 1U << cpu_index);
Should we assert cpu_index <
rtems_configuration_get_maximum_processors()? That would be consistent
with using assert that the vector is valid, since both are handled
when coming in through the rtems_interrupt_*() interface.
Yes, this makes sense.
--
embedded brains GmbH
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
https://embedded-brains.de/datenschutzerklaerung/
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 34/42] validation: Test rtems_interrupt_vector_disable()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
.../validation/tc-intr-vector-disable.c | 632 ++
2 files changed, 633 insertions(+)
create mode 100644 testsuites/validation/tc-intr-vector-disable.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 36d2a0f388..78633bebe5 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -16,6 +16,7 @@ source:
- testsuites/validation/tc-barrier-release.c
- testsuites/validation/tc-barrier-wait.c
- testsuites/validation/tc-intr-get-attributes.c
+- testsuites/validation/tc-intr-vector-disable.c
- testsuites/validation/tc-intr-vector-enable.c
- testsuites/validation/tc-intr-vector-is-enabled.c
- testsuites/validation/tc-message-construct-errors.c
diff --git a/testsuites/validation/tc-intr-vector-disable.c
b/testsuites/validation/tc-intr-vector-disable.c
new file mode 100644
index 00..7596f4f526
--- /dev/null
+++ b/testsuites/validation/tc-intr-vector-disable.c
@@ -0,0 +1,632 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqVectorDisable
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqVectorDisable \
+ * spec:/rtems/intr/req/vector-disable
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqVectorDisable_Pre_Vector_Valid,
+ RtemsIntrReqVectorDisable_Pre_Vector_Invalid,
+ RtemsIntrReqVectorDisable_Pre_Vector_NA
+} RtemsIntrReqVectorDisable_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqVectorDisable_Pre_IsEnabled_Yes,
+ RtemsIntrReqVectorDisable_Pre_IsEnabled_No,
+ RtemsIntrReqVectorDisable_Pre_IsEnabled_NA
+} RtemsIntrReqVectorDisable_Pre_IsEnabled;
+
+typedef enum {
+ RtemsIntrReqVectorDisable_Pre_CanDisable_Yes,
+ RtemsIntrReqVectorDisable_Pre_CanDisable_Maybe,
+ RtemsIntrReqVectorDisable_Pre_CanDisable_No,
+ RtemsIntrReqVectorDisable_Pre_CanDisable_NA
+} RtemsIntrReqVectorDisable_Pre_CanDisable;
+
+typedef enum {
+ RtemsIntrReqVectorDisable_Post_Status_Ok,
+ RtemsIntrReqVectorDisable_Post_Status_InvId,
+ RtemsIntrReqVectorDisable_Post_Status_Unsat,
+ RtemsIntrReqVectorDisable_Post_Status_NA
+} RtemsIntrReqVectorDisable_Post_Status;
+
+typedef enum {
+ RtemsIntrReqVectorDisable_Post_IsEnabled_Nop,
+ RtemsIntrReqVectorDisable_Post_IsEnabled_No,
+ RtemsIntrReqVectorDisable_Post_IsEnabled_Maybe,
+ RtemsIntrReqVectorDisable_Post_IsEnabled_NA
+} RtemsIntrReqVectorDisable_Post_IsEnabled;
+
+/**
+ * @brief Test context for spec:/rtems/intr/req/vector-disable test case.
+ */
+typedef struct {
+ /**
+ * @brief If this member is true, then an interrupt occurred.
+ */
+ bool interrupt_occurred;
+
+ /**
+ * @brief This
[PATCH v3 24/42] bsps/irq: Move bsp_interrupt_handler_is_empty()
This function is only used by one BSP.
Update #3269.
---
bsps/i386/shared/irq/irq.c | 11 +++
bsps/include/bsp/irq-generic.h | 11 ---
bsps/shared/irq/irq-generic.c | 19 ---
3 files changed, 11 insertions(+), 30 deletions(-)
diff --git a/bsps/i386/shared/irq/irq.c b/bsps/i386/shared/irq/irq.c
index a0745ab41d..3ba1051f8f 100644
--- a/bsps/i386/shared/irq/irq.c
+++ b/bsps/i386/shared/irq/irq.c
@@ -351,6 +351,17 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
return RTEMS_SUCCESSFUL;
}
+static bool bsp_interrupt_handler_is_empty(rtems_vector_number vector)
+{
+ rtems_vector_number index;
+ rtems_interrupt_entry *head;
+
+ index = bsp_interrupt_handler_index(vector);
+ head = _interrupt_handler_table[index];
+
+ return bsp_interrupt_is_empty_handler_entry(head);
+}
+
/*
* Global so the asm handler can call it.
*/
diff --git a/bsps/include/bsp/irq-generic.h b/bsps/include/bsp/irq-generic.h
index e9cb0b4bb9..12e8f9155b 100644
--- a/bsps/include/bsp/irq-generic.h
+++ b/bsps/include/bsp/irq-generic.h
@@ -415,17 +415,6 @@ static inline void bsp_interrupt_handler_dispatch(
rtems_vector_number vector )
}
}
-/**
- * @brief Is interrupt handler empty.
- *
- * This routine returns true if the handler is empty and has not been
- * initialised else false is returned. The interrupt lock is not used
- * so this call can be used from within interrupts.
- *
- * @return If empty true shall be returned else false is returned.
- */
-bool bsp_interrupt_handler_is_empty(rtems_vector_number vector);
-
/** @} */
/**
diff --git a/bsps/shared/irq/irq-generic.c b/bsps/shared/irq/irq-generic.c
index 59963182ab..df57c99ae3 100644
--- a/bsps/shared/irq/irq-generic.c
+++ b/bsps/shared/irq/irq-generic.c
@@ -462,22 +462,3 @@ rtems_status_code rtems_interrupt_handler_remove(
{
return bsp_interrupt_handler_remove(vector, handler, arg);
}
-
-bool bsp_interrupt_handler_is_empty(rtems_vector_number vector)
-{
- rtems_vector_number index = 0;
- rtems_interrupt_entry *head = NULL;
- bool empty;
-
- /* For use in interrupts so no lock. */
-
- /* Get handler table index */
- index = bsp_interrupt_handler_index(vector);
-
- /* Get head entry of the handler list for the vector */
- head = _interrupt_handler_table [index];
-
- empty = bsp_interrupt_is_empty_handler_entry(head);
-
- return empty;
-}
--
2.26.2
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 15/42] bsps/irq: bsp_interrupt_vector_enable()
Return a status code for bsp_interrupt_vector_enable().
Update #3269.
---
bsps/arm/beagle/irq/irq.c | 3 ++-
bsps/arm/csb336/irq/irq.c | 4 +++-
bsps/arm/csb337/irq/irq.c | 3 ++-
bsps/arm/edb7312/irq/irq.c| 4 +++-
bsps/arm/gumstix/irq/irq.c| 3 ++-
bsps/arm/lpc24xx/irq/irq.c| 3 ++-
bsps/arm/lpc32xx/irq/irq.c| 4 +++-
bsps/arm/raspberrypi/irq/irq.c| 3 ++-
bsps/arm/rtl22xx/irq/irq.c| 3 ++-
bsps/arm/shared/irq/irq-armv7m.c | 3 ++-
bsps/arm/smdk2410/irq/irq.c | 3 ++-
bsps/arm/tms570/irq/irq.c | 3 ++-
bsps/i386/shared/irq/irq.c| 3 ++-
bsps/include/bsp/irq-generic.h| 16 ++--
bsps/lm32/shared/irq/irq.c| 3 ++-
bsps/m68k/genmcf548x/irq/irq.c| 4 +++-
bsps/mips/shared/irq/irq.c| 3 ++-
bsps/powerpc/gen5200/irq/irq.c| 4 +++-
bsps/powerpc/gen83xx/irq/irq.c| 4 +++-
bsps/powerpc/mpc55xxevb/start/irq.c | 3 ++-
bsps/powerpc/mpc8260ads/irq/irq.c | 4 +++-
bsps/powerpc/psim/irq/irq_init.c | 3 ++-
bsps/powerpc/qemuppc/irq/irq_init.c | 3 ++-
bsps/powerpc/qoriq/irq/irq.c | 5 +++--
bsps/powerpc/shared/irq/ppc-irq-generic.c | 3 ++-
bsps/powerpc/t32mppc/irq/irq.c| 3 ++-
bsps/powerpc/tqm8xx/irq/irq.c | 4 +++-
bsps/powerpc/virtex/irq/irq_init.c| 4 +++-
bsps/riscv/griscv/irq/irq.c | 3 ++-
bsps/riscv/riscv/irq/irq.c| 4 +++-
bsps/shared/dev/irq/arm-gicv2.c | 3 ++-
bsps/shared/dev/irq/arm-gicv3.c | 4 +++-
bsps/shared/irq/irq-default.c | 3 ++-
bsps/shared/irq/irq-enable-disable.c | 4 +---
bsps/sparc/leon3/start/eirq.c | 3 ++-
bsps/sparc/shared/irq/irq-shared.c| 3 ++-
bsps/x86_64/amd64/interrupts/idt.c| 3 ++-
37 files changed, 93 insertions(+), 45 deletions(-)
diff --git a/bsps/arm/beagle/irq/irq.c b/bsps/arm/beagle/irq/irq.c
index b0b7f77011..ff5ab4d15f 100644
--- a/bsps/arm/beagle/irq/irq.c
+++ b/bsps/arm/beagle/irq/irq.c
@@ -137,7 +137,7 @@ rtems_status_code bsp_interrupt_vector_is_enabled(
return RTEMS_UNSATISFIED;
}
-void bsp_interrupt_vector_enable(rtems_vector_number vector)
+rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
{
uint32_t mask, cur;
uint32_t mir_reg = omap_get_mir_reg(vector, );
@@ -147,6 +147,7 @@ void bsp_interrupt_vector_enable(rtems_vector_number vector)
cur = mmio_read(omap_intr.base + mir_reg);
mmio_write(omap_intr.base + mir_reg, cur & ~mask);
flush_data_cache();
+ return RTEMS_SUCCESSFUL;
}
void bsp_interrupt_vector_disable(rtems_vector_number vector)
diff --git a/bsps/arm/csb336/irq/irq.c b/bsps/arm/csb336/irq/irq.c
index c16a6d8773..4cdce1a207 100644
--- a/bsps/arm/csb336/irq/irq.c
+++ b/bsps/arm/csb336/irq/irq.c
@@ -68,12 +68,14 @@ rtems_status_code bsp_interrupt_vector_is_enabled(
return RTEMS_UNSATISFIED;
}
-void bsp_interrupt_vector_enable(rtems_vector_number vector)
+rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
if (vector < MC9328MXL_NUM_INTS)
MC9328MXL_AITC_INTENNUM = vector;
+
+ return RTEMS_SUCCESSFUL;
}
void bsp_interrupt_vector_disable(rtems_vector_number vector)
diff --git a/bsps/arm/csb337/irq/irq.c b/bsps/arm/csb337/irq/irq.c
index 98d775ce28..f2e2dbbed8 100644
--- a/bsps/arm/csb337/irq/irq.c
+++ b/bsps/arm/csb337/irq/irq.c
@@ -69,10 +69,11 @@ rtems_status_code bsp_interrupt_vector_is_enabled(
return RTEMS_UNSATISFIED;
}
-void bsp_interrupt_vector_enable(rtems_vector_number vector)
+rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
AIC_CTL_REG(AIC_IECR) = 1 << vector;
+ return RTEMS_SUCCESSFUL;
}
void bsp_interrupt_vector_disable(rtems_vector_number vector)
diff --git a/bsps/arm/edb7312/irq/irq.c b/bsps/arm/edb7312/irq/irq.c
index 9a64e069d0..820628a61d 100644
--- a/bsps/arm/edb7312/irq/irq.c
+++ b/bsps/arm/edb7312/irq/irq.c
@@ -69,7 +69,7 @@ rtems_status_code bsp_interrupt_vector_is_enabled(
return RTEMS_UNSATISFIED;
}
-void bsp_interrupt_vector_enable(rtems_vector_number vector)
+rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
@@ -93,6 +93,8 @@ void bsp_interrupt_vector_enable(rtems_vector_number vector)
/* interrupt managed by INTMR3 and INTSR3 */
*EP7312_INTMR3 |= (1 << (vector - 21));
}
+
+return RTEMS_SUCCESSFUL;
}
void bsp_interrupt_vector_disable(rtems_vector_number vector)
diff --git a/bsps/arm/gumstix/irq/irq.c b/bsps/arm/gumstix/irq/irq.c
index ff465c0308..da90bc77d9
[PATCH v3 19/42] bsps/irq: Implement new directives for GICv2/3
Update #3269.
---
bsps/aarch64/a53/include/bsp/irq.h | 2 +-
bsps/include/dev/irq/arm-gic-irq.h | 3 +
bsps/shared/dev/irq/arm-gicv2.c| 87 +++
bsps/shared/dev/irq/arm-gicv3.c| 129 +
4 files changed, 189 insertions(+), 32 deletions(-)
diff --git a/bsps/aarch64/a53/include/bsp/irq.h
b/bsps/aarch64/a53/include/bsp/irq.h
index b797408ca5..e0cc6a6026 100644
--- a/bsps/aarch64/a53/include/bsp/irq.h
+++ b/bsps/aarch64/a53/include/bsp/irq.h
@@ -48,7 +48,7 @@
extern "C" {
#endif /* __cplusplus */
-#define BSP_INTERRUPT_VECTOR_COUNT 1024
+#define BSP_INTERRUPT_VECTOR_COUNT 256
/* Interrupts vectors */
#define BSP_TIMER_VIRT_PPI 27
diff --git a/bsps/include/dev/irq/arm-gic-irq.h
b/bsps/include/dev/irq/arm-gic-irq.h
index 68e0247fd8..398fd8bceb 100644
--- a/bsps/include/dev/irq/arm-gic-irq.h
+++ b/bsps/include/dev/irq/arm-gic-irq.h
@@ -46,6 +46,9 @@ extern "C" {
#define ARM_GIC_IRQ_SGI_13 13
#define ARM_GIC_IRQ_SGI_14 14
#define ARM_GIC_IRQ_SGI_15 15
+#define ARM_GIC_IRQ_SGI_LAST 15
+
+#define ARM_GIC_IRQ_PPI_LAST 31
#define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE)
diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c
index 8372d0f191..eaae6124e8 100644
--- a/bsps/shared/dev/irq/arm-gicv2.c
+++ b/bsps/shared/dev/irq/arm-gicv2.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013, 2021 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -69,6 +69,32 @@ rtems_status_code bsp_interrupt_get_attributes(
rtems_interrupt_attributes *attributes
)
{
+ attributes->is_maskable = true;
+ attributes->maybe_enable = true;
+ attributes->maybe_disable = true;
+ attributes->can_raise = true;
+
+ if ( vector <= ARM_GIC_IRQ_SGI_LAST ) {
+/*
+ * It is implementation-defined whether implemented SGIs are permanently
+ * enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and
+ * GICD_ICENABLER0.
+ */
+attributes->can_raise_on = true;
+attributes->cleared_by_acknowledge = true;
+attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL;
+ } else {
+attributes->can_disable = true;
+attributes->can_clear = true;
+attributes->trigger_signal = RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL;
+
+if ( vector > ARM_GIC_IRQ_PPI_LAST ) {
+ /* SPI */
+ attributes->can_get_affinity = true;
+ attributes->can_set_affinity = true;
+}
+ }
+
return RTEMS_SUCCESSFUL;
}
@@ -77,16 +103,25 @@ rtems_status_code bsp_interrupt_is_pending(
bool *pending
)
{
- bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
- bsp_interrupt_assert(pending != NULL);
- *pending = false;
- return RTEMS_UNSATISFIED;
+ volatile gic_dist *dist = ARM_GIC_DIST;
+
+ *pending = gic_id_is_pending(dist, vector);
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
- return RTEMS_UNSATISFIED;
+
+ if (vector <= ARM_GIC_IRQ_SGI_LAST) {
+arm_gic_trigger_sgi(vector, 1U << _SMP_Get_current_processor());
+ } else {
+volatile gic_dist *dist = ARM_GIC_DIST;
+
+gic_id_set_pending(dist, vector);
+ }
+
+ return RTEMS_SUCCESSFUL;
}
#if defined(RTEMS_SMP)
@@ -95,15 +130,27 @@ rtems_status_code bsp_interrupt_raise_on(
uint32_tcpu_index
)
{
- bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
- return RTEMS_UNSATISFIED;
+ if (vector >= 16) {
+return RTEMS_UNSATISFIED;
+ }
+
+ arm_gic_trigger_sgi(vector, 1U << cpu_index);
+ return RTEMS_SUCCESSFUL;
}
#endif
rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
{
+ volatile gic_dist *dist = ARM_GIC_DIST;
+
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
- return RTEMS_UNSATISFIED;
+
+ if (vector <= ARM_GIC_IRQ_SGI_LAST) {
+return RTEMS_UNSATISFIED;
+ }
+
+ gic_id_clear_pending(dist, vector);
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_vector_is_enabled(
@@ -111,10 +158,13 @@ rtems_status_code bsp_interrupt_vector_is_enabled(
bool *enabled
)
{
+ volatile gic_dist *dist = ARM_GIC_DIST;
+
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
bsp_interrupt_assert(enabled != NULL);
- *enabled = false;
- return RTEMS_UNSATISFIED;
+
+ *enabled = gic_id_is_enabled(dist, vector);
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
@@ -207,8 +257,8 @@ BSP_START_TEXT_SECTION void
arm_gic_irq_initialize_secondary_cpu(void)
dist->icdigr[0] = 0x;
#endif
- /* Initialize Peripheral Private Interrupts (PPIs) */
- for (id = 0; id < 32; ++id) {
+ /* Initialize priority of SGIs and PPIs */
+ for (id = 0; id <= ARM_GIC_IRQ_PPI_LAST; ++id) {
gic_id_set_priority(dist, id, PRIORITY_DEFAULT);
[PATCH v3 32/42] validation: rtems_interrupt_vector_is_enabled()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
.../validation/tc-intr-vector-is-enabled.c| 627 ++
2 files changed, 628 insertions(+)
create mode 100644 testsuites/validation/tc-intr-vector-is-enabled.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 4e8ecfe1a0..0fbd4d808f 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -16,6 +16,7 @@ source:
- testsuites/validation/tc-barrier-release.c
- testsuites/validation/tc-barrier-wait.c
- testsuites/validation/tc-intr-get-attributes.c
+- testsuites/validation/tc-intr-vector-is-enabled.c
- testsuites/validation/tc-message-construct-errors.c
- testsuites/validation/tc-object.c
- testsuites/validation/tc-signal-catch.c
diff --git a/testsuites/validation/tc-intr-vector-is-enabled.c
b/testsuites/validation/tc-intr-vector-is-enabled.c
new file mode 100644
index 00..15f13a132b
--- /dev/null
+++ b/testsuites/validation/tc-intr-vector-is-enabled.c
@@ -0,0 +1,627 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqVectorIsEnabled
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqVectorIsEnabled \
+ * spec:/rtems/intr/req/vector-is-enabled
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqVectorIsEnabled_Pre_Vector_Valid,
+ RtemsIntrReqVectorIsEnabled_Pre_Vector_Invalid,
+ RtemsIntrReqVectorIsEnabled_Pre_Vector_NA
+} RtemsIntrReqVectorIsEnabled_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqVectorIsEnabled_Pre_Enabled_Obj,
+ RtemsIntrReqVectorIsEnabled_Pre_Enabled_Null,
+ RtemsIntrReqVectorIsEnabled_Pre_Enabled_NA
+} RtemsIntrReqVectorIsEnabled_Pre_Enabled;
+
+typedef enum {
+ RtemsIntrReqVectorIsEnabled_Pre_IsEnabled_Yes,
+ RtemsIntrReqVectorIsEnabled_Pre_IsEnabled_No,
+ RtemsIntrReqVectorIsEnabled_Pre_IsEnabled_NA
+} RtemsIntrReqVectorIsEnabled_Pre_IsEnabled;
+
+typedef enum {
+ RtemsIntrReqVectorIsEnabled_Post_Status_Ok,
+ RtemsIntrReqVectorIsEnabled_Post_Status_InvAddr,
+ RtemsIntrReqVectorIsEnabled_Post_Status_InvId,
+ RtemsIntrReqVectorIsEnabled_Post_Status_NA
+} RtemsIntrReqVectorIsEnabled_Post_Status;
+
+typedef enum {
+ RtemsIntrReqVectorIsEnabled_Post_IsEnabled_Nop,
+ RtemsIntrReqVectorIsEnabled_Post_IsEnabled_Yes,
+ RtemsIntrReqVectorIsEnabled_Post_IsEnabled_No,
+ RtemsIntrReqVectorIsEnabled_Post_IsEnabled_NA
+} RtemsIntrReqVectorIsEnabled_Post_IsEnabled;
+
+/**
+ * @brief Test context for spec:/rtems/intr/req/vector-is-enabled test case.
+ */
+typedef struct {
+ /**
+ * @brief If this member is true, then an interrupt occurred.
+ */
+ bool interrupt_occurred;
+
+ /**
+ * @brief This member
[PATCH v3 39/42] validation: Test rtems_interrupt_is_pending()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
testsuites/validation/tc-intr-is-pending.c| 629 ++
2 files changed, 630 insertions(+)
create mode 100644 testsuites/validation/tc-intr-is-pending.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 13e3856b69..a54308bc2a 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -19,6 +19,7 @@ source:
- testsuites/validation/tc-intr-entry-install.c
- testsuites/validation/tc-intr-entry-remove.c
- testsuites/validation/tc-intr-get-attributes.c
+- testsuites/validation/tc-intr-is-pending.c
- testsuites/validation/tc-intr-raise.c
- testsuites/validation/tc-intr-vector-disable.c
- testsuites/validation/tc-intr-vector-enable.c
diff --git a/testsuites/validation/tc-intr-is-pending.c
b/testsuites/validation/tc-intr-is-pending.c
new file mode 100644
index 00..9a81cb9c23
--- /dev/null
+++ b/testsuites/validation/tc-intr-is-pending.c
@@ -0,0 +1,629 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqIsPending
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqIsPending spec:/rtems/intr/req/is-pending
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqIsPending_Pre_Vector_Valid,
+ RtemsIntrReqIsPending_Pre_Vector_Invalid,
+ RtemsIntrReqIsPending_Pre_Vector_NA
+} RtemsIntrReqIsPending_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqIsPending_Pre_Pending_Obj,
+ RtemsIntrReqIsPending_Pre_Pending_Null,
+ RtemsIntrReqIsPending_Pre_Pending_NA
+} RtemsIntrReqIsPending_Pre_Pending;
+
+typedef enum {
+ RtemsIntrReqIsPending_Pre_IsPending_Yes,
+ RtemsIntrReqIsPending_Pre_IsPending_No,
+ RtemsIntrReqIsPending_Pre_IsPending_NA
+} RtemsIntrReqIsPending_Pre_IsPending;
+
+typedef enum {
+ RtemsIntrReqIsPending_Post_Status_Ok,
+ RtemsIntrReqIsPending_Post_Status_InvAddr,
+ RtemsIntrReqIsPending_Post_Status_InvId,
+ RtemsIntrReqIsPending_Post_Status_NA
+} RtemsIntrReqIsPending_Post_Status;
+
+typedef enum {
+ RtemsIntrReqIsPending_Post_IsPending_Nop,
+ RtemsIntrReqIsPending_Post_IsPending_Yes,
+ RtemsIntrReqIsPending_Post_IsPending_No,
+ RtemsIntrReqIsPending_Post_IsPending_NA
+} RtemsIntrReqIsPending_Post_IsPending;
+
+/**
+ * @brief Test context for spec:/rtems/intr/req/is-pending test case.
+ */
+typedef struct {
+ /**
+ * @brief This member contains the count of serviced interrupts.
+ */
+ volatile uint32_t interrupt_count;
+
+ /**
+ * @brief If this member is true, then the interrupt shall be cleared.
+ */
+ bool do_clear;
+
+ /**
+ * @brief This member contains the current vector number.
+ */
+ rtems_vector_number vector;
[PATCH v3 40/42] validation: Test rtems_interrupt_raise_on()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
testsuites/validation/tc-intr-raise-on.c | 709 ++
testsuites/validation/ts-default.h| 12 +-
testsuites/validation/ts-validation-0.c | 2 +-
4 files changed, 722 insertions(+), 2 deletions(-)
create mode 100644 testsuites/validation/tc-intr-raise-on.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index a54308bc2a..6f68727f01 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -21,6 +21,7 @@ source:
- testsuites/validation/tc-intr-get-attributes.c
- testsuites/validation/tc-intr-is-pending.c
- testsuites/validation/tc-intr-raise.c
+- testsuites/validation/tc-intr-raise-on.c
- testsuites/validation/tc-intr-vector-disable.c
- testsuites/validation/tc-intr-vector-enable.c
- testsuites/validation/tc-intr-vector-is-enabled.c
diff --git a/testsuites/validation/tc-intr-raise-on.c
b/testsuites/validation/tc-intr-raise-on.c
new file mode 100644
index 00..2b1692d602
--- /dev/null
+++ b/testsuites/validation/tc-intr-raise-on.c
@@ -0,0 +1,709 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqRaiseOn
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqRaiseOn spec:/rtems/intr/req/raise-on
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqRaiseOn_Pre_Vector_Valid,
+ RtemsIntrReqRaiseOn_Pre_Vector_Invalid,
+ RtemsIntrReqRaiseOn_Pre_Vector_NA
+} RtemsIntrReqRaiseOn_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqRaiseOn_Pre_CPU_Online,
+ RtemsIntrReqRaiseOn_Pre_CPU_NotOnline,
+ RtemsIntrReqRaiseOn_Pre_CPU_NotConf,
+ RtemsIntrReqRaiseOn_Pre_CPU_NA
+} RtemsIntrReqRaiseOn_Pre_CPU;
+
+typedef enum {
+ RtemsIntrReqRaiseOn_Pre_CanRaiseOn_Yes,
+ RtemsIntrReqRaiseOn_Pre_CanRaiseOn_No,
+ RtemsIntrReqRaiseOn_Pre_CanRaiseOn_NA
+} RtemsIntrReqRaiseOn_Pre_CanRaiseOn;
+
+typedef enum {
+ RtemsIntrReqRaiseOn_Post_Status_Ok,
+ RtemsIntrReqRaiseOn_Post_Status_InvId,
+ RtemsIntrReqRaiseOn_Post_Status_NotConf,
+ RtemsIntrReqRaiseOn_Post_Status_IncStat,
+ RtemsIntrReqRaiseOn_Post_Status_Unsat,
+ RtemsIntrReqRaiseOn_Post_Status_NA
+} RtemsIntrReqRaiseOn_Post_Status;
+
+typedef enum {
+ RtemsIntrReqRaiseOn_Post_Pending_Yes,
+ RtemsIntrReqRaiseOn_Post_Pending_No,
+ RtemsIntrReqRaiseOn_Post_Pending_NA
+} RtemsIntrReqRaiseOn_Post_Pending;
+
+/**
+ * @brief Test context for spec:/rtems/intr/req/raise-on test case.
+ */
+typedef struct {
+ /**
+ * @brief This member contains the count of serviced interrupts.
+ */
+ volatile uint32_t interrupt_count;
+
+ /**
+ * @brief If this member is true, then the interrupt shall be
[PATCH v3 31/42] validation: Test rtems_interrupt_get_attributes()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
.../validation/tc-intr-get-attributes.c | 440 ++
2 files changed, 441 insertions(+)
create mode 100644 testsuites/validation/tc-intr-get-attributes.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 653872320c..4e8ecfe1a0 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -15,6 +15,7 @@ source:
- testsuites/validation/tc-barrier-delete.c
- testsuites/validation/tc-barrier-release.c
- testsuites/validation/tc-barrier-wait.c
+- testsuites/validation/tc-intr-get-attributes.c
- testsuites/validation/tc-message-construct-errors.c
- testsuites/validation/tc-object.c
- testsuites/validation/tc-signal-catch.c
diff --git a/testsuites/validation/tc-intr-get-attributes.c
b/testsuites/validation/tc-intr-get-attributes.c
new file mode 100644
index 00..16860a08cd
--- /dev/null
+++ b/testsuites/validation/tc-intr-get-attributes.c
@@ -0,0 +1,440 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqGetAttributes
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqGetAttributes \
+ * spec:/rtems/intr/req/get-attributes
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqGetAttributes_Pre_Vector_Valid,
+ RtemsIntrReqGetAttributes_Pre_Vector_Invalid,
+ RtemsIntrReqGetAttributes_Pre_Vector_NA
+} RtemsIntrReqGetAttributes_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqGetAttributes_Pre_Attributes_Obj,
+ RtemsIntrReqGetAttributes_Pre_Attributes_Null,
+ RtemsIntrReqGetAttributes_Pre_Attributes_NA
+} RtemsIntrReqGetAttributes_Pre_Attributes;
+
+typedef enum {
+ RtemsIntrReqGetAttributes_Post_Status_Ok,
+ RtemsIntrReqGetAttributes_Post_Status_InvAddr,
+ RtemsIntrReqGetAttributes_Post_Status_InvId,
+ RtemsIntrReqGetAttributes_Post_Status_NA
+} RtemsIntrReqGetAttributes_Post_Status;
+
+typedef enum {
+ RtemsIntrReqGetAttributes_Post_Attributes_Nop,
+ RtemsIntrReqGetAttributes_Post_Attributes_Zero,
+ RtemsIntrReqGetAttributes_Post_Attributes_Set,
+ RtemsIntrReqGetAttributes_Post_Attributes_NA
+} RtemsIntrReqGetAttributes_Post_Attributes;
+
+/**
+ * @brief Test context for spec:/rtems/intr/req/get-attributes test case.
+ */
+typedef struct {
+ /**
+ * @brief This member provides the rtems_interrupt_attributes object.
+ */
+ rtems_interrupt_attributes attributes_obj;
+
+ /**
+ * @brief If this member is true, then the ``vector`` parameter shall be
+ * valid.
+ */
+ bool valid_vector;
+
+ /**
+ * @brief This member specifies if the ``attributes`` parameter value.
+ */
+ rtems_interrupt_attributes *attributes;;
+
+ /**
+ * @brief This member
[PATCH v3 35/42] validation: Test rtems_interrupt_entry_install()
Update #3269.
---
.../testsuites/validation/validation-0.yml|1 +
testsuites/validation/tc-intr-entry-install.c | 1364 +
2 files changed, 1365 insertions(+)
create mode 100644 testsuites/validation/tc-intr-entry-install.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 78633bebe5..c536779f2d 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -15,6 +15,7 @@ source:
- testsuites/validation/tc-barrier-delete.c
- testsuites/validation/tc-barrier-release.c
- testsuites/validation/tc-barrier-wait.c
+- testsuites/validation/tc-intr-entry-install.c
- testsuites/validation/tc-intr-get-attributes.c
- testsuites/validation/tc-intr-vector-disable.c
- testsuites/validation/tc-intr-vector-enable.c
diff --git a/testsuites/validation/tc-intr-entry-install.c
b/testsuites/validation/tc-intr-entry-install.c
new file mode 100644
index 00..20d06df997
--- /dev/null
+++ b/testsuites/validation/tc-intr-entry-install.c
@@ -0,0 +1,1364 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqEntryInstall
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqEntryInstall \
+ * spec:/rtems/intr/req/entry-install
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqEntryInstall_Pre_Vector_Valid,
+ RtemsIntrReqEntryInstall_Pre_Vector_Invalid,
+ RtemsIntrReqEntryInstall_Pre_Vector_NA
+} RtemsIntrReqEntryInstall_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqEntryInstall_Pre_Options_Unique,
+ RtemsIntrReqEntryInstall_Pre_Options_Shared,
+ RtemsIntrReqEntryInstall_Pre_Options_Replace,
+ RtemsIntrReqEntryInstall_Pre_Options_NA
+} RtemsIntrReqEntryInstall_Pre_Options;
+
+typedef enum {
+ RtemsIntrReqEntryInstall_Pre_Entry_Obj,
+ RtemsIntrReqEntryInstall_Pre_Entry_Null,
+ RtemsIntrReqEntryInstall_Pre_Entry_NA
+} RtemsIntrReqEntryInstall_Pre_Entry;
+
+typedef enum {
+ RtemsIntrReqEntryInstall_Pre_Routine_Valid,
+ RtemsIntrReqEntryInstall_Pre_Routine_Null,
+ RtemsIntrReqEntryInstall_Pre_Routine_NA
+} RtemsIntrReqEntryInstall_Pre_Routine;
+
+typedef enum {
+ RtemsIntrReqEntryInstall_Pre_Init_Yes,
+ RtemsIntrReqEntryInstall_Pre_Init_No,
+ RtemsIntrReqEntryInstall_Pre_Init_NA
+} RtemsIntrReqEntryInstall_Pre_Init;
+
+typedef enum {
+ RtemsIntrReqEntryInstall_Pre_ISR_Yes,
+ RtemsIntrReqEntryInstall_Pre_ISR_No,
+ RtemsIntrReqEntryInstall_Pre_ISR_NA
+} RtemsIntrReqEntryInstall_Pre_ISR;
+
+typedef enum {
+ RtemsIntrReqEntryInstall_Pre_CanEnable_Yes,
+ RtemsIntrReqEntryInstall_Pre_CanEnable_Maybe,
+ RtemsIntrReqEntryInstall_Pre_CanEnable_No,
+ RtemsIntrReqEntryInstall_Pre_CanEnable_NA
+} RtemsIntrReqEntryInstall_Pre_CanEnable;
+
[PATCH v3 13/42] bsps/irq: Add rtems_interrupt_get_attributes()
Add a default implementation which clears the attributes to zero and
just returns RTEMS_SUCCESSFUL for valid parameters.
Update #3269.
---
bsps/arm/beagle/irq/irq.c | 8 ++
bsps/arm/csb336/irq/irq.c | 8 ++
bsps/arm/csb337/irq/irq.c | 8 ++
bsps/arm/edb7312/irq/irq.c| 8 ++
bsps/arm/gumstix/irq/irq.c| 8 ++
bsps/arm/lpc24xx/irq/irq.c| 8 ++
bsps/arm/lpc32xx/irq/irq.c| 8 ++
bsps/arm/raspberrypi/irq/irq.c| 8 ++
bsps/arm/rtl22xx/irq/irq.c| 8 ++
bsps/arm/shared/irq/irq-armv7m.c | 8 ++
bsps/arm/smdk2410/irq/irq.c | 8 ++
bsps/arm/tms570/irq/irq.c | 8 ++
bsps/i386/shared/irq/irq.c| 8 ++
bsps/include/bsp/irq-generic.h| 17
bsps/lm32/shared/irq/irq.c| 8 ++
bsps/m68k/genmcf548x/irq/irq.c| 8 ++
bsps/mips/shared/irq/irq.c| 8 ++
bsps/powerpc/gen5200/irq/irq.c| 10 +--
bsps/powerpc/gen83xx/irq/irq.c| 10 +--
bsps/powerpc/mpc55xxevb/start/irq.c | 8 ++
bsps/powerpc/mpc8260ads/irq/irq.c | 8 ++
bsps/powerpc/psim/irq/irq_init.c | 8 ++
bsps/powerpc/qemuppc/irq/irq_init.c | 10 +--
bsps/powerpc/qoriq/irq/irq.c | 16 +++
bsps/powerpc/shared/irq/ppc-irq-generic.c | 8 ++
bsps/powerpc/t32mppc/irq/irq.c| 8 ++
bsps/powerpc/tqm8xx/irq/irq.c | 10 +--
bsps/powerpc/virtex/irq/irq_init.c| 10 +--
bsps/riscv/griscv/irq/irq.c | 8 ++
bsps/riscv/riscv/irq/irq.c| 8 ++
bsps/shared/dev/irq/arm-gicv2.c | 8 ++
bsps/shared/dev/irq/arm-gicv3.c | 8 ++
bsps/shared/irq/irq-default.c | 8 ++
bsps/shared/irq/irq-enable-disable.c | 33 +--
bsps/sparc/leon3/start/eirq.c | 8 ++
bsps/sparc/shared/irq/irq-shared.c| 8 ++
bsps/x86_64/amd64/interrupts/idt.c| 9 +++
37 files changed, 337 insertions(+), 12 deletions(-)
diff --git a/bsps/arm/beagle/irq/irq.c b/bsps/arm/beagle/irq/irq.c
index 4a89189a32..0285e46442 100644
--- a/bsps/arm/beagle/irq/irq.c
+++ b/bsps/arm/beagle/irq/irq.c
@@ -95,6 +95,14 @@ static uint32_t omap_get_mir_reg(rtems_vector_number vector,
uint32_t *const mas
return mir_reg;
}
+rtems_status_code bsp_interrupt_get_attributes(
+ rtems_vector_number vector,
+ rtems_interrupt_attributes *attributes
+)
+{
+ return RTEMS_SUCCESSFUL;
+}
+
rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
diff --git a/bsps/arm/csb336/irq/irq.c b/bsps/arm/csb336/irq/irq.c
index 3c9e6a7ea7..85137195ef 100644
--- a/bsps/arm/csb336/irq/irq.c
+++ b/bsps/arm/csb336/irq/irq.c
@@ -26,6 +26,14 @@ void bsp_interrupt_dispatch(void)
bsp_interrupt_handler_dispatch(vector);
}
+rtems_status_code bsp_interrupt_get_attributes(
+ rtems_vector_number vector,
+ rtems_interrupt_attributes *attributes
+)
+{
+ return RTEMS_SUCCESSFUL;
+}
+
rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
diff --git a/bsps/arm/csb337/irq/irq.c b/bsps/arm/csb337/irq/irq.c
index d097a92259..e06c9f20b6 100644
--- a/bsps/arm/csb337/irq/irq.c
+++ b/bsps/arm/csb337/irq/irq.c
@@ -27,6 +27,14 @@ void bsp_interrupt_dispatch(void)
AIC_CTL_REG(AIC_EOICR) = 0;
}
+rtems_status_code bsp_interrupt_get_attributes(
+ rtems_vector_number vector,
+ rtems_interrupt_attributes *attributes
+)
+{
+ return RTEMS_SUCCESSFUL;
+}
+
rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
diff --git a/bsps/arm/edb7312/irq/irq.c b/bsps/arm/edb7312/irq/irq.c
index 0522e40bd8..c1d166049b 100644
--- a/bsps/arm/edb7312/irq/irq.c
+++ b/bsps/arm/edb7312/irq/irq.c
@@ -27,6 +27,14 @@ void edb7312_interrupt_dispatch(rtems_vector_number vector)
bsp_interrupt_handler_dispatch(vector);
}
+rtems_status_code bsp_interrupt_get_attributes(
+ rtems_vector_number vector,
+ rtems_interrupt_attributes *attributes
+)
+{
+ return RTEMS_SUCCESSFUL;
+}
+
rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
diff --git a/bsps/arm/gumstix/irq/irq.c b/bsps/arm/gumstix/irq/irq.c
index 0e7340dab2..8d66edaaf6 100644
--- a/bsps/arm/gumstix/irq/irq.c
+++ b/bsps/arm/gumstix/irq/irq.c
@@ -24,6 +24,14 @@ void bsp_interrupt_dispatch(void)
bsp_interrupt_handler_dispatch(vector);
}
+rtems_status_code bsp_interrupt_get_attributes(
+ rtems_vector_number vector,
+ rtems_interrupt_attributes *attributes
+)
+{
[PATCH v3 37/42] validation: Test rtems_interrupt_raise()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
testsuites/validation/tc-intr-raise.c | 576 ++
2 files changed, 577 insertions(+)
create mode 100644 testsuites/validation/tc-intr-raise.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 08ef145c82..4e79290d6b 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -18,6 +18,7 @@ source:
- testsuites/validation/tc-intr-entry-install.c
- testsuites/validation/tc-intr-entry-remove.c
- testsuites/validation/tc-intr-get-attributes.c
+- testsuites/validation/tc-intr-raise.c
- testsuites/validation/tc-intr-vector-disable.c
- testsuites/validation/tc-intr-vector-enable.c
- testsuites/validation/tc-intr-vector-is-enabled.c
diff --git a/testsuites/validation/tc-intr-raise.c
b/testsuites/validation/tc-intr-raise.c
new file mode 100644
index 00..1fea6ad867
--- /dev/null
+++ b/testsuites/validation/tc-intr-raise.c
@@ -0,0 +1,576 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqRaise
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqRaise spec:/rtems/intr/req/raise
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqRaise_Pre_Vector_Valid,
+ RtemsIntrReqRaise_Pre_Vector_Invalid,
+ RtemsIntrReqRaise_Pre_Vector_NA
+} RtemsIntrReqRaise_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqRaise_Pre_CanRaise_Yes,
+ RtemsIntrReqRaise_Pre_CanRaise_No,
+ RtemsIntrReqRaise_Pre_CanRaise_NA
+} RtemsIntrReqRaise_Pre_CanRaise;
+
+typedef enum {
+ RtemsIntrReqRaise_Post_Status_Ok,
+ RtemsIntrReqRaise_Post_Status_InvId,
+ RtemsIntrReqRaise_Post_Status_Unsat,
+ RtemsIntrReqRaise_Post_Status_NA
+} RtemsIntrReqRaise_Post_Status;
+
+typedef enum {
+ RtemsIntrReqRaise_Post_Pending_Yes,
+ RtemsIntrReqRaise_Post_Pending_No,
+ RtemsIntrReqRaise_Post_Pending_NA
+} RtemsIntrReqRaise_Post_Pending;
+
+/**
+ * @brief Test context for spec:/rtems/intr/req/raise test case.
+ */
+typedef struct {
+ /**
+ * @brief This member contains the count of serviced interrupts.
+ */
+ volatile uint32_t interrupt_count;
+
+ /**
+ * @brief If this member is true, then the interrupt shall be cleared.
+ */
+ bool do_clear;
+
+ /**
+ * @brief This member contains the current vector number.
+ */
+ rtems_vector_number vector;
+
+ /**
+ * @brief If this member is true, then the ``vector`` parameter shall be
+ * valid.
+ */
+ bool valid_vector;
+
+ /**
+ * @brief This member contains the return value of the
+ * rtems_interrupt_raise() call.
+ */
+ rtems_status_code status;
+
+ /**
+ * @brief This member defines the pre-condition states
[PATCH v3 30/42] validation: GetTestableInterruptVector()
Update #3269.
---
testsuites/validation/tx-interrupt.c | 47
testsuites/validation/tx-support.h | 2 ++
2 files changed, 49 insertions(+)
diff --git a/testsuites/validation/tx-interrupt.c
b/testsuites/validation/tx-interrupt.c
index 0ff5ec017f..e75c7a2aa0 100644
--- a/testsuites/validation/tx-interrupt.c
+++ b/testsuites/validation/tx-interrupt.c
@@ -69,6 +69,53 @@ rtems_vector_number GetValidInterruptVectorNumber(
return vector;
}
+rtems_vector_number GetTestableInterruptVector( void )
+{
+ rtems_vector_number vector;
+
+ for ( vector = 0; vector < BSP_INTERRUPT_VECTOR_COUNT; ++vector ) {
+rtems_status_code sc;
+rtems_interrupt_attributes attr;
+
+sc = rtems_interrupt_get_attributes( vector, );
+
+if ( sc != RTEMS_SUCCESSFUL ) {
+ continue;
+}
+
+if ( !attr.is_maskable ) {
+ continue;
+}
+
+if ( HasInterruptVectorEntriesInstalled( vector ) ) {
+ continue;
+}
+
+if ( attr.can_enable && attr.can_disable ) {
+ break;
+}
+
+if (
+ attr.maybe_enable && attr.maybe_disable &&
+ !attr.can_be_triggered_by_message &&
+ attr.trigger_signal == RTEMS_INTERRUPT_NO_SIGNAL
+) {
+ rtems_status_code sc;
+ bool enabled;
+
+ (void) rtems_interrupt_vector_enable( vector );
+ sc = rtems_interrupt_vector_is_enabled( vector, );
+
+ if ( sc == RTEMS_SUCCESSFUL && enabled ) {
+(void) rtems_interrupt_vector_disable( vector );
+break;
+ }
+}
+ }
+
+ return vector;
+}
+
static void HasInstalled(
void *arg,
const char *info,
diff --git a/testsuites/validation/tx-support.h
b/testsuites/validation/tx-support.h
index 20006f5dd8..b0e466fda1 100644
--- a/testsuites/validation/tx-support.h
+++ b/testsuites/validation/tx-support.h
@@ -118,6 +118,8 @@ rtems_vector_number GetValidInterruptVectorNumber(
const rtems_interrupt_attributes *required
);
+rtems_vector_number GetTestableInterruptVector( void );
+
bool HasInterruptVectorEntriesInstalled( rtems_vector_number vector );
/** @} */
--
2.26.2
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 33/42] validation: Test rtems_interrupt_vector_enable()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
testsuites/validation/tc-intr-vector-enable.c | 638 ++
2 files changed, 639 insertions(+)
create mode 100644 testsuites/validation/tc-intr-vector-enable.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 0fbd4d808f..36d2a0f388 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -16,6 +16,7 @@ source:
- testsuites/validation/tc-barrier-release.c
- testsuites/validation/tc-barrier-wait.c
- testsuites/validation/tc-intr-get-attributes.c
+- testsuites/validation/tc-intr-vector-enable.c
- testsuites/validation/tc-intr-vector-is-enabled.c
- testsuites/validation/tc-message-construct-errors.c
- testsuites/validation/tc-object.c
diff --git a/testsuites/validation/tc-intr-vector-enable.c
b/testsuites/validation/tc-intr-vector-enable.c
new file mode 100644
index 00..76e1bd0191
--- /dev/null
+++ b/testsuites/validation/tc-intr-vector-enable.c
@@ -0,0 +1,638 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqVectorEnable
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqVectorEnable \
+ * spec:/rtems/intr/req/vector-enable
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqVectorEnable_Pre_Vector_Valid,
+ RtemsIntrReqVectorEnable_Pre_Vector_Invalid,
+ RtemsIntrReqVectorEnable_Pre_Vector_NA
+} RtemsIntrReqVectorEnable_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqVectorEnable_Pre_IsEnabled_Yes,
+ RtemsIntrReqVectorEnable_Pre_IsEnabled_No,
+ RtemsIntrReqVectorEnable_Pre_IsEnabled_NA
+} RtemsIntrReqVectorEnable_Pre_IsEnabled;
+
+typedef enum {
+ RtemsIntrReqVectorEnable_Pre_CanEnable_Yes,
+ RtemsIntrReqVectorEnable_Pre_CanEnable_Maybe,
+ RtemsIntrReqVectorEnable_Pre_CanEnable_No,
+ RtemsIntrReqVectorEnable_Pre_CanEnable_NA
+} RtemsIntrReqVectorEnable_Pre_CanEnable;
+
+typedef enum {
+ RtemsIntrReqVectorEnable_Post_Status_Ok,
+ RtemsIntrReqVectorEnable_Post_Status_InvId,
+ RtemsIntrReqVectorEnable_Post_Status_Unsat,
+ RtemsIntrReqVectorEnable_Post_Status_NA
+} RtemsIntrReqVectorEnable_Post_Status;
+
+typedef enum {
+ RtemsIntrReqVectorEnable_Post_IsEnabled_Nop,
+ RtemsIntrReqVectorEnable_Post_IsEnabled_Yes,
+ RtemsIntrReqVectorEnable_Post_IsEnabled_Maybe,
+ RtemsIntrReqVectorEnable_Post_IsEnabled_NA
+} RtemsIntrReqVectorEnable_Post_IsEnabled;
+
+/**
+ * @brief Test context for spec:/rtems/intr/req/vector-enable test case.
+ */
+typedef struct {
+ /**
+ * @brief If this member is true, then an interrupt occurred.
+ */
+ bool interrupt_occurred;
+
+ /**
+ * @brief This member contains the current vector number.
+
[PATCH v3 22/42] bsps/irq: Use rtems_interrupt_entry
Update #3269.
---
bsps/include/bsp/irq-generic.h| 15 +++
bsps/shared/irq/irq-generic.c | 24
bsps/shared/irq/irq-handler-iterate.c | 2 +-
3 files changed, 16 insertions(+), 25 deletions(-)
diff --git a/bsps/include/bsp/irq-generic.h b/bsps/include/bsp/irq-generic.h
index 1ff1f61dd2..0f9bd5765b 100644
--- a/bsps/include/bsp/irq-generic.h
+++ b/bsps/include/bsp/irq-generic.h
@@ -83,16 +83,7 @@ extern "C" {
#define bsp_interrupt_assert(e) _Assert(e)
-struct bsp_interrupt_handler_entry {
- rtems_interrupt_handler handler;
- void *arg;
- const char *info;
- struct bsp_interrupt_handler_entry *next;
-};
-
-typedef struct bsp_interrupt_handler_entry bsp_interrupt_handler_entry;
-
-extern bsp_interrupt_handler_entry bsp_interrupt_handler_table [];
+extern rtems_interrupt_entry bsp_interrupt_handler_table [];
#ifdef BSP_INTERRUPT_USE_INDEX_TABLE
#if BSP_INTERRUPT_HANDLER_TABLE_SIZE < 0x100
@@ -386,7 +377,7 @@ static inline void bsp_interrupt_handler_dispatch_unchecked(
rtems_vector_number vector
)
{
- const bsp_interrupt_handler_entry *e;
+ const rtems_interrupt_entry *e;
e = _interrupt_handler_table[ bsp_interrupt_handler_index( vector ) ];
@@ -494,7 +485,7 @@ void bsp_interrupt_handler_empty( void *arg );
* @brief Checks if a handler entry is empty.
*/
static inline bool bsp_interrupt_is_empty_handler_entry(
- const bsp_interrupt_handler_entry *entry
+ const rtems_interrupt_entry *entry
)
{
return entry->handler == bsp_interrupt_handler_empty;
diff --git a/bsps/shared/irq/irq-generic.c b/bsps/shared/irq/irq-generic.c
index 81da647228..a7e8c1163f 100644
--- a/bsps/shared/irq/irq-generic.c
+++ b/bsps/shared/irq/irq-generic.c
@@ -46,7 +46,7 @@
[BSP_INTERRUPT_VECTOR_COUNT];
#endif
-bsp_interrupt_handler_entry bsp_interrupt_handler_table
+rtems_interrupt_entry bsp_interrupt_handler_table
[BSP_INTERRUPT_HANDLER_TABLE_SIZE];
/* The last entry indicates if everything is initialized */
@@ -87,7 +87,7 @@ static inline void bsp_interrupt_set_initialized(void)
}
static inline void bsp_interrupt_clear_handler_entry(
- bsp_interrupt_handler_entry *e,
+ rtems_interrupt_entry *e,
rtems_vector_number vector
)
{
@@ -108,7 +108,7 @@ static inline bool bsp_interrupt_allocate_handler_index(
/* The first entry will remain empty */
for (i = 1; i < BSP_INTERRUPT_HANDLER_TABLE_SIZE; ++i) {
- const bsp_interrupt_handler_entry *e = _interrupt_handler_table [i];
+ const rtems_interrupt_entry *e = _interrupt_handler_table [i];
if (bsp_interrupt_is_empty_handler_entry(e)) {
*index = i;
return true;
@@ -164,7 +164,7 @@ static rtems_status_code bsp_interrupt_handler_install(
{
rtems_interrupt_level level;
rtems_vector_number index = 0;
- bsp_interrupt_handler_entry *head = NULL;
+ rtems_interrupt_entry *head = NULL;
bool enable_vector = false;
bool replace = RTEMS_INTERRUPT_IS_REPLACE(options);
@@ -218,9 +218,9 @@ static rtems_status_code bsp_interrupt_handler_install(
/* This is the first handler so enable the vector later */
enable_vector = true;
} else {
-bsp_interrupt_handler_entry *current = head;
-bsp_interrupt_handler_entry *tail = NULL;
-bsp_interrupt_handler_entry *match = NULL;
+rtems_interrupt_entry *current = head;
+rtems_interrupt_entry *tail = NULL;
+rtems_interrupt_entry *match = NULL;
/* Ensure that a unique handler remains unique */
if (
@@ -327,10 +327,10 @@ static rtems_status_code bsp_interrupt_handler_remove(
{
rtems_interrupt_level level;
rtems_vector_number index = 0;
- bsp_interrupt_handler_entry *head = NULL;
- bsp_interrupt_handler_entry *current = NULL;
- bsp_interrupt_handler_entry *previous = NULL;
- bsp_interrupt_handler_entry *match = NULL;
+ rtems_interrupt_entry *head = NULL;
+ rtems_interrupt_entry *current = NULL;
+ rtems_interrupt_entry *previous = NULL;
+ rtems_interrupt_entry *match = NULL;
/* Check parameters and system state */
if (!bsp_interrupt_is_initialized()) {
@@ -454,7 +454,7 @@ rtems_status_code rtems_interrupt_handler_remove(
bool bsp_interrupt_handler_is_empty(rtems_vector_number vector)
{
rtems_vector_number index = 0;
- bsp_interrupt_handler_entry *head = NULL;
+ rtems_interrupt_entry *head = NULL;
bool empty;
/* For use in interrupts so no lock. */
diff --git a/bsps/shared/irq/irq-handler-iterate.c
b/bsps/shared/irq/irq-handler-iterate.c
index 8adbdb4679..3c642b075e 100644
--- a/bsps/shared/irq/irq-handler-iterate.c
+++ b/bsps/shared/irq/irq-handler-iterate.c
@@ -52,7 +52,7 @@ static rtems_status_code bsp_interrupt_handler_iterate(
void *arg
)
{
- bsp_interrupt_handler_entry *current = NULL;
+ rtems_interrupt_entry *current = NULL;
rtems_option options = 0;
rtems_vector_number index = 0;
--
2.26.2
___
devel mailing list
devel@rtems.org
[PATCH v3 05/42] rtems: Generate
Use which just provides the data types and avoid a
dependency on which contains the full chain
implementation.
Change license to BSD-2-Clause according to file histories and
documentation re-licensing agreement.
Update #3269.
Update #3899.
Update #3993.
---
cpukit/include/rtems/irq-extension.h | 1830 +++---
1 file changed, 1354 insertions(+), 476 deletions(-)
diff --git a/cpukit/include/rtems/irq-extension.h
b/cpukit/include/rtems/irq-extension.h
index 915be09e2b..5f24fb502e 100644
--- a/cpukit/include/rtems/irq-extension.h
+++ b/cpukit/include/rtems/irq-extension.h
@@ -1,294 +1,566 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/**
* @file
*
- * @ingroup rtems_interrupt_extension
+ * @ingroup RTEMSAPIClassicIntr
*
- * @brief Header file for the Interrupt Manager Extension.
+ * @brief This header file defines the Interrupt Manager Extension API.
+ */
+
+/*
+ * Copyright (C) 2008, 2021 embedded brains GmbH
(http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*/
/*
- * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette.
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
*
- * Copyright (C) 2008, 2020 embedded brains GmbH
(http://www.embedded-brains.de)
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
*
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
+ * https://docs.rtems.org
*/
-#ifndef RTEMS_IRQ_EXTENSION_H
-#define RTEMS_IRQ_EXTENSION_H
+/* Generated from spec:/rtems/intr/if/header-2 */
-#include
-#include
+#ifndef _RTEMS_IRQ_EXTENSION_H
+#define _RTEMS_IRQ_EXTENSION_H
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
#ifdef __cplusplus
extern "C" {
-#endif /* __cplusplus */
+#endif
+
+/* Generated from spec:/rtems/intr/if/handler */
/**
- * @defgroup rtems_interrupt_extension Interrupt Manager Extension
- *
* @ingroup RTEMSAPIClassicIntr
*
- * In addition to the Classic API interrupt handler with a handle are
- * supported. You can also install multiple shared handler for one interrupt
- * vector.
+ * @brief Interrupt handler routines shall have this type.
*/
-/**@{**/
+typedef void ( *rtems_interrupt_handler )( void * );
+
+/* Generated from spec:/rtems/intr/if/per-handler-routine */
/**
- * @brief Makes the interrupt handler unique. Prevents other handler from
- * using the same interrupt vector.
+ * @ingroup RTEMSAPIClassicIntr
+ *
+ * @brief Visitor routines invoked by rtems_interrupt_handler_iterate() shall
+ * have this type.
*/
-#define RTEMS_INTERRUPT_UNIQUE ((rtems_option) 0x0001)
+typedef void ( *rtems_interrupt_per_handler_routine )(
+ void *,
+ const char *,
+ rtems_option,
+ rtems_interrupt_handler,
+ void *
+);
+
+/* Generated from spec:/rtems/intr/if/shared */
/**
- * @brief Allows that this interrupt handler may share a common interrupt
- * vector with other handler.
+ * @ingroup RTEMSAPIClassicIntr
+ *
+ * @brief This interrupt handler install option allows that the interrupt
+ * handler may share the interrupt vector with other handler.
*/
-#define
[PATCH v3 21/42] rtems: Add rtems_interrupt_entry_install()
Add RTEMS_INTERRUPT_ENTRY_INITIALIZER(),
rtems_interrupt_entry_initialize(), and
rtems_interrupt_entry_remove(). This allows to install interrupt
handlers using user-provided storage as an alternative to
rtems_interrupt_handler_install() which has to allocate memory.
Update #3269.
---
cpukit/include/rtems/irq-extension.h | 237 +++
1 file changed, 237 insertions(+)
diff --git a/cpukit/include/rtems/irq-extension.h
b/cpukit/include/rtems/irq-extension.h
index 0a26ef959c..e45ea43004 100644
--- a/cpukit/include/rtems/irq-extension.h
+++ b/cpukit/include/rtems/irq-extension.h
@@ -166,6 +166,243 @@ typedef void ( *rtems_interrupt_per_handler_routine )(
#define RTEMS_INTERRUPT_IS_REPLACE( _options ) \
( ( _options ) & RTEMS_INTERRUPT_REPLACE )
+/* Generated from spec:/rtems/intr/if/entry */
+
+/**
+ * @ingroup RTEMSAPIClassicIntr
+ *
+ * @brief This structure represents an interrupt entry.
+ *
+ * @par Notes
+ * This structure shall be treated as an opaque data type from the API point of
+ * view. Members shall not be accessed directly. An entry may be initialized
+ * by RTEMS_INTERRUPT_ENTRY_INITIALIZER() or
+ * rtems_interrupt_entry_initialize(). It may be installed for an interrupt
+ * vector with rtems_interrupt_entry_install() and removed from an interrupt
+ * vector by rtems_interrupt_entry_remove().
+ */
+typedef struct rtems_interrupt_entry {
+ /**
+ * @brief This member is the interrupt handler routine.
+ */
+ rtems_interrupt_handler handler;
+
+ /**
+ * @brief This member is the interrupt handler argument.
+ */
+ void *arg;
+
+ /**
+ * @brief This member is the reference to the next entry or NULL.
+ */
+ struct rtems_interrupt_entry *next;
+
+ /**
+ * @brief This member is the descriptive information of the entry.
+ */
+ const char *info;
+} rtems_interrupt_entry;
+
+/* Generated from spec:/rtems/intr/if/entry-initializer */
+
+/**
+ * @ingroup RTEMSAPIClassicIntr
+ *
+ * @brief Statically initializes an interrupt entry object.
+ *
+ * @param _routine is the interrupt handler routine for the entry.
+ *
+ * @param _arg is the interrupt handler argument for the entry.
+ *
+ * @param _info is the descriptive information for the entry.
+ *
+ * @par Notes
+ * Alternatively, rtems_interrupt_entry_initialize() may be used to dynamically
+ * initialize an interrupt entry.
+ */
+#define RTEMS_INTERRUPT_ENTRY_INITIALIZER( _routine, _arg, _info ) \
+ { _routine, _arg, NULL, _info }
+
+/* Generated from spec:/rtems/intr/if/entry-initialize */
+
+/**
+ * @ingroup RTEMSAPIClassicIntr
+ *
+ * @brief Initializes the interrupt entry.
+ *
+ * @param[out] entry is the interrupt entry to initialize.
+ *
+ * @param routine is the interrupt handler routine for the entry.
+ *
+ * @param arg is the interrupt handler argument for the entry.
+ *
+ * @param info is the descriptive information for the entry.
+ *
+ * @par Notes
+ * Alternatively, RTEMS_INTERRUPT_ENTRY_INITIALIZER() may be used to statically
+ * initialize an interrupt entry.
+ *
+ * @par Constraints
+ * @parblock
+ * The following constraints apply to this directive:
+ *
+ * * The directive may be called from within any runtime context.
+ *
+ * * The directive will not cause the calling task to be preempted.
+ * @endparblock
+ */
+static inline void rtems_interrupt_entry_initialize(
+ rtems_interrupt_entry *entry,
+ rtems_interrupt_handler routine,
+ void *arg,
+ const char *info
+)
+{
+ entry->handler = routine;
+ entry->arg = arg;
+ entry->next = NULL;
+ entry->info = info;
+}
+
+/* Generated from spec:/rtems/intr/if/entry-install */
+
+/**
+ * @ingroup RTEMSAPIClassicIntr
+ *
+ * @brief Installs the interrupt entry at the interrupt vector.
+ *
+ * @param vector is the interrupt vector number.
+ *
+ * @param options is the interrupt entry install option set.
+ *
+ * @param entry is the interrupt entry to install.
+ *
+ * One of the following mutually exclusive options
+ *
+ * * #RTEMS_INTERRUPT_UNIQUE, and
+ *
+ * * #RTEMS_INTERRUPT_SHARED
+ *
+ * shall be set in the ``options`` parameter.
+ *
+ * The handler routine of the entry specified by ``entry`` will be called with
+ * the handler argument of the entry when dispatched. The order in which
+ * shared interrupt handlers are dispatched for one vector is defined by the
+ * installation order. The first installed handler is dispatched first.
+ *
+ * If the option #RTEMS_INTERRUPT_UNIQUE is set, then it will be ensured that
+ * the handler will be the only one for the interrupt vector.
+ *
+ * If the option #RTEMS_INTERRUPT_SHARED is set, then multiple handlers may be
+ * installed for the interrupt vector.
+ *
+ * @retval ::RTEMS_SUCCESSFUL The requested operation was successful.
+ *
+ * @retval ::RTEMS_INVALID_ADDRESS The ``entry`` parameter was NULL.
+ *
+ * @retval ::RTEMS_INCORRECT_STATE The service was not initialized.
+ *
+ * @retval ::RTEMS_INVALID_ADDRESS The handler routine of the entry was NULL.
+
[PATCH v3 20/42] sparc/irq: Implement new interrupt directives
Update #3269.
---
bsps/sparc/erc32/include/bsp/irq.h | 3 +-
bsps/sparc/erc32/include/erc32.h | 12 -
bsps/sparc/leon2/include/bsp/irq.h | 3 +-
bsps/sparc/leon2/include/leon.h| 16 +-
bsps/sparc/leon3/start/eirq.c | 87 +++---
bsps/sparc/shared/irq/irq-shared.c | 48 ++---
6 files changed, 148 insertions(+), 21 deletions(-)
diff --git a/bsps/sparc/erc32/include/bsp/irq.h
b/bsps/sparc/erc32/include/bsp/irq.h
index a61f51d6b6..83b383ba7a 100644
--- a/bsps/sparc/erc32/include/bsp/irq.h
+++ b/bsps/sparc/erc32/include/bsp/irq.h
@@ -23,8 +23,7 @@
#define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */
#define BSP_INTERRUPT_VECTOR_COUNT (BSP_INTERRUPT_VECTOR_MAX_STD + 1)
-/* No extra check is needed */
-#undef BSP_INTERRUPT_CUSTOM_VALID_VECTOR
+#define BSP_INTERRUPT_CUSTOM_VALID_VECTOR
RTEMS_INLINE_ROUTINE rtems_status_code bsp_interrupt_set_affinity(
rtems_vector_number vector,
diff --git a/bsps/sparc/erc32/include/erc32.h b/bsps/sparc/erc32/include/erc32.h
index a677b13d25..f9cdbc960a 100644
--- a/bsps/sparc/erc32/include/erc32.h
+++ b/bsps/sparc/erc32/include/erc32.h
@@ -352,7 +352,7 @@ static __inline__ int bsp_irq_fixup(int irq)
\
_level = sparc_disable_interrupts(); \
ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x8; \
-ERC32_MEC.Interrupt_Force = (1 << (_source)); \
+ERC32_MEC.Interrupt_Force |= (1 << (_source)); \
sparc_enable_interrupts( _level ); \
} while (0)
@@ -406,7 +406,17 @@ static __inline__ int bsp_irq_fixup(int irq)
/* Make all SPARC BSPs have common macros for interrupt handling on local CPU
*/
#define BSP_Clear_interrupt(_source) ERC32_Clear_interrupt(_source)
#define BSP_Force_interrupt(_source) ERC32_Force_interrupt(_source)
+#define BSP_Clear_forced_interrupt( _source ) \
+ do { \
+uint32_t _level; \
+\
+_level = sparc_disable_interrupts(); \
+ ERC32_MEC.Interrupt_Force &= ~(1 << (_source)); \
+sparc_enable_interrupts( _level ); \
+ } while (0)
#define BSP_Is_interrupt_pending(_source) ERC32_Is_interrupt_pending(_source)
+#define BSP_Is_interrupt_forced(_source) \
+ (ERC32_MEC.Interrupt_Force & (1 << (_source)))
#define BSP_Is_interrupt_masked(_source) ERC32_Is_interrupt_masked(_source)
#define BSP_Unmask_interrupt(_source) ERC32_Unmask_interrupt(_source)
#define BSP_Mask_interrupt(_source) ERC32_Mask_interrupt(_source)
diff --git a/bsps/sparc/leon2/include/bsp/irq.h
b/bsps/sparc/leon2/include/bsp/irq.h
index 5f2359014a..a4ce3c55ff 100644
--- a/bsps/sparc/leon2/include/bsp/irq.h
+++ b/bsps/sparc/leon2/include/bsp/irq.h
@@ -21,7 +21,6 @@
#define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */
#define BSP_INTERRUPT_VECTOR_COUNT (BSP_INTERRUPT_VECTOR_MAX_STD + 1)
-/* No extra check is needed */
-#undef BSP_INTERRUPT_CUSTOM_VALID_VECTOR
+#define BSP_INTERRUPT_CUSTOM_VALID_VECTOR
#endif /* LIBBSP_LEON2_IRQ_CONFIG_H */
diff --git a/bsps/sparc/leon2/include/leon.h b/bsps/sparc/leon2/include/leon.h
index fc90e1f7e6..11196aee6d 100644
--- a/bsps/sparc/leon2/include/leon.h
+++ b/bsps/sparc/leon2/include/leon.h
@@ -295,7 +295,11 @@ static __inline__ int bsp_irq_fixup(int irq)
#define LEON_Force_interrupt( _source ) \
do { \
-LEON_REG.Interrupt_Force = (1 << (_source)); \
+uint32_t _level; \
+\
+_level = sparc_disable_interrupts(); \
+ LEON_REG.Interrupt_Force |= (1 << (_source)); \
+sparc_enable_interrupts( _level ); \
} while (0)
#define LEON_Is_interrupt_pending( _source ) \
@@ -348,7 +352,17 @@ static __inline__ int bsp_irq_fixup(int irq)
/* Make all SPARC BSPs have common macros for interrupt handling */
#define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source)
#define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source)
+#define BSP_Clear_forced_interrupt( _source ) \
+ do { \
+uint32_t _level; \
+\
+_level = sparc_disable_interrupts(); \
+ LEON_REG.Interrupt_Force &= ~(1 << (_source)); \
+sparc_enable_interrupts( _level ); \
+ } while (0)
#define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source)
+#define BSP_Is_interrupt_forced(_source) \
+ (LEON_REG.Interrupt_Force & (1 << (_source)))
#define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source)
#define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source)
#define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source)
diff --git a/bsps/sparc/leon3/start/eirq.c b/bsps/sparc/leon3/start/eirq.c
index 5519d6efe7..80c0efd3fa 100644
--- a/bsps/sparc/leon3/start/eirq.c
+++ b/bsps/sparc/leon3/start/eirq.c
@@ -66,6 +66,20 @@ rtems_status_code bsp_interrupt_get_attributes(
rtems_interrupt_attributes *attributes
)
{
+ bool is_standard_interrupt;
+
+ is_standard_interrupt = (vector <= BSP_INTERRUPT_VECTOR_MAX_STD);
+ attributes->is_maskable = (vector != 15);
+ attributes->can_enable = true;
+ attributes->maybe_enable = true;
+
[PATCH v3 23/42] bsps/irq: Add bsp_interrupt_check_and_lock()
Return RTEMS_INCORRECT_STATE instead of RTEMS_INTERNAL_ERROR in case the
interrupt support is not initialized. This is similar to
rtems_timer_server_fire_after() for example.
Update #3269.
---
bsps/include/bsp/irq-generic.h| 38 -
bsps/shared/irq/irq-generic.c | 60 ---
bsps/shared/irq/irq-handler-iterate.c | 51 +++
3 files changed, 86 insertions(+), 63 deletions(-)
diff --git a/bsps/include/bsp/irq-generic.h b/bsps/include/bsp/irq-generic.h
index 0f9bd5765b..e9cb0b4bb9 100644
--- a/bsps/include/bsp/irq-generic.h
+++ b/bsps/include/bsp/irq-generic.h
@@ -428,12 +428,46 @@ bool bsp_interrupt_handler_is_empty(rtems_vector_number
vector);
/** @} */
-/* For internal use only */
+/**
+ * @brief Acquires the interrupt support lock.
+ *
+ * The interrupt support lock is a mutex. The mutex is only acquired if the
+ * system is the ::SYSTEM_STATE_UP state.
+ */
void bsp_interrupt_lock(void);
-/* For internal use only */
+/**
+ * @brief Releases the interrupt support lock.
+ *
+ * The mutex is only released if the system is the ::SYSTEM_STATE_UP state.
+ */
void bsp_interrupt_unlock(void);
+/**
+ * @brief Checks the vector and routine. When the checks were successful, the
+ * interrupt support lock will be obtained.
+ *
+ * @param vector is the interrupt vector number to check.
+ *
+ * @param routine is the routine to check.
+ *
+ * @retval ::RTEMS_SUCCESSFUL The requested operation was successful.
+ *
+ * @retval ::RTEMS_INCORRECT_STATE The interrupt support was not initialized.
+ *
+ * @retval ::RTEMS_CALLED_FROM_ISR The function was called from within
+ * interrupt context.
+ *
+ * @retval ::RTEMS_INVALID_ADDRESS The ``routine`` parameter was NULL.
+ *
+ * @retval ::RTEMS_INVALID_ID There was no interrupt vector associated with the
+ * number specified by ``vector``.
+ */
+rtems_status_code bsp_interrupt_check_and_lock(
+ rtems_vector_number vector,
+ rtems_interrupt_handler handler
+);
+
/**
* @brief This table contains a bit map which indicates if an entry is unique
* or shared.
diff --git a/bsps/shared/irq/irq-generic.c b/bsps/shared/irq/irq-generic.c
index a7e8c1163f..59963182ab 100644
--- a/bsps/shared/irq/irq-generic.c
+++ b/bsps/shared/irq/irq-generic.c
@@ -122,6 +122,32 @@ static inline bool bsp_interrupt_allocate_handler_index(
#endif
}
+rtems_status_code bsp_interrupt_check_and_lock(
+ rtems_vector_number vector,
+ rtems_interrupt_handler handler
+)
+{
+ if ( !bsp_interrupt_is_initialized() ) {
+return RTEMS_INCORRECT_STATE;
+ }
+
+ if ( handler == NULL ) {
+return RTEMS_INVALID_ADDRESS;
+ }
+
+ if ( !bsp_interrupt_is_valid_vector( vector ) ) {
+return RTEMS_INVALID_ID;
+ }
+
+ if ( rtems_interrupt_is_in_progress() ) {
+return RTEMS_CALLED_FROM_ISR;
+ }
+
+ bsp_interrupt_lock();
+
+ return RTEMS_SUCCESSFUL;
+}
+
void bsp_interrupt_initialize(void)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
@@ -162,25 +188,18 @@ static rtems_status_code bsp_interrupt_handler_install(
void *arg
)
{
+ rtems_status_code sc;
rtems_interrupt_level level;
rtems_vector_number index = 0;
rtems_interrupt_entry *head = NULL;
bool enable_vector = false;
bool replace = RTEMS_INTERRUPT_IS_REPLACE(options);
- /* Check parameters and system state */
- if (!bsp_interrupt_is_initialized()) {
-return RTEMS_INTERNAL_ERROR;
- } else if (!bsp_interrupt_is_valid_vector(vector)) {
-return RTEMS_INVALID_ID;
- } else if (handler == NULL) {
-return RTEMS_INVALID_ADDRESS;
- } else if (rtems_interrupt_is_in_progress()) {
-return RTEMS_CALLED_FROM_ISR;
- }
+ sc = bsp_interrupt_check_and_lock( vector, handler );
- /* Lock */
- bsp_interrupt_lock();
+ if ( sc != RTEMS_SUCCESSFUL ) {
+return sc;
+ }
/* Get handler table index */
index = bsp_interrupt_handler_index(vector);
@@ -325,6 +344,7 @@ static rtems_status_code bsp_interrupt_handler_remove(
void *arg
)
{
+ rtems_status_code sc;
rtems_interrupt_level level;
rtems_vector_number index = 0;
rtems_interrupt_entry *head = NULL;
@@ -332,19 +352,11 @@ static rtems_status_code bsp_interrupt_handler_remove(
rtems_interrupt_entry *previous = NULL;
rtems_interrupt_entry *match = NULL;
- /* Check parameters and system state */
- if (!bsp_interrupt_is_initialized()) {
-return RTEMS_INTERNAL_ERROR;
- } else if (!bsp_interrupt_is_valid_vector(vector)) {
-return RTEMS_INVALID_ID;
- } else if (handler == NULL) {
-return RTEMS_INVALID_ADDRESS;
- } else if (rtems_interrupt_is_in_progress()) {
-return RTEMS_CALLED_FROM_ISR;
- }
+ sc = bsp_interrupt_check_and_lock( vector, handler );
- /* Lock */
- bsp_interrupt_lock();
+ if ( sc != RTEMS_SUCCESSFUL ) {
+return sc;
+ }
/* Get handler table index */
index = bsp_interrupt_handler_index(vector);
diff --git a/bsps/shared/irq/irq-handler-iterate.c
b/bsps/shared/irq/irq-handler-iterate.c
index
[PATCH v3 25/42] bsps/irq: Add rtems_interrupt_entry_install()
Add rtems_interrupt_entry_remove(). Split up irq-generic.c into several files.
In particular, place all functions which use dynamic memory into their own
file.
Add optional macros to let the BSP customize the vector installation after
installing the first entry and the vector removal before removing the last
entry:
* bsp_interrupt_vector_install()
* bsp_interrupt_vector_remove()
Use these new customization options in the m68k/genmcf548x BSP so re-use the
generic interrupt controller support.
Update #3269.
---
bsps/i386/shared/irq/irq.c | 8 +-
bsps/include/bsp/irq-generic.h | 214 ++--
bsps/m68k/genmcf548x/include/bsp/irq.h | 8 +
bsps/m68k/genmcf548x/irq/irq.c | 140 +-
bsps/shared/irq-default-sources.am | 3 +
bsps/shared/irq-sources.am | 3 +
bsps/shared/irq/irq-entry-remove.c | 115 +
bsps/shared/irq/irq-generic.c| 486 ++-
bsps/shared/irq/irq-handler-install.c| 114 +
bsps/shared/irq/irq-handler-iterate.c| 21 +-
bsps/shared/irq/irq-handler-remove.c | 80 +++
c/src/lib/libbsp/m68k/genmcf548x/Makefile.am | 10 +-
c/src/lib/libbsp/powerpc/ss555/Makefile.am | 3 +
spec/build/bsps/m68k/genmcf548x/grp.yml | 2 +
spec/build/bsps/m68k/genmcf548x/obj.yml | 9 -
spec/build/bsps/objirq.yml | 3 +
spec/build/bsps/powerpc/ss555/bspss555.yml | 3 +
17 files changed, 681 insertions(+), 541 deletions(-)
create mode 100644 bsps/shared/irq/irq-entry-remove.c
create mode 100644 bsps/shared/irq/irq-handler-install.c
create mode 100644 bsps/shared/irq/irq-handler-remove.c
diff --git a/bsps/i386/shared/irq/irq.c b/bsps/i386/shared/irq/irq.c
index 3ba1051f8f..e6994d49c7 100644
--- a/bsps/i386/shared/irq/irq.c
+++ b/bsps/i386/shared/irq/irq.c
@@ -353,13 +353,7 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
static bool bsp_interrupt_handler_is_empty(rtems_vector_number vector)
{
- rtems_vector_number index;
- rtems_interrupt_entry *head;
-
- index = bsp_interrupt_handler_index(vector);
- head = _interrupt_handler_table[index];
-
- return bsp_interrupt_is_empty_handler_entry(head);
+ return bsp_interrupt_entry_load_first(vector) == NULL;
}
/*
diff --git a/bsps/include/bsp/irq-generic.h b/bsps/include/bsp/irq-generic.h
index 12e8f9155b..e27c1b230c 100644
--- a/bsps/include/bsp/irq-generic.h
+++ b/bsps/include/bsp/irq-generic.h
@@ -12,7 +12,7 @@
/*
* Copyright (C) 2016 Chris Johns
*
- * Copyright (C) 2008, 2017 embedded brains GmbH
(http://www.embedded-brains.de)
+ * Copyright (C) 2008, 2021 embedded brains GmbH
(http://www.embedded-brains.de)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -70,20 +70,13 @@ extern "C" {
#define BSP_INTERRUPT_HANDLER_TABLE_SIZE BSP_INTERRUPT_VECTOR_COUNT
#endif
-/* Internal macros for SMP support, do not use externally */
-#ifdef RTEMS_SMP
- #define bsp_interrupt_disable(level) do { (void) level; } while (0)
- #define bsp_interrupt_enable(level) do { } while (0)
- #define bsp_interrupt_fence(order) _Atomic_Fence(order)
-#else
- #define bsp_interrupt_disable(level) rtems_interrupt_disable(level)
- #define bsp_interrupt_enable(level) rtems_interrupt_enable(level)
- #define bsp_interrupt_fence(order) do { } while (0)
-#endif
-
#define bsp_interrupt_assert(e) _Assert(e)
-extern rtems_interrupt_entry bsp_interrupt_handler_table [];
+/**
+ * @brief Each member of this table references the first installed entry at the
+ * corresponding interrupt vector or is NULL.
+ */
+extern rtems_interrupt_entry *bsp_interrupt_handler_table[];
#ifdef BSP_INTERRUPT_USE_INDEX_TABLE
#if BSP_INTERRUPT_HANDLER_TABLE_SIZE < 0x100
@@ -141,6 +134,12 @@ static inline rtems_vector_number
bsp_interrupt_handler_index(
* - bsp_interrupt_vector_disable()
* - bsp_interrupt_handler_default()
*
+ * Optionally, the BSP may define the following macros to customize the vector
+ * installation after installing the first entry and the vector removal before
+ * removing the last entry:
+ * - bsp_interrupt_vector_install()
+ * - bsp_interrupt_vector_remove()
+ *
* The following now deprecated functions are provided for backward
* compatibility:
* - BSP_get_current_rtems_irq_handler()
@@ -362,14 +361,114 @@ rtems_status_code bsp_interrupt_raise_on(
*/
rtems_status_code bsp_interrupt_clear( rtems_vector_number vector );
+#if defined(RTEMS_SMP)
+/**
+ * @brief Handles a spurious interrupt.
+ *
+ * @param vector is the vector number.
+ */
+void bsp_interrupt_spurious( rtems_vector_number vector );
+#endif
+
+/**
+ * @brief Loads the interrupt entry with atomic acquire semantic.
+ *
+ * @param ptr is the pointer to an ::rtems_interrupt_entry pointer.
+ *
+ * @return Returns the pointer value.
+ */
+static inline rtems_interrupt_entry
[PATCH v3 11/42] bsps/irq: Add rtems_interrupt_vector_is_enabled()
Add a default implementation which just returns RTEMS_UNSATISFIED for
valid parameters.
Update #3269.
---
bsps/arm/beagle/irq/irq.c | 11 +++
bsps/arm/csb336/irq/irq.c | 11 +++
bsps/arm/csb337/irq/irq.c | 11 +++
bsps/arm/edb7312/irq/irq.c| 11 +++
bsps/arm/gumstix/irq/irq.c| 11 +++
bsps/arm/lpc24xx/irq/irq.c| 11 +++
bsps/arm/lpc32xx/irq/irq.c| 11 +++
bsps/arm/raspberrypi/irq/irq.c| 11 +++
bsps/arm/rtl22xx/irq/irq.c| 11 +++
bsps/arm/shared/irq/irq-armv7m.c | 11 +++
bsps/arm/smdk2410/irq/irq.c | 11 +++
bsps/arm/tms570/irq/irq.c | 11 +++
bsps/i386/shared/irq/irq.c| 11 +++
bsps/include/bsp/irq-generic.h| 23 +++
bsps/lm32/shared/irq/irq.c| 11 +++
bsps/m68k/genmcf548x/irq/irq.c| 11 +++
bsps/mips/shared/irq/irq.c| 11 +++
bsps/powerpc/gen5200/irq/irq.c| 11 +++
bsps/powerpc/gen83xx/irq/irq.c| 11 +++
bsps/powerpc/mpc55xxevb/start/irq.c | 11 +++
bsps/powerpc/mpc8260ads/irq/irq.c | 11 +++
bsps/powerpc/psim/irq/irq_init.c | 11 +++
bsps/powerpc/qemuppc/irq/irq_init.c | 11 +++
bsps/powerpc/qoriq/irq/irq.c | 22 ++
bsps/powerpc/shared/irq/ppc-irq-generic.c | 11 +++
bsps/powerpc/t32mppc/irq/irq.c| 11 +++
bsps/powerpc/tqm8xx/irq/irq.c | 11 +++
bsps/powerpc/virtex/irq/irq_init.c| 11 +++
bsps/riscv/griscv/irq/irq.c | 11 +++
bsps/riscv/riscv/irq/irq.c| 11 +++
bsps/shared/dev/irq/arm-gicv2.c | 11 +++
bsps/shared/dev/irq/arm-gicv3.c | 11 +++
bsps/shared/irq/irq-default.c | 11 +++
bsps/shared/irq/irq-enable-disable.c | 19 ++-
bsps/sparc/leon3/start/eirq.c | 11 +++
bsps/sparc/shared/irq/irq-shared.c| 11 +++
bsps/x86_64/amd64/interrupts/idt.c| 11 +++
37 files changed, 437 insertions(+), 1 deletion(-)
diff --git a/bsps/arm/beagle/irq/irq.c b/bsps/arm/beagle/irq/irq.c
index 8e9294cae9..d0a07d1937 100644
--- a/bsps/arm/beagle/irq/irq.c
+++ b/bsps/arm/beagle/irq/irq.c
@@ -95,6 +95,17 @@ static uint32_t omap_get_mir_reg(rtems_vector_number vector,
uint32_t *const mas
return mir_reg;
}
+rtems_status_code bsp_interrupt_vector_is_enabled(
+ rtems_vector_number vector,
+ bool *enabled
+)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ bsp_interrupt_assert(enabled != NULL);
+ *enabled = false;
+ return RTEMS_UNSATISFIED;
+}
+
void bsp_interrupt_vector_enable(rtems_vector_number vector)
{
uint32_t mask, cur;
diff --git a/bsps/arm/csb336/irq/irq.c b/bsps/arm/csb336/irq/irq.c
index e5887b9717..80914fe28f 100644
--- a/bsps/arm/csb336/irq/irq.c
+++ b/bsps/arm/csb336/irq/irq.c
@@ -26,6 +26,17 @@ void bsp_interrupt_dispatch(void)
bsp_interrupt_handler_dispatch(vector);
}
+rtems_status_code bsp_interrupt_vector_is_enabled(
+ rtems_vector_number vector,
+ bool *enabled
+)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ bsp_interrupt_assert(enabled != NULL);
+ *enabled = false;
+ return RTEMS_UNSATISFIED;
+}
+
void bsp_interrupt_vector_enable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
diff --git a/bsps/arm/csb337/irq/irq.c b/bsps/arm/csb337/irq/irq.c
index 95e93845b9..5276374a1e 100644
--- a/bsps/arm/csb337/irq/irq.c
+++ b/bsps/arm/csb337/irq/irq.c
@@ -27,6 +27,17 @@ void bsp_interrupt_dispatch(void)
AIC_CTL_REG(AIC_EOICR) = 0;
}
+rtems_status_code bsp_interrupt_vector_is_enabled(
+ rtems_vector_number vector,
+ bool *enabled
+)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ bsp_interrupt_assert(enabled != NULL);
+ *enabled = false;
+ return RTEMS_UNSATISFIED;
+}
+
void bsp_interrupt_vector_enable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
diff --git a/bsps/arm/edb7312/irq/irq.c b/bsps/arm/edb7312/irq/irq.c
index 1d9151a1bd..d11cbf78c3 100644
--- a/bsps/arm/edb7312/irq/irq.c
+++ b/bsps/arm/edb7312/irq/irq.c
@@ -27,6 +27,17 @@ void edb7312_interrupt_dispatch(rtems_vector_number vector)
bsp_interrupt_handler_dispatch(vector);
}
+rtems_status_code bsp_interrupt_vector_is_enabled(
+ rtems_vector_number vector,
+ bool *enabled
+)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ bsp_interrupt_assert(enabled != NULL);
+ *enabled = false;
+ return RTEMS_UNSATISFIED;
+}
+
[PATCH v3 36/42] validation: Test rtems_interrupt_entry_remove()
Update #3269.
---
.../testsuites/validation/validation-0.yml|1 +
testsuites/validation/tc-intr-entry-remove.c | 1432 +
2 files changed, 1433 insertions(+)
create mode 100644 testsuites/validation/tc-intr-entry-remove.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index c536779f2d..08ef145c82 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -16,6 +16,7 @@ source:
- testsuites/validation/tc-barrier-release.c
- testsuites/validation/tc-barrier-wait.c
- testsuites/validation/tc-intr-entry-install.c
+- testsuites/validation/tc-intr-entry-remove.c
- testsuites/validation/tc-intr-get-attributes.c
- testsuites/validation/tc-intr-vector-disable.c
- testsuites/validation/tc-intr-vector-enable.c
diff --git a/testsuites/validation/tc-intr-entry-remove.c
b/testsuites/validation/tc-intr-entry-remove.c
new file mode 100644
index 00..64f6e46de7
--- /dev/null
+++ b/testsuites/validation/tc-intr-entry-remove.c
@@ -0,0 +1,1432 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqEntryRemove
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqEntryRemove \
+ * spec:/rtems/intr/req/entry-remove
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_Vector_Valid,
+ RtemsIntrReqEntryRemove_Pre_Vector_Invalid,
+ RtemsIntrReqEntryRemove_Pre_Vector_NA
+} RtemsIntrReqEntryRemove_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_Entry_Obj,
+ RtemsIntrReqEntryRemove_Pre_Entry_Null,
+ RtemsIntrReqEntryRemove_Pre_Entry_NA
+} RtemsIntrReqEntryRemove_Pre_Entry;
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_Routine_Valid,
+ RtemsIntrReqEntryRemove_Pre_Routine_Null,
+ RtemsIntrReqEntryRemove_Pre_Routine_NA
+} RtemsIntrReqEntryRemove_Pre_Routine;
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_EntryObj_Installed,
+ RtemsIntrReqEntryRemove_Pre_EntryObj_Match,
+ RtemsIntrReqEntryRemove_Pre_EntryObj_NoMatch,
+ RtemsIntrReqEntryRemove_Pre_EntryObj_NA
+} RtemsIntrReqEntryRemove_Pre_EntryObj;
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_Init_Yes,
+ RtemsIntrReqEntryRemove_Pre_Init_No,
+ RtemsIntrReqEntryRemove_Pre_Init_NA
+} RtemsIntrReqEntryRemove_Pre_Init;
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_ISR_Yes,
+ RtemsIntrReqEntryRemove_Pre_ISR_No,
+ RtemsIntrReqEntryRemove_Pre_ISR_NA
+} RtemsIntrReqEntryRemove_Pre_ISR;
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_CanDisable_Yes,
+ RtemsIntrReqEntryRemove_Pre_CanDisable_Maybe,
+ RtemsIntrReqEntryRemove_Pre_CanDisable_No,
+ RtemsIntrReqEntryRemove_Pre_CanDisable_NA
+} RtemsIntrReqEntryRemove_Pre_CanDisable;
+
+typedef enum {
+
[PATCH v3 18/42] bsps/irq: bsp_interrupt_set_affinity()
Return a status code for bsp_interrupt_set_affinity().
Update #3269.
---
bsps/include/dev/irq/arm-gic-irq.h | 2 +-
bsps/powerpc/qoriq/include/bsp/irq.h | 2 +-
bsps/powerpc/qoriq/irq/irq.c | 5 +++--
bsps/powerpc/t32mppc/include/bsp/irq.h | 3 ++-
bsps/riscv/griscv/include/bsp/irq.h| 2 +-
bsps/riscv/griscv/irq/irq.c| 4 +++-
bsps/riscv/riscv/include/bsp/irq.h | 2 +-
bsps/riscv/riscv/irq/irq.c | 8 +---
bsps/shared/dev/irq/arm-gicv2.c| 3 ++-
bsps/shared/dev/irq/arm-gicv3.c| 3 ++-
bsps/shared/irq/irq-affinity.c | 5 +++--
bsps/sparc/erc32/include/bsp/irq.h | 3 ++-
bsps/sparc/leon3/include/bsp/irq.h | 2 +-
bsps/sparc/leon3/start/eirq.c | 3 ++-
14 files changed, 29 insertions(+), 18 deletions(-)
diff --git a/bsps/include/dev/irq/arm-gic-irq.h
b/bsps/include/dev/irq/arm-gic-irq.h
index 730d792ce4..68e0247fd8 100644
--- a/bsps/include/dev/irq/arm-gic-irq.h
+++ b/bsps/include/dev/irq/arm-gic-irq.h
@@ -69,7 +69,7 @@ rtems_status_code arm_gic_irq_get_group(
gic_group *group
);
-void bsp_interrupt_set_affinity(
+rtems_status_code bsp_interrupt_set_affinity(
rtems_vector_number vector,
const Processor_mask *affinity
);
diff --git a/bsps/powerpc/qoriq/include/bsp/irq.h
b/bsps/powerpc/qoriq/include/bsp/irq.h
index 6618d54190..cd642fa00b 100644
--- a/bsps/powerpc/qoriq/include/bsp/irq.h
+++ b/bsps/powerpc/qoriq/include/bsp/irq.h
@@ -380,7 +380,7 @@ rtems_status_code qoriq_pic_set_priority(
int *old_priority
);
-void bsp_interrupt_set_affinity(
+rtems_status_code bsp_interrupt_set_affinity(
rtems_vector_number vector,
const Processor_mask *affinity
);
diff --git a/bsps/powerpc/qoriq/irq/irq.c b/bsps/powerpc/qoriq/irq/irq.c
index f335aa0602..68292ec81b 100644
--- a/bsps/powerpc/qoriq/irq/irq.c
+++ b/bsps/powerpc/qoriq/irq/irq.c
@@ -45,7 +45,7 @@ RTEMS_INTERRUPT_LOCK_DEFINE(static, lock, "QorIQ IRQ")
#ifdef QORIQ_IS_HYPERVISOR_GUEST
-void bsp_interrupt_set_affinity(
+rtems_status_code bsp_interrupt_set_affinity(
rtems_vector_number vector,
const Processor_mask *affinity
)
@@ -62,6 +62,7 @@ void bsp_interrupt_set_affinity(
ev_int_get_config(vector, , , );
ev_int_set_config(vector, config, priority, new_destination);
rtems_interrupt_lock_release(, _context);
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_get_affinity(
@@ -314,7 +315,7 @@ rtems_status_code qoriq_pic_set_priority(
return sc;
}
-void bsp_interrupt_set_affinity(
+rtems_status_code bsp_interrupt_set_affinity(
rtems_vector_number vector,
const Processor_mask *affinity
)
diff --git a/bsps/powerpc/t32mppc/include/bsp/irq.h
b/bsps/powerpc/t32mppc/include/bsp/irq.h
index c0c374edae..dc3f55b296 100644
--- a/bsps/powerpc/t32mppc/include/bsp/irq.h
+++ b/bsps/powerpc/t32mppc/include/bsp/irq.h
@@ -26,13 +26,14 @@ extern "C" {
#define BSP_INTERRUPT_VECTOR_COUNT 1
-RTEMS_INLINE_ROUTINE void bsp_interrupt_set_affinity(
+RTEMS_INLINE_ROUTINE rtems_status_code bsp_interrupt_set_affinity(
rtems_vector_number vector,
const Processor_mask *affinity
)
{
(void) vector;
(void) affinity;
+ return RTEMS_SUCCESSFUL;
}
RTEMS_INLINE_ROUTINE rtems_status_code bsp_interrupt_get_affinity(
diff --git a/bsps/riscv/griscv/include/bsp/irq.h
b/bsps/riscv/griscv/include/bsp/irq.h
index 1df7b4b584..634fee4d01 100644
--- a/bsps/riscv/griscv/include/bsp/irq.h
+++ b/bsps/riscv/griscv/include/bsp/irq.h
@@ -56,7 +56,7 @@
#define BSP_INTERRUPT_VECTOR_COUNT
RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS)
-void bsp_interrupt_set_affinity(
+rtems_status_code bsp_interrupt_set_affinity(
rtems_vector_number vector,
const Processor_mask *affinity
);
diff --git a/bsps/riscv/griscv/irq/irq.c b/bsps/riscv/griscv/irq/irq.c
index 5c52238753..3f1c75dc8e 100644
--- a/bsps/riscv/griscv/irq/irq.c
+++ b/bsps/riscv/griscv/irq/irq.c
@@ -175,7 +175,7 @@ rtems_status_code bsp_interrupt_get_affinity(
return RTEMS_SUCCESSFUL;
}
-void bsp_interrupt_set_affinity(
+rtems_status_code bsp_interrupt_set_affinity(
rtems_vector_number vector,
const Processor_mask *affinity
)
@@ -196,4 +196,6 @@ void bsp_interrupt_set_affinity(
} else {
GRLIB_Disable_interrupt_broadcast(vector);
}
+
+ return RTEMS_SUCCESSFUL;
}
diff --git a/bsps/riscv/riscv/include/bsp/irq.h
b/bsps/riscv/riscv/include/bsp/irq.h
index 03fe8ced3a..1b67c4e046 100644
--- a/bsps/riscv/riscv/include/bsp/irq.h
+++ b/bsps/riscv/riscv/include/bsp/irq.h
@@ -56,7 +56,7 @@
#define BSP_INTERRUPT_VECTOR_COUNT
RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS)
-void bsp_interrupt_set_affinity(
+rtems_status_code bsp_interrupt_set_affinity(
rtems_vector_number vector,
const Processor_mask *affinity
);
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c
index 098a482cd4..eff0de7156 100644
--- a/bsps/riscv/riscv/irq/irq.c
+++
[PATCH v3 38/42] validation: Test rtems_interrupt_clear()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
testsuites/validation/tc-intr-clear.c | 586 ++
2 files changed, 587 insertions(+)
create mode 100644 testsuites/validation/tc-intr-clear.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 4e79290d6b..13e3856b69 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -15,6 +15,7 @@ source:
- testsuites/validation/tc-barrier-delete.c
- testsuites/validation/tc-barrier-release.c
- testsuites/validation/tc-barrier-wait.c
+- testsuites/validation/tc-intr-clear.c
- testsuites/validation/tc-intr-entry-install.c
- testsuites/validation/tc-intr-entry-remove.c
- testsuites/validation/tc-intr-get-attributes.c
diff --git a/testsuites/validation/tc-intr-clear.c
b/testsuites/validation/tc-intr-clear.c
new file mode 100644
index 00..8482d8ceff
--- /dev/null
+++ b/testsuites/validation/tc-intr-clear.c
@@ -0,0 +1,586 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqClear
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqClear spec:/rtems/intr/req/clear
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqClear_Pre_Vector_Valid,
+ RtemsIntrReqClear_Pre_Vector_Invalid,
+ RtemsIntrReqClear_Pre_Vector_NA
+} RtemsIntrReqClear_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqClear_Pre_CanClear_Yes,
+ RtemsIntrReqClear_Pre_CanClear_No,
+ RtemsIntrReqClear_Pre_CanClear_NA
+} RtemsIntrReqClear_Pre_CanClear;
+
+typedef enum {
+ RtemsIntrReqClear_Post_Status_Ok,
+ RtemsIntrReqClear_Post_Status_InvId,
+ RtemsIntrReqClear_Post_Status_Unsat,
+ RtemsIntrReqClear_Post_Status_NA
+} RtemsIntrReqClear_Post_Status;
+
+typedef enum {
+ RtemsIntrReqClear_Post_Cleared_Yes,
+ RtemsIntrReqClear_Post_Cleared_No,
+ RtemsIntrReqClear_Post_Cleared_NA
+} RtemsIntrReqClear_Post_Cleared;
+
+/**
+ * @brief Test context for spec:/rtems/intr/req/clear test case.
+ */
+typedef struct {
+ /**
+ * @brief This member contains the count of serviced interrupts.
+ */
+ volatile uint32_t interrupt_count;
+
+ /**
+ * @brief If this member is true, then the interrupt shall be cleared.
+ */
+ bool do_clear;
+
+ /**
+ * @brief This member contains the current vector number.
+ */
+ rtems_vector_number vector;
+
+ /**
+ * @brief If this member is true, then the ``vector`` parameter shall be
+ * valid.
+ */
+ bool valid_vector;
+
+ /**
+ * @brief This member contains the return value of the
+ * rtems_interrupt_clear() call.
+ */
+ rtems_status_code status;
+
+ /**
+ * @brief This member defines the pre-condition states for the next
[PATCH v3 26/42] bsp/raspberrypi: Add interrupt get/set affinity
Add default implementations for bsp_interrupt_get_affinity() and
bsp_interrupt_set_affinity() which are required to link all tests in SMP
configurations.
Update #3269.
---
bsps/arm/raspberrypi/include/bsp/irq.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/bsps/arm/raspberrypi/include/bsp/irq.h
b/bsps/arm/raspberrypi/include/bsp/irq.h
index a363e7ce90..6801b01d84 100644
--- a/bsps/arm/raspberrypi/include/bsp/irq.h
+++ b/bsps/arm/raspberrypi/include/bsp/irq.h
@@ -25,6 +25,10 @@
#include
#include
+#if defined(RTEMS_SMP)
+#include
+#endif
+
/**
* @defgroup raspberrypi_interrupt Interrrupt Support
*
@@ -74,5 +78,27 @@
#define BSP_IRQ_COUNT (BCM2835_INTC_TOTAL_IRQ)
+#if defined(RTEMS_SMP)
+static inline rtems_status_code bsp_interrupt_set_affinity(
+ rtems_vector_number vector,
+ const Processor_mask *affinity
+)
+{
+ (void) vector;
+ (void) affinity;
+ return RTEMS_UNSATISFIED;
+}
+
+static inline rtems_status_code bsp_interrupt_get_affinity(
+ rtems_vector_number vector,
+ Processor_mask *affinity
+)
+{
+ (void) vector;
+ _Processor_mask_From_index( affinity, 0 );
+ return RTEMS_UNSATISFIED;
+}
+#endif
+
#endif /* ASM */
#endif /* LIBBSP_ARM_RASPBERRYPI_IRQ_H */
--
2.26.2
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 10/42] rtems: Add RTEMS_FATAL_SOURCE_SPURIOUS_INTERRUPT
Add RTEMS_FATAL_SOURCE_SPURIOUS_INTERRUPT as the fatal source for
spurious interrupts. Use the interrupt vector number of the spurious
interrupt for the fatal code.
Update #3269.
---
bsps/shared/irq/irq-default-handler.c | 12 +---
cpukit/include/rtems/score/interr.h | 7 +++
cpukit/sapi/src/fatalsrctext.c | 3 ++-
testsuites/sptests/spinternalerror02/init.c | 2 +-
4 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/bsps/shared/irq/irq-default-handler.c
b/bsps/shared/irq/irq-default-handler.c
index cfe91f4202..666d48aaa8 100644
--- a/bsps/shared/irq/irq-default-handler.c
+++ b/bsps/shared/irq/irq-default-handler.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2008, 2012 embedded brains GmbH
(http://www.embedded-brains.de)
+ * Copyright (C) 2008, 2021 embedded brains GmbH
(http://www.embedded-brains.de)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -34,13 +34,11 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include
-
-#include
-
#include
-void bsp_interrupt_handler_default(rtems_vector_number vector)
+#include
+
+void bsp_interrupt_handler_default( rtems_vector_number vector )
{
- printk("spurious interrupt: %" PRIu32 "\n", vector);
+ _Terminate( RTEMS_FATAL_SOURCE_SPURIOUS_INTERRUPT, vector );
}
diff --git a/cpukit/include/rtems/score/interr.h
b/cpukit/include/rtems/score/interr.h
index 33e9524b65..e5a0a62cf6 100644
--- a/cpukit/include/rtems/score/interr.h
+++ b/cpukit/include/rtems/score/interr.h
@@ -143,6 +143,13 @@ typedef enum {
*/
RTEMS_FATAL_SOURCE_HEAP = 13,
+ /**
+ * @brief Fatal source for spurious interrupts.
+ *
+ * The fatal code is the interrupt vector number of the spurious interrupt.
+ */
+ RTEMS_FATAL_SOURCE_SPURIOUS_INTERRUPT = 14,
+
/**
* @brief The last available fatal source.
*
diff --git a/cpukit/sapi/src/fatalsrctext.c b/cpukit/sapi/src/fatalsrctext.c
index 6510725e13..636878da4c 100644
--- a/cpukit/sapi/src/fatalsrctext.c
+++ b/cpukit/sapi/src/fatalsrctext.c
@@ -41,7 +41,8 @@ static const char *const fatal_source_text[] = {
"RTEMS_FATAL_SOURCE_SMP",
"RTEMS_FATAL_SOURCE_PANIC",
"RTEMS_FATAL_SOURCE_INVALID_HEAP_FREE",
- "RTEMS_FATAL_SOURCE_HEAP"
+ "RTEMS_FATAL_SOURCE_HEAP",
+ "RTEMS_FATAL_SOURCE_SPURIOUS_INTERRUPT"
};
const char *rtems_fatal_source_text( rtems_fatal_source source )
diff --git a/testsuites/sptests/spinternalerror02/init.c
b/testsuites/sptests/spinternalerror02/init.c
index 1564061956..30f09de6cc 100644
--- a/testsuites/sptests/spinternalerror02/init.c
+++ b/testsuites/sptests/spinternalerror02/init.c
@@ -53,7 +53,7 @@ static void test_fatal_source_text(void)
puts( text );
} while ( text != text_last );
- rtems_test_assert( source - 3 == RTEMS_FATAL_SOURCE_HEAP );
+ rtems_test_assert( source - 3 == RTEMS_FATAL_SOURCE_SPURIOUS_INTERRUPT );
}
static void test_status_text(void)
--
2.26.2
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 42/42] validation: Test rtems_interrupt_set_affinity()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
testsuites/validation/tc-intr-set-affinity.c | 670 ++
2 files changed, 671 insertions(+)
create mode 100644 testsuites/validation/tc-intr-set-affinity.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 5b337b3a34..9f7ab9f6c1 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -23,6 +23,7 @@ source:
- testsuites/validation/tc-intr-is-pending.c
- testsuites/validation/tc-intr-raise.c
- testsuites/validation/tc-intr-raise-on.c
+- testsuites/validation/tc-intr-set-affinity.c
- testsuites/validation/tc-intr-vector-disable.c
- testsuites/validation/tc-intr-vector-enable.c
- testsuites/validation/tc-intr-vector-is-enabled.c
diff --git a/testsuites/validation/tc-intr-set-affinity.c
b/testsuites/validation/tc-intr-set-affinity.c
new file mode 100644
index 00..b2b47baea8
--- /dev/null
+++ b/testsuites/validation/tc-intr-set-affinity.c
@@ -0,0 +1,670 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqSetAffinity
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqSetAffinity \
+ * spec:/rtems/intr/req/set-affinity
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqSetAffinity_Pre_Vector_Valid,
+ RtemsIntrReqSetAffinity_Pre_Vector_Invalid,
+ RtemsIntrReqSetAffinity_Pre_Vector_NA
+} RtemsIntrReqSetAffinity_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqSetAffinity_Pre_CPUSetKind_Valid,
+ RtemsIntrReqSetAffinity_Pre_CPUSetKind_Huge,
+ RtemsIntrReqSetAffinity_Pre_CPUSetKind_Askew,
+ RtemsIntrReqSetAffinity_Pre_CPUSetKind_NA
+} RtemsIntrReqSetAffinity_Pre_CPUSetKind;
+
+typedef enum {
+ RtemsIntrReqSetAffinity_Pre_CPUSet_Valid,
+ RtemsIntrReqSetAffinity_Pre_CPUSet_Null,
+ RtemsIntrReqSetAffinity_Pre_CPUSet_NA
+} RtemsIntrReqSetAffinity_Pre_CPUSet;
+
+typedef enum {
+ RtemsIntrReqSetAffinity_Pre_CanSetAffinity_Yes,
+ RtemsIntrReqSetAffinity_Pre_CanSetAffinity_No,
+ RtemsIntrReqSetAffinity_Pre_CanSetAffinity_NA
+} RtemsIntrReqSetAffinity_Pre_CanSetAffinity;
+
+typedef enum {
+ RtemsIntrReqSetAffinity_Post_Status_Ok,
+ RtemsIntrReqSetAffinity_Post_Status_InvAddr,
+ RtemsIntrReqSetAffinity_Post_Status_InvId,
+ RtemsIntrReqSetAffinity_Post_Status_InvNum,
+ RtemsIntrReqSetAffinity_Post_Status_Unsat,
+ RtemsIntrReqSetAffinity_Post_Status_NA
+} RtemsIntrReqSetAffinity_Post_Status;
+
+typedef enum {
+ RtemsIntrReqSetAffinity_Post_SetAffinity_Yes,
+ RtemsIntrReqSetAffinity_Post_SetAffinity_Nop,
+ RtemsIntrReqSetAffinity_Post_SetAffinity_NA
+} RtemsIntrReqSetAffinity_Post_SetAffinity;
+
+/**
+ * @brief Test context for
[PATCH v3 14/42] bsps/irq: Add rtems_interrupt_is_pending()
Add a default implementation which just returns RTEMS_UNSATISFIED.
Update #3269.
---
bsps/arm/beagle/irq/irq.c | 11 ++
bsps/arm/csb336/irq/irq.c | 11 ++
bsps/arm/csb337/irq/irq.c | 11 ++
bsps/arm/edb7312/irq/irq.c| 11 ++
bsps/arm/gumstix/irq/irq.c| 11 ++
bsps/arm/lpc24xx/irq/irq.c| 11 ++
bsps/arm/lpc32xx/irq/irq.c| 11 ++
bsps/arm/raspberrypi/irq/irq.c| 11 ++
bsps/arm/rtl22xx/irq/irq.c| 11 ++
bsps/arm/shared/irq/irq-armv7m.c | 11 ++
bsps/arm/smdk2410/irq/irq.c | 11 ++
bsps/arm/tms570/irq/irq.c | 11 ++
bsps/i386/shared/irq/irq.c| 11 ++
bsps/include/bsp/irq-generic.h| 26 +++
bsps/lm32/shared/irq/irq.c| 11 ++
bsps/m68k/genmcf548x/irq/irq.c| 11 ++
bsps/mips/shared/irq/irq.c| 11 ++
bsps/powerpc/gen5200/irq/irq.c| 11 ++
bsps/powerpc/gen83xx/irq/irq.c| 11 ++
bsps/powerpc/mpc55xxevb/start/irq.c | 11 ++
bsps/powerpc/mpc8260ads/irq/irq.c | 11 ++
bsps/powerpc/psim/irq/irq_init.c | 11 ++
bsps/powerpc/qemuppc/irq/irq_init.c | 11 ++
bsps/powerpc/qoriq/irq/irq.c | 22 +++
bsps/powerpc/shared/irq/ppc-irq-generic.c | 11 ++
bsps/powerpc/t32mppc/irq/irq.c| 11 ++
bsps/powerpc/tqm8xx/irq/irq.c | 11 ++
bsps/powerpc/virtex/irq/irq_init.c| 11 ++
bsps/riscv/griscv/irq/irq.c | 11 ++
bsps/riscv/riscv/irq/irq.c| 11 ++
bsps/shared/dev/irq/arm-gicv2.c | 11 ++
bsps/shared/dev/irq/arm-gicv3.c | 11 ++
bsps/shared/irq/irq-default.c | 11 ++
bsps/shared/irq/irq-raise-clear.c | 17 ++-
bsps/sparc/leon3/start/eirq.c | 11 ++
bsps/sparc/shared/irq/irq-shared.c| 11 ++
bsps/x86_64/amd64/interrupts/idt.c| 11 ++
37 files changed, 438 insertions(+), 1 deletion(-)
diff --git a/bsps/arm/beagle/irq/irq.c b/bsps/arm/beagle/irq/irq.c
index 0285e46442..b0b7f77011 100644
--- a/bsps/arm/beagle/irq/irq.c
+++ b/bsps/arm/beagle/irq/irq.c
@@ -103,6 +103,17 @@ rtems_status_code bsp_interrupt_get_attributes(
return RTEMS_SUCCESSFUL;
}
+rtems_status_code bsp_interrupt_is_pending(
+ rtems_vector_number vector,
+ bool *pending
+)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ bsp_interrupt_assert(pending != NULL);
+ *pending = false;
+ return RTEMS_UNSATISFIED;
+}
+
rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
diff --git a/bsps/arm/csb336/irq/irq.c b/bsps/arm/csb336/irq/irq.c
index 85137195ef..c16a6d8773 100644
--- a/bsps/arm/csb336/irq/irq.c
+++ b/bsps/arm/csb336/irq/irq.c
@@ -34,6 +34,17 @@ rtems_status_code bsp_interrupt_get_attributes(
return RTEMS_SUCCESSFUL;
}
+rtems_status_code bsp_interrupt_is_pending(
+ rtems_vector_number vector,
+ bool *pending
+)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ bsp_interrupt_assert(pending != NULL);
+ *pending = false;
+ return RTEMS_UNSATISFIED;
+}
+
rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
diff --git a/bsps/arm/csb337/irq/irq.c b/bsps/arm/csb337/irq/irq.c
index e06c9f20b6..98d775ce28 100644
--- a/bsps/arm/csb337/irq/irq.c
+++ b/bsps/arm/csb337/irq/irq.c
@@ -35,6 +35,17 @@ rtems_status_code bsp_interrupt_get_attributes(
return RTEMS_SUCCESSFUL;
}
+rtems_status_code bsp_interrupt_is_pending(
+ rtems_vector_number vector,
+ bool *pending
+)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ bsp_interrupt_assert(pending != NULL);
+ *pending = false;
+ return RTEMS_UNSATISFIED;
+}
+
rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
diff --git a/bsps/arm/edb7312/irq/irq.c b/bsps/arm/edb7312/irq/irq.c
index c1d166049b..9a64e069d0 100644
--- a/bsps/arm/edb7312/irq/irq.c
+++ b/bsps/arm/edb7312/irq/irq.c
@@ -35,6 +35,17 @@ rtems_status_code bsp_interrupt_get_attributes(
return RTEMS_SUCCESSFUL;
}
+rtems_status_code bsp_interrupt_is_pending(
+ rtems_vector_number vector,
+ bool *pending
+)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ bsp_interrupt_assert(pending != NULL);
+ *pending = false;
+ return RTEMS_UNSATISFIED;
+}
+
rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
{
[PATCH v3 41/42] validation: Test rtems_interrupt_get_affinity()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
testsuites/validation/tc-intr-get-affinity.c | 639 ++
2 files changed, 640 insertions(+)
create mode 100644 testsuites/validation/tc-intr-get-affinity.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 6f68727f01..5b337b3a34 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -18,6 +18,7 @@ source:
- testsuites/validation/tc-intr-clear.c
- testsuites/validation/tc-intr-entry-install.c
- testsuites/validation/tc-intr-entry-remove.c
+- testsuites/validation/tc-intr-get-affinity.c
- testsuites/validation/tc-intr-get-attributes.c
- testsuites/validation/tc-intr-is-pending.c
- testsuites/validation/tc-intr-raise.c
diff --git a/testsuites/validation/tc-intr-get-affinity.c
b/testsuites/validation/tc-intr-get-affinity.c
new file mode 100644
index 00..43d8c75fec
--- /dev/null
+++ b/testsuites/validation/tc-intr-get-affinity.c
@@ -0,0 +1,639 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqGetAffinity
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqGetAffinity \
+ * spec:/rtems/intr/req/get-affinity
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqGetAffinity_Pre_Vector_Valid,
+ RtemsIntrReqGetAffinity_Pre_Vector_Invalid,
+ RtemsIntrReqGetAffinity_Pre_Vector_NA
+} RtemsIntrReqGetAffinity_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqGetAffinity_Pre_CPUSetSize_Valid,
+ RtemsIntrReqGetAffinity_Pre_CPUSetSize_TooSmall,
+ RtemsIntrReqGetAffinity_Pre_CPUSetSize_Askew,
+ RtemsIntrReqGetAffinity_Pre_CPUSetSize_NA
+} RtemsIntrReqGetAffinity_Pre_CPUSetSize;
+
+typedef enum {
+ RtemsIntrReqGetAffinity_Pre_CPUSet_Valid,
+ RtemsIntrReqGetAffinity_Pre_CPUSet_Null,
+ RtemsIntrReqGetAffinity_Pre_CPUSet_NA
+} RtemsIntrReqGetAffinity_Pre_CPUSet;
+
+typedef enum {
+ RtemsIntrReqGetAffinity_Pre_CanGetAffinity_Yes,
+ RtemsIntrReqGetAffinity_Pre_CanGetAffinity_No,
+ RtemsIntrReqGetAffinity_Pre_CanGetAffinity_NA
+} RtemsIntrReqGetAffinity_Pre_CanGetAffinity;
+
+typedef enum {
+ RtemsIntrReqGetAffinity_Post_Status_Ok,
+ RtemsIntrReqGetAffinity_Post_Status_InvAddr,
+ RtemsIntrReqGetAffinity_Post_Status_InvId,
+ RtemsIntrReqGetAffinity_Post_Status_InvSize,
+ RtemsIntrReqGetAffinity_Post_Status_Unsat,
+ RtemsIntrReqGetAffinity_Post_Status_NA
+} RtemsIntrReqGetAffinity_Post_Status;
+
+typedef enum {
+ RtemsIntrReqGetAffinity_Post_CPUSetObj_Set,
+ RtemsIntrReqGetAffinity_Post_CPUSetObj_Nop,
+ RtemsIntrReqGetAffinity_Post_CPUSetObj_NA
+} RtemsIntrReqGetAffinity_Post_CPUSetObj;
+
+/**
+ * @brief Test context for
[PATCH v3 07/42] rtems: Add rtems_interrupt_vector_enable()
Add rtems_interrupt_vector_disable().
Update #3269.
---
bsps/shared/irq-default-sources.am | 1 +
bsps/shared/irq-sources.am | 1 +
bsps/shared/irq/irq-enable-disable.c | 59 +
c/src/lib/libbsp/m68k/genmcf548x/Makefile.am | 1 +
c/src/lib/libbsp/powerpc/ss555/Makefile.am | 1 +
cpukit/include/rtems/irq-extension.h | 88
spec/build/bsps/m68k/genmcf548x/obj.yml | 1 +
spec/build/bsps/objirq.yml | 1 +
spec/build/bsps/powerpc/ss555/bspss555.yml | 1 +
9 files changed, 154 insertions(+)
create mode 100644 bsps/shared/irq/irq-enable-disable.c
diff --git a/bsps/shared/irq-default-sources.am
b/bsps/shared/irq-default-sources.am
index 9f0e4686f7..fe3352f7e5 100644
--- a/bsps/shared/irq-default-sources.am
+++ b/bsps/shared/irq-default-sources.am
@@ -1,6 +1,7 @@
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-affinity.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default.c
librtemsbsp_a_SOURCES +=
../../../../../../bsps/shared/irq/irq-default-handler.c
+librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-enable-disable.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-generic.c
librtemsbsp_a_SOURCES +=
../../../../../../bsps/shared/irq/irq-handler-iterate.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-info.c
diff --git a/bsps/shared/irq-sources.am b/bsps/shared/irq-sources.am
index 776958dd8f..d2536eb56d 100644
--- a/bsps/shared/irq-sources.am
+++ b/bsps/shared/irq-sources.am
@@ -1,4 +1,5 @@
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-affinity.c
+librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-enable-disable.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-generic.c
librtemsbsp_a_SOURCES +=
../../../../../../bsps/shared/irq/irq-handler-iterate.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-info.c
diff --git a/bsps/shared/irq/irq-enable-disable.c
b/bsps/shared/irq/irq-enable-disable.c
new file mode 100644
index 00..792f5e60c6
--- /dev/null
+++ b/bsps/shared/irq/irq-enable-disable.c
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief This source file contains the implementation of
+ * rtems_interrupt_vector_enable() and rtems_interrupt_vector_disable().
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+
+rtems_status_code rtems_interrupt_vector_enable( rtems_vector_number vector )
+{
+ if ( !bsp_interrupt_is_valid_vector( vector ) ) {
+return RTEMS_INVALID_ID;
+ }
+
+ bsp_interrupt_vector_enable( vector );
+
+ return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code rtems_interrupt_vector_disable( rtems_vector_number vector )
+{
+ if ( !bsp_interrupt_is_valid_vector( vector ) ) {
+return RTEMS_INVALID_ID;
+ }
+
+ bsp_interrupt_vector_disable( vector );
+
+ return RTEMS_SUCCESSFUL;
+}
diff --git a/c/src/lib/libbsp/m68k/genmcf548x/Makefile.am
b/c/src/lib/libbsp/m68k/genmcf548x/Makefile.am
index 88a1ab0e5b..ecc8c99b26 100644
--- a/c/src/lib/libbsp/m68k/genmcf548x/Makefile.am
+++ b/c/src/lib/libbsp/m68k/genmcf548x/Makefile.am
@@ -40,6 +40,7 @@ librtemsbsp_a_SOURCES +=
../../../../../../bsps/m68k/genmcf548x/btimer/btimer.c
# IRQ
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-affinity.c
librtemsbsp_a_SOURCES +=
../../../../../../bsps/shared/irq/irq-default-handler.c
+librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-enable-disable.c
librtemsbsp_a_SOURCES +=
[PATCH v3 09/42] rtems: Add rtems_interrupt_is_pending()
Update #3269. --- cpukit/include/rtems/irq-extension.h | 54 1 file changed, 54 insertions(+) diff --git a/cpukit/include/rtems/irq-extension.h b/cpukit/include/rtems/irq-extension.h index f538297b3c..0a26ef959c 100644 --- a/cpukit/include/rtems/irq-extension.h +++ b/cpukit/include/rtems/irq-extension.h @@ -453,6 +453,60 @@ rtems_status_code rtems_interrupt_vector_enable( rtems_vector_number vector ); */ rtems_status_code rtems_interrupt_vector_disable( rtems_vector_number vector ); +/* Generated from spec:/rtems/intr/if/is-pending */ + +/** + * @ingroup RTEMSAPIClassicIntr + * + * @brief Checks if the interrupt is pending. + * + * @param vector is the interrupt vector number. + * + * @param[out] pending is the pointer to a ``bool`` object. When the directive + * call is successful, the pending status of the interrupt associated with + * the interrupt vector specified by ``vector`` will be stored in this + * object. When the interrupt was pending for the processor executing the + * directive call at some time point during the call, the object value will + * be set to true, otherwise to false. + * + * The directive checks if the interrupt associated with the interrupt vector + * specified by ``vector`` was pending for the processor executing the + * directive call at some time point during the call. + * + * @retval ::RTEMS_SUCCESSFUL The requested operation was successful. + * + * @retval ::RTEMS_INVALID_ADDRESS The ``pending`` parameter was NULL. + * + * @retval ::RTEMS_INVALID_ID There was no interrupt vector associated with the + * number specified by ``vector``. + * + * @retval ::RTEMS_UNSATISFIED The request to get the pending status has not + * been satisfied. + * + * @par Notes + * Interrupts may be made pending by calling the rtems_interrupt_raise() or + * rtems_interrupt_raise_on() directives or due to external signals or + * messages. The pending state may be cleared by rtems_interrupt_clear(). + * + * @par Constraints + * @parblock + * The following constraints apply to this directive: + * + * * The directive may be called from within interrupt context. + * + * * The directive may be called from within device driver initialization + * context. + * + * * The directive may be called from within task context. + * + * * The directive will not cause the calling task to be preempted. + * @endparblock + */ +rtems_status_code rtems_interrupt_is_pending( + rtems_vector_number vector, + bool *pending +); + /* Generated from spec:/rtems/intr/if/get-affinity */ /** -- 2.26.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 12/42] bsps/irq: Add rtems_interrupt_raise()
Add rtems_interrupt_raise_on() and rtems_interrupt_clear().
Add a default implementation which just returns RTEMS_UNSATISFIED for
valid parameters.
Update #3269.
---
bsps/arm/beagle/irq/irq.c| 12 +++
bsps/arm/csb336/irq/irq.c| 12 +++
bsps/arm/csb337/irq/irq.c| 12 +++
bsps/arm/edb7312/irq/irq.c | 12 +++
bsps/arm/gumstix/irq/irq.c | 12 +++
bsps/arm/lpc24xx/irq/irq.c | 12 +++
bsps/arm/lpc32xx/irq/irq.c | 12 +++
bsps/arm/raspberrypi/irq/irq.c | 23 ++
bsps/arm/rtl22xx/irq/irq.c | 12 +++
bsps/arm/shared/irq/irq-armv7m.c | 12 +++
bsps/arm/smdk2410/irq/irq.c | 12 +++
bsps/arm/tms570/irq/irq.c| 12 +++
bsps/i386/shared/irq/irq.c | 12 +++
bsps/include/bsp/irq-generic.h | 47 +++
bsps/lm32/shared/irq/irq.c | 12 +++
bsps/m68k/genmcf548x/irq/irq.c | 12 +++
bsps/mips/shared/irq/irq.c | 12 +++
bsps/powerpc/gen5200/irq/irq.c | 12 +++
bsps/powerpc/gen83xx/irq/irq.c | 12 +++
bsps/powerpc/mpc55xxevb/start/irq.c | 12 +++
bsps/powerpc/mpc8260ads/irq/irq.c| 12 +++
bsps/powerpc/psim/irq/irq_init.c | 12 +++
bsps/powerpc/qemuppc/irq/irq_init.c | 12 +++
bsps/powerpc/qoriq/irq/irq.c | 46 +++
bsps/powerpc/shared/irq/ppc-irq-generic.c| 12 +++
bsps/powerpc/t32mppc/irq/irq.c | 12 +++
bsps/powerpc/tqm8xx/irq/irq.c| 12 +++
bsps/powerpc/virtex/irq/irq_init.c | 12 +++
bsps/riscv/griscv/irq/irq.c | 23 ++
bsps/riscv/riscv/irq/irq.c | 23 ++
bsps/shared/dev/irq/arm-gicv2.c | 23 ++
bsps/shared/dev/irq/arm-gicv3.c | 23 ++
bsps/shared/irq-default-sources.am | 1 +
bsps/shared/irq-sources.am | 1 +
bsps/shared/irq/irq-default.c| 12 +++
bsps/shared/irq/irq-raise-clear.c| 84
bsps/sparc/leon3/start/eirq.c| 23 ++
bsps/sparc/shared/irq/irq-shared.c | 23 ++
bsps/x86_64/amd64/interrupts/idt.c | 12 +++
c/src/lib/libbsp/m68k/genmcf548x/Makefile.am | 1 +
c/src/lib/libbsp/powerpc/ss555/Makefile.am | 1 +
spec/build/bsps/m68k/genmcf548x/obj.yml | 1 +
spec/build/bsps/objirq.yml | 1 +
spec/build/bsps/powerpc/ss555/bspss555.yml | 1 +
44 files changed, 669 insertions(+)
create mode 100644 bsps/shared/irq/irq-raise-clear.c
diff --git a/bsps/arm/beagle/irq/irq.c b/bsps/arm/beagle/irq/irq.c
index d0a07d1937..4a89189a32 100644
--- a/bsps/arm/beagle/irq/irq.c
+++ b/bsps/arm/beagle/irq/irq.c
@@ -95,6 +95,18 @@ static uint32_t omap_get_mir_reg(rtems_vector_number vector,
uint32_t *const mas
return mir_reg;
}
+rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ return RTEMS_UNSATISFIED;
+}
+
+rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ return RTEMS_UNSATISFIED;
+}
+
rtems_status_code bsp_interrupt_vector_is_enabled(
rtems_vector_number vector,
bool *enabled
diff --git a/bsps/arm/csb336/irq/irq.c b/bsps/arm/csb336/irq/irq.c
index 80914fe28f..3c9e6a7ea7 100644
--- a/bsps/arm/csb336/irq/irq.c
+++ b/bsps/arm/csb336/irq/irq.c
@@ -26,6 +26,18 @@ void bsp_interrupt_dispatch(void)
bsp_interrupt_handler_dispatch(vector);
}
+rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ return RTEMS_UNSATISFIED;
+}
+
+rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ return RTEMS_UNSATISFIED;
+}
+
rtems_status_code bsp_interrupt_vector_is_enabled(
rtems_vector_number vector,
bool *enabled
diff --git a/bsps/arm/csb337/irq/irq.c b/bsps/arm/csb337/irq/irq.c
index 5276374a1e..d097a92259 100644
--- a/bsps/arm/csb337/irq/irq.c
+++ b/bsps/arm/csb337/irq/irq.c
@@ -27,6 +27,18 @@ void bsp_interrupt_dispatch(void)
AIC_CTL_REG(AIC_EOICR) = 0;
}
+rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ return RTEMS_UNSATISFIED;
+}
+
+rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ return RTEMS_UNSATISFIED;
+}
+
rtems_status_code bsp_interrupt_vector_is_enabled(
rtems_vector_number vector,
bool *enabled
diff --git a/bsps/arm/edb7312/irq/irq.c b/bsps/arm/edb7312/irq/irq.c
index d11cbf78c3..0522e40bd8 100644
---
[PATCH v3 29/42] validation: GetValidInterruptVectorNumber()
Update #3269.
---
testsuites/validation/tx-interrupt.c | 26 ++
testsuites/validation/tx-support.h | 5 +
2 files changed, 31 insertions(+)
diff --git a/testsuites/validation/tx-interrupt.c
b/testsuites/validation/tx-interrupt.c
index d056af5abc..0ff5ec017f 100644
--- a/testsuites/validation/tx-interrupt.c
+++ b/testsuites/validation/tx-interrupt.c
@@ -43,6 +43,32 @@
#include
#include
+#include
+
+rtems_vector_number GetValidInterruptVectorNumber(
+ const rtems_interrupt_attributes *required
+)
+{
+ rtems_vector_number vector;
+
+ for ( vector = 0; vector < BSP_INTERRUPT_VECTOR_COUNT; ++vector ) {
+rtems_status_code sc;
+rtems_interrupt_attributes attr;
+
+sc = rtems_interrupt_get_attributes( vector, );
+
+if (
+ sc == RTEMS_SUCCESSFUL &&
+( required == NULL ||
+ !required->can_get_affinity || attr.can_get_affinity )
+ ) {
+ break;
+}
+ }
+
+ return vector;
+}
+
static void HasInstalled(
void *arg,
const char *info,
diff --git a/testsuites/validation/tx-support.h
b/testsuites/validation/tx-support.h
index 378e98ee3f..20006f5dd8 100644
--- a/testsuites/validation/tx-support.h
+++ b/testsuites/validation/tx-support.h
@@ -38,6 +38,7 @@
#define _TX_SUPPORT_H
#include
+#include
#include
#ifdef __cplusplus
@@ -113,6 +114,10 @@ void CallWithinISRSubmit( CallWithinISRRequest *request );
void CallWithinISRWait( const CallWithinISRRequest *request );
+rtems_vector_number GetValidInterruptVectorNumber(
+ const rtems_interrupt_attributes *required
+);
+
bool HasInterruptVectorEntriesInstalled( rtems_vector_number vector );
/** @} */
--
2.26.2
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 28/42] validation: HasInterruptVectorEntriesInstalled()
Update #3269.
---
.../testsuites/validation/libvalidation.yml | 1 +
testsuites/validation/tx-interrupt.c | 79 +++
testsuites/validation/tx-support.h| 2 +
3 files changed, 82 insertions(+)
create mode 100644 testsuites/validation/tx-interrupt.c
diff --git a/spec/build/testsuites/validation/libvalidation.yml
b/spec/build/testsuites/validation/libvalidation.yml
index 54c7ae0ac0..98dd2e3623 100644
--- a/spec/build/testsuites/validation/libvalidation.yml
+++ b/spec/build/testsuites/validation/libvalidation.yml
@@ -12,6 +12,7 @@ install-path: null
links: []
source:
- testsuites/validation/tx-call-within-isr.c
+- testsuites/validation/tx-interrupt.c
- testsuites/validation/tx-support.c
target: validation
type: build
diff --git a/testsuites/validation/tx-interrupt.c
b/testsuites/validation/tx-interrupt.c
new file mode 100644
index 00..d056af5abc
--- /dev/null
+++ b/testsuites/validation/tx-interrupt.c
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestSuites
+ *
+ * @brief This source file contains the implementation of
+ * HasInterruptVectorEntriesInstalled().
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "tx-support.h"
+
+#include
+#include
+
+static void HasInstalled(
+ void *arg,
+ const char *info,
+ rtems_optionoptions,
+ rtems_interrupt_handler handler_routine,
+ void *handler_arg
+)
+{
+ bool *has_installed_entries;
+
+ (void) info;
+ (void) options;
+ (void) handler_routine;
+ (void) handler_arg;
+
+ has_installed_entries = arg;
+ *has_installed_entries = true;
+}
+
+bool HasInterruptVectorEntriesInstalled( rtems_vector_number vector )
+{
+ bool has_installed_entries;
+ rtems_status_code sc;
+
+ has_installed_entries = false;
+ sc = rtems_interrupt_handler_iterate(
+vector,
+HasInstalled,
+_installed_entries
+ );
+ T_quiet_rsc_success( sc );
+
+ return has_installed_entries;
+}
diff --git a/testsuites/validation/tx-support.h
b/testsuites/validation/tx-support.h
index 9d5a51e461..378e98ee3f 100644
--- a/testsuites/validation/tx-support.h
+++ b/testsuites/validation/tx-support.h
@@ -113,6 +113,8 @@ void CallWithinISRSubmit( CallWithinISRRequest *request );
void CallWithinISRWait( const CallWithinISRRequest *request );
+bool HasInterruptVectorEntriesInstalled( rtems_vector_number vector );
+
/** @} */
#ifdef __cplusplus
--
2.26.2
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 16/42] bsps/irq: bsp_interrupt_vector_disable()
Return a status code for bsp_interrupt_vector_disable().
Update #3269.
---
bsps/arm/beagle/irq/irq.c | 3 ++-
bsps/arm/csb336/irq/irq.c | 4 +++-
bsps/arm/csb337/irq/irq.c | 3 ++-
bsps/arm/edb7312/irq/irq.c| 4 +++-
bsps/arm/gumstix/irq/irq.c| 3 ++-
bsps/arm/lpc24xx/irq/irq.c| 3 ++-
bsps/arm/lpc32xx/irq/irq.c| 4 +++-
bsps/arm/raspberrypi/irq/irq.c| 3 ++-
bsps/arm/rtl22xx/irq/irq.c| 3 ++-
bsps/arm/shared/irq/irq-armv7m.c | 3 ++-
bsps/arm/smdk2410/irq/irq.c | 3 ++-
bsps/arm/tms570/irq/irq.c | 3 ++-
bsps/i386/shared/irq/irq.c| 3 ++-
bsps/include/bsp/irq-generic.h| 16 ++--
bsps/lm32/shared/irq/irq.c| 3 ++-
bsps/m68k/genmcf548x/irq/irq.c| 4 +++-
bsps/mips/shared/irq/irq.c| 3 ++-
bsps/powerpc/gen5200/irq/irq.c| 4 +++-
bsps/powerpc/gen83xx/irq/irq.c| 4 +++-
bsps/powerpc/mpc55xxevb/start/irq.c | 3 ++-
bsps/powerpc/mpc8260ads/irq/irq.c | 4 +++-
bsps/powerpc/psim/irq/irq_init.c | 3 ++-
bsps/powerpc/qemuppc/irq/irq_init.c | 3 ++-
bsps/powerpc/qoriq/irq/irq.c | 5 +++--
bsps/powerpc/shared/irq/ppc-irq-generic.c | 3 ++-
bsps/powerpc/t32mppc/irq/irq.c| 3 ++-
bsps/powerpc/tqm8xx/irq/irq.c | 4 +++-
bsps/powerpc/virtex/irq/irq_init.c| 4 +++-
bsps/riscv/griscv/irq/irq.c | 3 ++-
bsps/riscv/riscv/irq/irq.c| 4 +++-
bsps/shared/dev/irq/arm-gicv2.c | 3 ++-
bsps/shared/dev/irq/arm-gicv3.c | 4 +++-
bsps/shared/irq/irq-default.c | 3 ++-
bsps/shared/irq/irq-enable-disable.c | 4 +---
bsps/sparc/leon3/start/eirq.c | 3 ++-
bsps/sparc/shared/irq/irq-shared.c| 3 ++-
bsps/x86_64/amd64/interrupts/idt.c| 3 ++-
37 files changed, 93 insertions(+), 45 deletions(-)
diff --git a/bsps/arm/beagle/irq/irq.c b/bsps/arm/beagle/irq/irq.c
index ff5ab4d15f..d892299fbe 100644
--- a/bsps/arm/beagle/irq/irq.c
+++ b/bsps/arm/beagle/irq/irq.c
@@ -150,7 +150,7 @@ rtems_status_code
bsp_interrupt_vector_enable(rtems_vector_number vector)
return RTEMS_SUCCESSFUL;
}
-void bsp_interrupt_vector_disable(rtems_vector_number vector)
+rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
{
uint32_t mask, cur;
uint32_t mir_reg = omap_get_mir_reg(vector, );
@@ -160,6 +160,7 @@ void bsp_interrupt_vector_disable(rtems_vector_number
vector)
cur = mmio_read(omap_intr.base + mir_reg);
mmio_write(omap_intr.base + mir_reg, cur | mask);
flush_data_cache();
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_facility_initialize(void)
diff --git a/bsps/arm/csb336/irq/irq.c b/bsps/arm/csb336/irq/irq.c
index 4cdce1a207..266ca0113f 100644
--- a/bsps/arm/csb336/irq/irq.c
+++ b/bsps/arm/csb336/irq/irq.c
@@ -78,12 +78,14 @@ rtems_status_code
bsp_interrupt_vector_enable(rtems_vector_number vector)
return RTEMS_SUCCESSFUL;
}
-void bsp_interrupt_vector_disable(rtems_vector_number vector)
+rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
if (vector < MC9328MXL_NUM_INTS)
MC9328MXL_AITC_INTDISNUM = vector;
+
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_facility_initialize(void)
diff --git a/bsps/arm/csb337/irq/irq.c b/bsps/arm/csb337/irq/irq.c
index f2e2dbbed8..32f19c7000 100644
--- a/bsps/arm/csb337/irq/irq.c
+++ b/bsps/arm/csb337/irq/irq.c
@@ -76,10 +76,11 @@ rtems_status_code
bsp_interrupt_vector_enable(rtems_vector_number vector)
return RTEMS_SUCCESSFUL;
}
-void bsp_interrupt_vector_disable(rtems_vector_number vector)
+rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
AIC_CTL_REG(AIC_IDCR) = 1 << vector;
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_facility_initialize(void)
diff --git a/bsps/arm/edb7312/irq/irq.c b/bsps/arm/edb7312/irq/irq.c
index 820628a61d..e039e119e5 100644
--- a/bsps/arm/edb7312/irq/irq.c
+++ b/bsps/arm/edb7312/irq/irq.c
@@ -97,7 +97,7 @@ rtems_status_code
bsp_interrupt_vector_enable(rtems_vector_number vector)
return RTEMS_SUCCESSFUL;
}
-void bsp_interrupt_vector_disable(rtems_vector_number vector)
+rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
@@ -121,6 +121,8 @@ void bsp_interrupt_vector_disable(rtems_vector_number
vector)
/* interrupt managed by INTMR3 and INTSR3 */
*EP7312_INTMR3 &= ~(1 << (vector - 21));
}
+
+return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_facility_initialize(void)
diff
[PATCH v3 27/42] validation: Add CallWithinISR()
Update #3269.
---
.../testsuites/validation/libvalidation.yml | 1 +
testsuites/validation/tx-call-within-isr.c| 134 ++
testsuites/validation/tx-support.h| 14 ++
3 files changed, 149 insertions(+)
create mode 100644 testsuites/validation/tx-call-within-isr.c
diff --git a/spec/build/testsuites/validation/libvalidation.yml
b/spec/build/testsuites/validation/libvalidation.yml
index d55d4b9e41..54c7ae0ac0 100644
--- a/spec/build/testsuites/validation/libvalidation.yml
+++ b/spec/build/testsuites/validation/libvalidation.yml
@@ -11,6 +11,7 @@ install: []
install-path: null
links: []
source:
+- testsuites/validation/tx-call-within-isr.c
- testsuites/validation/tx-support.c
target: validation
type: build
diff --git a/testsuites/validation/tx-call-within-isr.c
b/testsuites/validation/tx-call-within-isr.c
new file mode 100644
index 00..226647c0bc
--- /dev/null
+++ b/testsuites/validation/tx-call-within-isr.c
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestSuites
+ *
+ * @brief This source file contains the implementation of CallWithinISR(),
+ * CallWithinISRSubmit(), and CallWithinISRWait().
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "tx-support.h"
+
+#include
+#include
+
+#include
+
+/* Some target architectures need this variable for */
+uint32_t Interrupt_nest;
+
+#define _RTEMS_TMTEST27
+
+#include
+
+typedef struct {
+ Chain_Control pending;
+ RTEMS_INTERRUPT_LOCK_MEMBER( lock )
+} CallWithinISRContext;
+
+static CallWithinISRContext CallWithinISRInstance = {
+#if defined( RTEMS_SMP )
+ .lock = RTEMS_INTERRUPT_LOCK_INITIALIZER( "CallWithinISR" ),
+#endif
+ .pending = CHAIN_INITIALIZER_EMPTY( CallWithinISRInstance.pending )
+};
+
+static void CallWithinISRHandler( rtems_vector_number vector )
+{
+ CallWithinISRContext *ctx;
+
+ (void) vector;
+ ctx =
+
+ while ( true ) {
+rtems_interrupt_lock_context lock_context;
+CallWithinISRRequest*request;
+
+rtems_interrupt_lock_acquire( >lock, _context );
+request = (CallWithinISRRequest *)
+ _Chain_Get_unprotected( >pending );
+rtems_interrupt_lock_release( >lock, _context );
+
+if ( request == NULL ) {
+ break;
+}
+
+( *request->handler )( request->arg );
+_Atomic_Store_uint( >done, 1, ATOMIC_ORDER_RELEASE );
+ }
+}
+
+void CallWithinISR( void ( *handler )( void * ), void *arg )
+{
+ CallWithinISRRequest request;
+
+ request.handler = handler;
+ request.arg = arg;
+ CallWithinISRSubmit( );
+ CallWithinISRWait( );
+}
+
+void CallWithinISRSubmit( CallWithinISRRequest *request )
+{
+ CallWithinISRContext*ctx;
+ rtems_interrupt_lock_context lock_context;
+
+ ctx =
+
+ rtems_interrupt_lock_acquire( >lock, _context );
+ _Atomic_Store_uint( >done, 0, ATOMIC_ORDER_RELAXED );
+ _Chain_Initialize_node( >node );
+ _Chain_Append_unprotected( >pending, >node );
+ rtems_interrupt_lock_release( >lock, _context );
+
+ Cause_tm27_intr();
+}
+
+void CallWithinISRWait( const CallWithinISRRequest *request )
+{
+ while ( _Atomic_Load_uint( >done, ATOMIC_ORDER_ACQUIRE ) == 0 ) {
+/* Wait */
+ }
+}
+
+static void CallWithinISRInitialize( void )
+{
+ Install_tm27_vector( CallWithinISRHandler );
+}
+
+RTEMS_SYSINIT_ITEM(
+ CallWithinISRInitialize,
+ RTEMS_SYSINIT_DEVICE_DRIVERS,
+ RTEMS_SYSINIT_ORDER_MIDDLE
+);
diff --git a/testsuites/validation/tx-support.h
b/testsuites/validation/tx-support.h
index 932584b168..9d5a51e461 100644
---
[PATCH v3 17/42] bsps/irq: bsp_interrupt_get_affinity()
Return a status code for bsp_interrupt_get_affinity().
Update #3269.
---
bsps/include/dev/irq/arm-gic-irq.h | 2 +-
bsps/powerpc/qoriq/include/bsp/irq.h | 2 +-
bsps/powerpc/qoriq/irq/irq.c | 5 +++--
bsps/powerpc/t32mppc/include/bsp/irq.h | 3 ++-
bsps/riscv/griscv/include/bsp/irq.h| 2 +-
bsps/riscv/griscv/irq/irq.c| 4 +++-
bsps/riscv/riscv/include/bsp/irq.h | 2 +-
bsps/riscv/riscv/irq/irq.c | 4 +++-
bsps/shared/dev/irq/arm-gicv2.c| 3 ++-
bsps/shared/dev/irq/arm-gicv3.c| 3 ++-
bsps/shared/irq/irq-affinity.c | 9 -
bsps/sparc/erc32/include/bsp/irq.h | 3 ++-
bsps/sparc/leon3/include/bsp/irq.h | 2 +-
bsps/sparc/leon3/start/eirq.c | 3 ++-
bsps/sparc/shared/irq/irq-shared.c | 2 +-
15 files changed, 33 insertions(+), 16 deletions(-)
diff --git a/bsps/include/dev/irq/arm-gic-irq.h
b/bsps/include/dev/irq/arm-gic-irq.h
index 5ce9d54684..730d792ce4 100644
--- a/bsps/include/dev/irq/arm-gic-irq.h
+++ b/bsps/include/dev/irq/arm-gic-irq.h
@@ -74,7 +74,7 @@ void bsp_interrupt_set_affinity(
const Processor_mask *affinity
);
-void bsp_interrupt_get_affinity(
+rtems_status_code bsp_interrupt_get_affinity(
rtems_vector_number vector,
Processor_mask *affinity
);
diff --git a/bsps/powerpc/qoriq/include/bsp/irq.h
b/bsps/powerpc/qoriq/include/bsp/irq.h
index cf46832045..6618d54190 100644
--- a/bsps/powerpc/qoriq/include/bsp/irq.h
+++ b/bsps/powerpc/qoriq/include/bsp/irq.h
@@ -385,7 +385,7 @@ void bsp_interrupt_set_affinity(
const Processor_mask *affinity
);
-void bsp_interrupt_get_affinity(
+rtems_status_code bsp_interrupt_get_affinity(
rtems_vector_number vector,
Processor_mask *affinity
);
diff --git a/bsps/powerpc/qoriq/irq/irq.c b/bsps/powerpc/qoriq/irq/irq.c
index 37945a..f335aa0602 100644
--- a/bsps/powerpc/qoriq/irq/irq.c
+++ b/bsps/powerpc/qoriq/irq/irq.c
@@ -64,7 +64,7 @@ void bsp_interrupt_set_affinity(
rtems_interrupt_lock_release(, _context);
}
-void bsp_interrupt_get_affinity(
+rtems_status_code bsp_interrupt_get_affinity(
rtems_vector_number vector,
Processor_mask *affinity
)
@@ -75,6 +75,7 @@ void bsp_interrupt_get_affinity(
ev_int_get_config(vector, , , );
_Processor_mask_From_uint32_t(affinity, destination, 0);
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_get_attributes(
@@ -323,7 +324,7 @@ void bsp_interrupt_set_affinity(
src_cfg->dr = _Processor_mask_To_uint32_t(affinity, 0);
}
-void bsp_interrupt_get_affinity(
+rtems_status_code bsp_interrupt_get_affinity(
rtems_vector_number vector,
Processor_mask *affinity
)
diff --git a/bsps/powerpc/t32mppc/include/bsp/irq.h
b/bsps/powerpc/t32mppc/include/bsp/irq.h
index 998eadf3df..c0c374edae 100644
--- a/bsps/powerpc/t32mppc/include/bsp/irq.h
+++ b/bsps/powerpc/t32mppc/include/bsp/irq.h
@@ -35,13 +35,14 @@ RTEMS_INLINE_ROUTINE void bsp_interrupt_set_affinity(
(void) affinity;
}
-RTEMS_INLINE_ROUTINE void bsp_interrupt_get_affinity(
+RTEMS_INLINE_ROUTINE rtems_status_code bsp_interrupt_get_affinity(
rtems_vector_number vector,
Processor_mask *affinity
)
{
(void) vector;
_Processor_mask_From_index( affinity, 0 );
+ return RTEMS_SUCCESSFUL;
}
#ifdef __cplusplus
diff --git a/bsps/riscv/griscv/include/bsp/irq.h
b/bsps/riscv/griscv/include/bsp/irq.h
index f9e280d5a9..1df7b4b584 100644
--- a/bsps/riscv/griscv/include/bsp/irq.h
+++ b/bsps/riscv/griscv/include/bsp/irq.h
@@ -61,7 +61,7 @@ void bsp_interrupt_set_affinity(
const Processor_mask *affinity
);
-void bsp_interrupt_get_affinity(
+rtems_status_code bsp_interrupt_get_affinity(
rtems_vector_number vector,
Processor_mask *affinity
);
diff --git a/bsps/riscv/griscv/irq/irq.c b/bsps/riscv/griscv/irq/irq.c
index 454de414d7..5c52238753 100644
--- a/bsps/riscv/griscv/irq/irq.c
+++ b/bsps/riscv/griscv/irq/irq.c
@@ -156,7 +156,7 @@ rtems_status_code
bsp_interrupt_vector_disable(rtems_vector_number vector)
return RTEMS_SUCCESSFUL;
}
-void bsp_interrupt_get_affinity(
+rtems_status_code bsp_interrupt_get_affinity(
rtems_vector_number vector,
Processor_mask *affinity
)
@@ -171,6 +171,8 @@ void bsp_interrupt_get_affinity(
_Processor_mask_Set(affinity, cpu_index);
}
}
+
+ return RTEMS_SUCCESSFUL;
}
void bsp_interrupt_set_affinity(
diff --git a/bsps/riscv/riscv/include/bsp/irq.h
b/bsps/riscv/riscv/include/bsp/irq.h
index 306988d5e3..03fe8ced3a 100644
--- a/bsps/riscv/riscv/include/bsp/irq.h
+++ b/bsps/riscv/riscv/include/bsp/irq.h
@@ -61,7 +61,7 @@ void bsp_interrupt_set_affinity(
const Processor_mask *affinity
);
-void bsp_interrupt_get_affinity(
+rtems_status_code bsp_interrupt_get_affinity(
rtems_vector_number vector,
Processor_mask *affinity
);
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c
index 000f5c5dea..098a482cd4 100644
--- a/bsps/riscv/riscv/irq/irq.c
+++
[PATCH v3 03/42] bsps/irq: Move handler iterate to separate file
Update #3269.
---
bsps/include/bsp/irq-generic.h | 57
bsps/shared/irq-default-sources.am | 1 +
bsps/shared/irq-sources.am | 1 +
bsps/shared/irq/irq-generic.c| 86 +-
bsps/shared/irq/irq-handler-iterate.c| 96
c/src/lib/libbsp/m68k/genmcf548x/Makefile.am | 1 +
c/src/lib/libbsp/powerpc/ss555/Makefile.am | 1 +
spec/build/bsps/m68k/genmcf548x/obj.yml | 1 +
spec/build/bsps/objirq.yml | 1 +
spec/build/bsps/powerpc/ss555/bspss555.yml | 1 +
10 files changed, 164 insertions(+), 82 deletions(-)
create mode 100644 bsps/shared/irq/irq-handler-iterate.c
diff --git a/bsps/include/bsp/irq-generic.h b/bsps/include/bsp/irq-generic.h
index 8f7683c517..72c1d51332 100644
--- a/bsps/include/bsp/irq-generic.h
+++ b/bsps/include/bsp/irq-generic.h
@@ -322,6 +322,63 @@ void bsp_interrupt_lock(void);
/* For internal use only */
void bsp_interrupt_unlock(void);
+/**
+ * @brief This table contains a bit map which indicates if an entry is unique
+ * or shared.
+ *
+ * If the bit associated with a vector is set, then the entry is unique,
+ * otherwise it may be shared. If the bit with index
+ * #BSP_INTERRUPT_HANDLER_TABLE_SIZE is set, then the interrupt support is
+ * initialized, otherwise it is not initialized.
+ */
+extern uint8_t bsp_interrupt_handler_unique_table[];
+
+/**
+ * @brief Checks if the handler entry associated with the hander index is
+ * unique.
+ *
+ * @param index is the handler index to check.
+ *
+ * @return Returns true, if handler entry associated with the hander index is
+ * unique, otherwise false.
+ */
+static inline bool bsp_interrupt_is_handler_unique( rtems_vector_number index )
+{
+ rtems_vector_number table_index;
+ uint8_t bit;
+
+ table_index = index / 8;
+ bit = (uint8_t) ( 1U << ( index % 8 ) );
+
+ return ( bsp_interrupt_handler_unique_table[ table_index ] & bit ) != 0;
+}
+
+/**
+ * @brief Checks if the interrupt support is initialized.
+ *
+ * @return Returns true, if the interrupt support is initialized, otherwise
+ * false.
+ */
+static inline bool bsp_interrupt_is_initialized( void )
+{
+ return bsp_interrupt_is_handler_unique( BSP_INTERRUPT_HANDLER_TABLE_SIZE );
+}
+
+/**
+ * @brief This handler routine is used for empty entries.
+ */
+void bsp_interrupt_handler_empty( void *arg );
+
+/**
+ * @brief Checks if a handler entry is empty.
+ */
+static inline bool bsp_interrupt_is_empty_handler_entry(
+ const bsp_interrupt_handler_entry *entry
+)
+{
+ return entry->handler == bsp_interrupt_handler_empty;
+}
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/bsps/shared/irq-default-sources.am
b/bsps/shared/irq-default-sources.am
index 6b4696dd26..9f0e4686f7 100644
--- a/bsps/shared/irq-default-sources.am
+++ b/bsps/shared/irq-default-sources.am
@@ -2,6 +2,7 @@ librtemsbsp_a_SOURCES +=
../../../../../../bsps/shared/irq/irq-affinity.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default.c
librtemsbsp_a_SOURCES +=
../../../../../../bsps/shared/irq/irq-default-handler.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-generic.c
+librtemsbsp_a_SOURCES +=
../../../../../../bsps/shared/irq/irq-handler-iterate.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-info.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-lock.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-server.c
diff --git a/bsps/shared/irq-sources.am b/bsps/shared/irq-sources.am
index 65c380a2da..776958dd8f 100644
--- a/bsps/shared/irq-sources.am
+++ b/bsps/shared/irq-sources.am
@@ -1,5 +1,6 @@
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-affinity.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-generic.c
+librtemsbsp_a_SOURCES +=
../../../../../../bsps/shared/irq/irq-handler-iterate.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-info.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-legacy.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-lock.c
diff --git a/bsps/shared/irq/irq-generic.c b/bsps/shared/irq/irq-generic.c
index bea6612136..81da647228 100644
--- a/bsps/shared/irq/irq-generic.c
+++ b/bsps/shared/irq/irq-generic.c
@@ -50,14 +50,14 @@ bsp_interrupt_handler_entry bsp_interrupt_handler_table
[BSP_INTERRUPT_HANDLER_TABLE_SIZE];
/* The last entry indicates if everything is initialized */
-static uint8_t bsp_interrupt_handler_unique_table
- [(BSP_INTERRUPT_HANDLER_TABLE_SIZE + 7 + 1) / 8];
+uint8_t bsp_interrupt_handler_unique_table
+ [ ( BSP_INTERRUPT_HANDLER_TABLE_SIZE + 7 + 1 ) / 8 ];
-static void bsp_interrupt_handler_empty(void *arg)
+void bsp_interrupt_handler_empty( void *arg )
{
rtems_vector_number vector = (rtems_vector_number) (uintptr_t) arg;
- bsp_interrupt_handler_default(vector);
+ bsp_interrupt_handler_default( vector );
}
[PATCH v3 08/42] rtems: Add rtems_interrupt_vector_is_enabled()
Update #3269. --- cpukit/include/rtems/irq-extension.h | 50 1 file changed, 50 insertions(+) diff --git a/cpukit/include/rtems/irq-extension.h b/cpukit/include/rtems/irq-extension.h index e0d63c9dcb..f538297b3c 100644 --- a/cpukit/include/rtems/irq-extension.h +++ b/cpukit/include/rtems/irq-extension.h @@ -315,6 +315,56 @@ rtems_status_code rtems_interrupt_handler_remove( void *arg ); +/* Generated from spec:/rtems/intr/if/vector-is-enabled */ + +/** + * @ingroup RTEMSAPIClassicIntr + * + * @brief Checks if the interrupt vector is enabled. + * + * @param vector is the interrupt vector number. + * + * @param[out] enabled is the pointer to a ``bool`` object. When the directive + * call is successful, the enabled status of the interrupt associated with + * the interrupt vector specified by ``vector`` will be stored in this + * object. When the interrupt was enabled for the processor executing the + * directive call at some time point during the call, the object value will + * be set to true, otherwise to false. + * + * The directive checks if the interrupt associated with the interrupt vector + * specified by ``vector`` was enabled for the processor executing the + * directive call at some time point during the call. + * + * @retval ::RTEMS_SUCCESSFUL The requested operation was successful. + * + * @retval ::RTEMS_INVALID_ADDRESS The ``enabled`` parameter was NULL. + * + * @retval ::RTEMS_INVALID_ID There was no interrupt vector associated with the + * number specified by ``vector``. + * + * @par Notes + * Interrupt vectors may be enabled by rtems_interrupt_vector_enable() and + * disabled by rtems_interrupt_vector_disable(). + * + * @par Constraints + * @parblock + * The following constraints apply to this directive: + * + * * The directive may be called from within interrupt context. + * + * * The directive may be called from within device driver initialization + * context. + * + * * The directive may be called from within task context. + * + * * The directive will not cause the calling task to be preempted. + * @endparblock + */ +rtems_status_code rtems_interrupt_vector_is_enabled( + rtems_vector_number vector, + bool *enabled +); + /* Generated from spec:/rtems/intr/if/vector-enable */ /** -- 2.26.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 00/42] Document, enhance, and test Interrupt Manager Extension
This patch set enhances the Interrupt Manager Extension so that it can be tested with generic tests. The following new directives are introduced for this purpose: * rtems_interrupt_get_attributes() * rtems_interrupt_vector_is_enabled() * rtems_interrupt_vector_enable() * rtems_interrupt_vector_disable() * rtems_interrupt_is_pending() * rtems_interrupt_cause_on() The documentation and the implementation for the following directives is also provided: * rtems_interrupt_cause() * rtems_interrupt_clear() A default implementation is provided for all BSPs so that the new test cases link. A proper implementation is provided for SPARC BSPs and AArch32/AArch64 BSPs which use the GIC. I used an i.MX7D BSP to run the tests on real hardware. The tests don't run on Qemu currently due to a bug in the GIC emulation: https://lists.gnu.org/archive/html/qemu-devel/2021-07/msg02500.html The following new directives were added to support interrupt handlers which are managed through user-provided storage (rtems_interrupt_entry): * rtems_interrupt_entry_initialize() * rtems_interrupt_entry_install() * rtems_interrupt_entry_remove() All directives are documented in the RTEMS Classic API Guide: https://ftp.rtems.org/pub/rtems/people/sebh/c-user.pdf See also: https://lists.rtems.org/pipermail/devel/2019-October/055770.html https://devel.rtems.org/ticket/3269 v3: * Rename rtems_interrupt_cause() in rtems_interrupt_raise(). * Rename rtems_interrupt_cause_on() in rtems_interrupt_raise_on(). * Fine tune the interrupt attributes. * Fix several typos. Sebastian Huber (42): bsps/irq: Move get/set affinity to separate file bsps/irq: Canonicalize get/set affinity errors bsps/irq: Move handler iterate to separate file rtems: Add rtems_interrupt_raise() rtems: Generate rtems: Add rtems_interrupt_get_attributes() rtems: Add rtems_interrupt_vector_enable() rtems: Add rtems_interrupt_vector_is_enabled() rtems: Add rtems_interrupt_is_pending() rtems: Add RTEMS_FATAL_SOURCE_SPURIOUS_INTERRUPT bsps/irq: Add rtems_interrupt_vector_is_enabled() bsps/irq: Add rtems_interrupt_raise() bsps/irq: Add rtems_interrupt_get_attributes() bsps/irq: Add rtems_interrupt_is_pending() bsps/irq: bsp_interrupt_vector_enable() bsps/irq: bsp_interrupt_vector_disable() bsps/irq: bsp_interrupt_get_affinity() bsps/irq: bsp_interrupt_set_affinity() bsps/irq: Implement new directives for GICv2/3 sparc/irq: Implement new interrupt directives rtems: Add rtems_interrupt_entry_install() bsps/irq: Use rtems_interrupt_entry bsps/irq: Add bsp_interrupt_check_and_lock() bsps/irq: Move bsp_interrupt_handler_is_empty() bsps/irq: Add rtems_interrupt_entry_install() bsp/raspberrypi: Add interrupt get/set affinity validation: Add CallWithinISR() validation: HasInterruptVectorEntriesInstalled() validation: GetValidInterruptVectorNumber() validation: GetTestableInterruptVector() validation: Test rtems_interrupt_get_attributes() validation: rtems_interrupt_vector_is_enabled() validation: Test rtems_interrupt_vector_enable() validation: Test rtems_interrupt_vector_disable() validation: Test rtems_interrupt_entry_install() validation: Test rtems_interrupt_entry_remove() validation: Test rtems_interrupt_raise() validation: Test rtems_interrupt_clear() validation: Test rtems_interrupt_is_pending() validation: Test rtems_interrupt_raise_on() validation: Test rtems_interrupt_get_affinity() validation: Test rtems_interrupt_set_affinity() bsps/aarch64/a53/include/bsp/irq.h|2 +- bsps/arm/beagle/irq/irq.c | 48 +- bsps/arm/csb336/irq/irq.c | 50 +- bsps/arm/csb337/irq/irq.c | 48 +- bsps/arm/edb7312/irq/irq.c| 50 +- bsps/arm/gumstix/irq/irq.c| 48 +- bsps/arm/lpc24xx/irq/irq.c| 48 +- bsps/arm/lpc32xx/irq/irq.c| 50 +- bsps/arm/raspberrypi/include/bsp/irq.h| 26 + bsps/arm/raspberrypi/irq/irq.c| 59 +- bsps/arm/rtl22xx/irq/irq.c| 48 +- bsps/arm/shared/irq/irq-armv7m.c | 48 +- bsps/arm/smdk2410/irq/irq.c | 48 +- bsps/arm/tms570/irq/irq.c | 48 +- bsps/i386/shared/irq/irq.c| 53 +- bsps/include/bsp/irq-generic.h| 436 ++- bsps/include/dev/irq/arm-gic-irq.h|7 +- bsps/lm32/shared/irq/irq.c| 48 +- bsps/m68k/genmcf548x/include/bsp/irq.h|8 + bsps/m68k/genmcf548x/irq/irq.c| 188 +- bsps/mips/shared/irq/irq.c| 48 +- bsps/powerpc/gen5200/irq/irq.c| 52 +- bsps/powerpc/gen83xx/irq/irq.c| 52 +- bsps/powerpc/mpc55xxevb/start/irq.c | 48 +- bsps/powerpc/mpc8260ads/irq/irq.c | 50 +- bsps/powerpc/psim/irq/irq_init.c
[PATCH v3 04/42] rtems: Add rtems_interrupt_raise()
Add rtems_interrupt_raise_on(). Document the currently not implemented
rtems_interrupt_clear(). Remove the not implemented and badly named
rtems_interrupt_cause() directive.
Update #3269.
---
cpukit/include/rtems/rtems/intr.h | 162 +++---
1 file changed, 125 insertions(+), 37 deletions(-)
diff --git a/cpukit/include/rtems/rtems/intr.h
b/cpukit/include/rtems/rtems/intr.h
index 178cf342df..7663541adc 100644
--- a/cpukit/include/rtems/rtems/intr.h
+++ b/cpukit/include/rtems/rtems/intr.h
@@ -54,6 +54,7 @@
#ifndef _RTEMS_RTEMS_INTR_H
#define _RTEMS_RTEMS_INTR_H
+#include
#include
#include
#include
@@ -99,7 +100,7 @@ typedef ISR_Handler rtems_isr;
* @ingroup RTEMSAPIClassicIntr
*
* @brief Interrupt service routines installed by rtems_interrupt_catch() shall
- * have this function pointer type.
+ * have this type.
*/
#if CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE
typedef ISR_Handler_entry rtems_isr_entry;
@@ -502,42 +503,6 @@ rtems_status_code rtems_interrupt_catch(
*/
#define rtems_interrupt_is_in_progress() _ISR_Is_in_progress()
-/* Generated from spec:/rtems/intr/if/cause */
-
-/**
- * @ingroup RTEMSAPIClassicIntr
- *
- * @brief Causes the interrupt.
- *
- * @param _vector is the vector number of the interrupt to cause.
- *
- * @par Constraints
- * @parblock
- * The following constraints apply to this directive:
- *
- * * The directive is not implemented.
- * @endparblock
- */
-#define rtems_interrupt_cause( _vector ) do { } while ( 0 )
-
-/* Generated from spec:/rtems/intr/if/clear */
-
-/**
- * @ingroup RTEMSAPIClassicIntr
- *
- * @brief Clears the interrupt.
- *
- * @param _vector is the vector number of the interrupt to clear.
- *
- * @par Constraints
- * @parblock
- * The following constraints apply to this directive:
- *
- * * The directive is not implemented.
- * @endparblock
- */
-#define rtems_interrupt_clear( _vector ) do { } while ( 0 )
-
/* Generated from spec:/rtems/intr/if/lock-initialize */
/**
@@ -909,6 +874,129 @@ rtems_status_code rtems_interrupt_catch(
#define RTEMS_INTERRUPT_LOCK_REFERENCE( _designator, _target ) \
ISR_LOCK_REFERENCE( _designator, _target )
+/* Generated from spec:/rtems/intr/if/raise */
+
+/**
+ * @ingroup RTEMSAPIClassicIntr
+ *
+ * @brief Raises the interrupt vector.
+ *
+ * @param vector is the number of the interrupt vector to raise.
+ *
+ * @retval ::RTEMS_SUCCESSFUL The requested operation was successful.
+ *
+ * @retval ::RTEMS_INVALID_ID There was no interrupt vector associated with the
+ * number specified by ``vector``.
+ *
+ * @retval ::RTEMS_UNSATISFIED The request to raise the interrupt vector has
+ * not been satisfied.
+ *
+ * @par Notes
+ * The rtems_interrupt_get_attributes() directive may be used to check if an
+ * interrupt vector can be raised.
+ *
+ * @par Constraints
+ * @parblock
+ * The following constraints apply to this directive:
+ *
+ * * The directive may be called from within interrupt context.
+ *
+ * * The directive may be called from within device driver initialization
+ * context.
+ *
+ * * The directive may be called from within task context.
+ *
+ * * The directive will not cause the calling task to be preempted.
+ * @endparblock
+ */
+rtems_status_code rtems_interrupt_raise( rtems_vector_number vector );
+
+/* Generated from spec:/rtems/intr/if/raise-on */
+
+/**
+ * @ingroup RTEMSAPIClassicIntr
+ *
+ * @brief Raises the interrupt vector on the processor.
+ *
+ * @param vector is the number of the interrupt vector to raise.
+ *
+ * @param cpu_index is the index of the target processor of the interrupt
+ * vector to raise.
+ *
+ * @retval ::RTEMS_SUCCESSFUL The requested operation was successful.
+ *
+ * @retval ::RTEMS_INVALID_ID There was no interrupt vector associated with the
+ * number specified by ``vector``.
+ *
+ * @retval ::RTEMS_NOT_CONFIGURED The processor specified by ``cpu_index`` was
+ * not configured to be used by the application.
+ *
+ * @retval ::RTEMS_INCORRECT_STATE The processor specified by ``cpu_index`` was
+ * configured to be used by the application, however, it was not online.
+ *
+ * @retval ::RTEMS_UNSATISFIED The request to raise the interrupt vector has
+ * not been satisfied.
+ *
+ * @par Notes
+ * The rtems_interrupt_get_attributes() directive may be used to check if an
+ * interrupt vector can be raised on a processor.
+ *
+ * @par Constraints
+ * @parblock
+ * The following constraints apply to this directive:
+ *
+ * * The directive may be called from within interrupt context.
+ *
+ * * The directive may be called from within device driver initialization
+ * context.
+ *
+ * * The directive may be called from within task context.
+ *
+ * * The directive will not cause the calling task to be preempted.
+ * @endparblock
+ */
+rtems_status_code rtems_interrupt_raise_on(
+ rtems_vector_number vector,
+ uint32_tcpu_index
+);
+
+/* Generated from spec:/rtems/intr/if/clear */
+
+/**
+ * @ingroup
[PATCH v3 06/42] rtems: Add rtems_interrupt_get_attributes()
Add a directive to query the attributes of an interrupt vector. This
can be used for generic tests and system diagnostics.
Update #3269.
---
cpukit/include/rtems/irq-extension.h | 207 +++
1 file changed, 207 insertions(+)
diff --git a/cpukit/include/rtems/irq-extension.h
b/cpukit/include/rtems/irq-extension.h
index 5f24fb502e..81de54d334 100644
--- a/cpukit/include/rtems/irq-extension.h
+++ b/cpukit/include/rtems/irq-extension.h
@@ -419,6 +419,213 @@ rtems_status_code rtems_interrupt_set_affinity(
const cpu_set_t*affinity
);
+/* Generated from spec:/rtems/intr/if/signal-variant */
+
+/**
+ * @ingroup RTEMSAPIClassicIntr
+ *
+ * @brief This enumeration provides interrupt trigger signal variants.
+ */
+typedef enum {
+ /**
+ * @brief This interrupt signal variant indicates that the interrupt trigger
+ * signal is unspecified.
+ */
+ RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL,
+
+ /**
+ * @brief This interrupt signal variant indicates that the interrupt cannot
be
+ * triggered by a signal.
+ */
+ RTEMS_INTERRUPT_NO_SIGNAL,
+
+ /**
+ * @brief This interrupt signal variant indicates that the interrupt is
+ * triggered by a low level signal.
+ */
+ RTEMS_INTERRUPT_SIGNAL_LEVEL_LOW,
+
+ /**
+ * @brief This interrupt signal variant indicates that the interrupt is
+ * triggered by a high level signal.
+ */
+ RTEMS_INTERRUPT_SIGNAL_LEVEL_HIGH,
+
+ /**
+ * @brief This interrupt signal variant indicates that the interrupt is
+ * triggered by a falling edge signal.
+ */
+ RTEMS_INTERRUPT_SIGNAL_EDGE_FALLING,
+
+ /**
+ * @brief This interrupt signal variant indicates that the interrupt is
+ * triggered by a raising edge signal.
+ */
+ RTEMS_INTERRUPT_SIGNAL_EDGE_RAISING
+} rtems_interrupt_signal_variant;
+
+/* Generated from spec:/rtems/intr/if/attributes */
+
+/**
+ * @ingroup RTEMSAPIClassicIntr
+ *
+ * @brief This structure provides the attributes of an interrupt vector.
+ *
+ * The rtems_interrupt_get_attributes() directive may be used to obtain the
+ * attributes of an interrupt vector.
+ */
+typedef struct {
+ /**
+ * @brief This member is true, if the interrupt vector is maskable by
+ * rtems_interrupt_local_disable(), otherwise it is false.
+ *
+ * Interrupt vectors which are not maskable by
rtems_interrupt_local_disable()
+ * should be used with care since they cannot use most operating system
+ * services.
+ */
+ bool is_maskable;
+
+ /**
+ * @brief This member is true, if the interrupt vector can be enabled by
+ * rtems_interrupt_vector_enable(), otherwise it is false.
+ *
+ * When an interrupt vector can be enabled, this means that the enabled state
+ * can always be changed from disabled to enabled. For an interrupt vector
+ * which can be enabled it follows that it may be enabled.
+ */
+ bool can_enable;
+
+ /**
+ * @brief This member is true, if the interrupt vector may be enabled by
+ * rtems_interrupt_vector_enable(), otherwise it is false.
+ *
+ * When an interrupt vector may be enabled, this means that the enabled state
+ * may be changed from disabled to enabled. The requested enabled state
change
+ * should be checked by rtems_interrupt_vector_is_enabled(). Some interrupt
+ * vectors may be optionally available and cannot be enabled on a particular
+ * target.
+ */
+ bool maybe_enable;
+
+ /**
+ * @brief This member is true, if the interrupt vector can be disabled by
+ * rtems_interrupt_vector_disable(), otherwise it is false.
+ *
+ * When an interrupt vector can be disabled, this means that the enabled
state
+ * can be changed from enabled to disabled. For an interrupt vector which
can
+ * be disabled it follows that it may be disabled.
+ */
+ bool can_disable;
+
+ /**
+ * @brief This member is true, if the interrupt vector may be disabled by
+ * rtems_interrupt_vector_disable(), otherwise it is false.
+ *
+ * When an interrupt vector may be disabled, this means that the enabled
state
+ * may be changed from enabled to disabled. The requested enabled state
change
+ * should be checked by rtems_interrupt_vector_is_enabled(). Some interrupt
+ * vectors may be always enabled and cannot be disabled on a particular
target.
+ */
+ bool maybe_disable;
+
+ /**
+ * @brief This member is true, if the interrupt vector can be raised by
+ * rtems_interrupt_raise(), otherwise it is false.
+ */
+ bool can_raise;
+
+ /**
+ * @brief This member is true, if the interrupt vector can be raised on a
+ * processor by rtems_interrupt_raise_on(), otherwise it is false.
+ */
+ bool can_raise_on;
+
+ /**
+ * @brief This member is true, if the interrupt vector can be cleared by
+ * rtems_interrupt_clear(), otherwise it is false.
+ */
+ bool can_clear;
+
+ /**
+ * @brief This member is true, if the pending status of the interrupt
+ * associated with the interrupt vector is cleared by an
[PATCH v3 02/42] bsps/irq: Canonicalize get/set affinity errors
Bring the error conditions and status in line with
rtems_task_get_affinity() and rtems_task_set_affinity().
Update #3269.
---
bsps/shared/irq/irq-affinity.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/bsps/shared/irq/irq-affinity.c b/bsps/shared/irq/irq-affinity.c
index f750d6b174..d2214cf6ec 100644
--- a/bsps/shared/irq/irq-affinity.c
+++ b/bsps/shared/irq/irq-affinity.c
@@ -47,13 +47,17 @@ rtems_status_code rtems_interrupt_set_affinity(
Processor_mask set;
Processor_mask_Copy_status status;
+ if ( affinity == NULL ) {
+return RTEMS_INVALID_ADDRESS;
+ }
+
if (!bsp_interrupt_is_valid_vector(vector)) {
return RTEMS_INVALID_ID;
}
status = _Processor_mask_From_cpu_set_t(, affinity_size, affinity);
- if (status != PROCESSOR_MASK_COPY_LOSSLESS) {
-return RTEMS_INVALID_SIZE;
+ if ( !_Processor_mask_Is_at_most_partial_loss( status ) ) {
+return RTEMS_INVALID_NUMBER;
}
#if defined(RTEMS_SMP)
@@ -71,6 +75,10 @@ rtems_status_code rtems_interrupt_get_affinity(
Processor_mask set;
Processor_mask_Copy_status status;
+ if ( affinity == NULL ) {
+return RTEMS_INVALID_ADDRESS;
+ }
+
if (!bsp_interrupt_is_valid_vector(vector)) {
return RTEMS_INVALID_ID;
}
--
2.26.2
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 01/42] bsps/irq: Move get/set affinity to separate file
Update #3269.
---
bsps/shared/irq-default-sources.am | 1 +
bsps/shared/irq-sources.am | 1 +
bsps/shared/irq/irq-affinity.c | 90
bsps/shared/irq/irq-generic.c| 52 ---
c/src/lib/libbsp/m68k/genmcf548x/Makefile.am | 1 +
c/src/lib/libbsp/powerpc/ss555/Makefile.am | 1 +
spec/build/bsps/m68k/genmcf548x/obj.yml | 1 +
spec/build/bsps/objirq.yml | 1 +
spec/build/bsps/powerpc/ss555/bspss555.yml | 1 +
9 files changed, 97 insertions(+), 52 deletions(-)
create mode 100644 bsps/shared/irq/irq-affinity.c
diff --git a/bsps/shared/irq-default-sources.am
b/bsps/shared/irq-default-sources.am
index 1163f77bd8..6b4696dd26 100644
--- a/bsps/shared/irq-default-sources.am
+++ b/bsps/shared/irq-default-sources.am
@@ -1,3 +1,4 @@
+librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-affinity.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default.c
librtemsbsp_a_SOURCES +=
../../../../../../bsps/shared/irq/irq-default-handler.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-generic.c
diff --git a/bsps/shared/irq-sources.am b/bsps/shared/irq-sources.am
index a5e8e6ffdf..65c380a2da 100644
--- a/bsps/shared/irq-sources.am
+++ b/bsps/shared/irq-sources.am
@@ -1,3 +1,4 @@
+librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-affinity.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-generic.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-info.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-legacy.c
diff --git a/bsps/shared/irq/irq-affinity.c b/bsps/shared/irq/irq-affinity.c
new file mode 100644
index 00..f750d6b174
--- /dev/null
+++ b/bsps/shared/irq/irq-affinity.c
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief This source file contains the implementation of
+ * rtems_interrupt_get_affinity() and rtems_interrupt_set_affinity().
+ */
+
+/*
+ * Copyright (C) 2017 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+
+#include
+
+rtems_status_code rtems_interrupt_set_affinity(
+ rtems_vector_number vector,
+ size_t affinity_size,
+ const cpu_set_t *affinity
+)
+{
+ Processor_mask set;
+ Processor_mask_Copy_status status;
+
+ if (!bsp_interrupt_is_valid_vector(vector)) {
+return RTEMS_INVALID_ID;
+ }
+
+ status = _Processor_mask_From_cpu_set_t(, affinity_size, affinity);
+ if (status != PROCESSOR_MASK_COPY_LOSSLESS) {
+return RTEMS_INVALID_SIZE;
+ }
+
+#if defined(RTEMS_SMP)
+ bsp_interrupt_set_affinity(vector, );
+#endif
+ return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code rtems_interrupt_get_affinity(
+ rtems_vector_number vector,
+ size_t affinity_size,
+ cpu_set_t *affinity
+)
+{
+ Processor_mask set;
+ Processor_mask_Copy_status status;
+
+ if (!bsp_interrupt_is_valid_vector(vector)) {
+return RTEMS_INVALID_ID;
+ }
+
+#if defined(RTEMS_SMP)
+ bsp_interrupt_get_affinity(vector, );
+#else
+ _Processor_mask_From_index(, 0);
+#endif
+
+ status = _Processor_mask_To_cpu_set_t(, affinity_size, affinity);
+ if (status != PROCESSOR_MASK_COPY_LOSSLESS) {
+return RTEMS_INVALID_SIZE;
+ }
+
+ return RTEMS_SUCCESSFUL;
+}
diff --git a/bsps/shared/irq/irq-generic.c b/bsps/shared/irq/irq-generic.c
index 65971fb1b3..bea6612136 100644
--- a/bsps/shared/irq/irq-generic.c
+++ b/bsps/shared/irq/irq-generic.c
@@ -39,7 +39,6 @@
#include
-#include
#include
#ifdef BSP_INTERRUPT_USE_INDEX_TABLE
@@
Re: libbsd kernel namespace generation
Hello Chris, On 22/07/2021 10:44, Chris Johns wrote: Hello, Libbsd uses the pre-processor to map all the kernel calls into a libbsd kernel name space by prepending _bsd_ to each symbol. The script ... https://git.rtems.org/rtems-libbsd/tree/create-kernel-namespace.sh?h=6-freebsd-12 ... generates the list and the result is pushed into the repo. The symbols need to be regenerated when new sources are added into the `freebsd` tree. The script has a few issues: 1. Objdump does not work on FreeBSD for different archs. 2. Binutils is being removed from FreeBSD base. what would be the alternative? 3. A number of BSPs need to be built to cover all the possible symbols I would like to document the list of BSPs a generate needs to cover. I propose: arm/xilinx_zynq_a9_qemu aarch64/xilinx_versal_lp64_qemu i386/pc686 powerpc/mvme2307 sparc/erc32 Basically if you import code you just have to build a BSP which covers the imported code. Then you use ... Also the documentation says to use `git add -p` to add the changes. How does an interactive add help? git add -p to add only the changes relevant to the imported (or removed or changed) code. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] build: Merge default-by-family into by-variant
Prefix the BSP family name with "bsps/" to make it distinct to the BSP variant names. --- spec/build/bsps/optconsolebaud.yml | 5 + wscript| 10 ++ 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/spec/build/bsps/optconsolebaud.yml b/spec/build/bsps/optconsolebaud.yml index 4b0869beca..0233fdd61b 100644 --- a/spec/build/bsps/optconsolebaud.yml +++ b/spec/build/bsps/optconsolebaud.yml @@ -6,13 +6,10 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: 115200 -default-by-family: -- value: 9600 - families: - - powerpc/motorola_powerpc default-by-variant: - value: 9600 variants: + - bsps/powerpc/motorola_powerpc - m68k/m5484FireEngine - powerpc/hsc_cm01 - powerpc/beatnik diff --git a/wscript b/wscript index fb8ce9292d..bd75de9807 100755 --- a/wscript +++ b/wscript @@ -698,10 +698,12 @@ class OptionItem(Item): if OptionItem._is_variant(default["variants"], variant): value = default["value"] break -for default in self.data["default-by-family"]: -if OptionItem._is_variant(default["families"], family): -value = default["value"] -break +else: +family = "bsps/" + family +for default in self.data["default-by-variant"]: +if OptionItem._is_variant(default["variants"], family): +value = default["value"] +break if value is None: return value if isinstance(value, list): -- 2.26.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 04/41] rtems: Add rtems_interrupt_cause_on()
On 21/07/2021 20:10, Gedare Bloom wrote: One more thing, should we specifically say "on_processor" or something, to make it clear what this means? When I first read the function name, I thought it is "cause on a condition" so I was confused. Another thought with this "cause_on" directive, should we have an opaque type for the cpu_index? In the RTEMS API we use uint32_t currently. I think this is in line with other numbers such as a pending message count. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] build: Add "family/" prefix to BSP familiy enable
On 22/07/2021 10:47, Chris Johns wrote: On 22/7/21 6:37 pm, Sebastian Huber wrote: On 22/07/2021 10:33, Chris Johns wrote: and so the arch part is not really needed. My concern is this type code ... https://git.rtems.org/rtems_waf/tree/rtems.py#n758 that breaks. Is this an issue? I think a single `/` in a BSP or family is cleaner. Why is this an issue? This BSP family stuff is local to the RTEMS build system. Currently. It is about the symmetry of the naming and how it would look from outside. Nothing more. You mean that maybe someone wants to build an application or library for a BSP family? I guess this is currently not supported, but you could do this with the "bsps/powerpc/motorola_powerpc" approach. Yes it could happen and this is where the symmetry and the existing code matters. For example with `bsps/motorola_powerpc` the code can be easily or cleanly extended by looking for `bsps` as an arch and knowing that is a `family`. Otherwise the error is `invalid arch/bsp` and then you need check two lengths etc etc. If you want to add this feature, then you have to update the code anyway. You have to figure out which BSPs belong to a family for example. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] build: Add "family/" prefix to BSP familiy enable
On 22/07/2021 10:33, Chris Johns wrote: and so the arch part is not really needed. My concern is this type code ... https://git.rtems.org/rtems_waf/tree/rtems.py#n758 that breaks. Is this an issue? I think a single `/` in a BSP or family is cleaner. Why is this an issue? This BSP family stuff is local to the RTEMS build system. Currently. It is about the symmetry of the naming and how it would look from outside. Nothing more. You mean that maybe someone wants to build an application or library for a BSP family? I guess this is currently not supported, but you could do this with the "bsps/powerpc/motorola_powerpc" approach. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 20/41] sparc/irq: Implement new interrupt directives
On 22/07/2021 08:43, Chris Johns wrote: On 22/7/21 5:08 am, Sebastian Huber wrote: On 21/07/2021 21:04, Gedare Bloom wrote: On Wed, Jul 21, 2021 at 12:31 PM Sebastian Huber wrote: On 21/07/2021 20:28, Gedare Bloom wrote: Why not throw an error here instead? In production, you wouldn't want this code... The main issue is the bad chip design. If we don't have this code, we can't test the extended interrupts. In production, you want tested code. ok, thanks. My comments are all pretty minor, except for the terminology issues of "cause" but that wording already exists. post the v2 series, but I probably won't review it and you can check it in if no one complains. It's up to you if you want to work a different wording than "cause" -- I prefer "raise" Thanks a lot for the review. Joel, what is your opinion with respect to "cause" vs. "raise"? I think `raise`. Ok, great. I will replace "cause" with "raise" and send a v3 version of the patch set. I think we should remove the unimplemented rtems_interrupt_cause(). -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] build: Add "family/" prefix to BSP familiy enable
On 22/07/2021 08:37, Chris Johns wrote: On 22/7/21 4:20 pm, Sebastian Huber wrote: On 22/07/2021 02:39, Chris Johns wrote: On 22/7/21 5:22 am, Sebastian Huber wrote: BSP family and BSP variant names may be equal. This prefix avoids ambiguity in the enabled-by expressions. --- wscript | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wscript b/wscript index f27dba6831..b7a0412150 100755 --- a/wscript +++ b/wscript @@ -1394,7 +1394,7 @@ def configure_variant(conf, cp, bsp_map, path_list, top_group, variant): conf.env["ENABLE"] = [ get_compiler(conf, cp, variant), arch, - arch_family, + "family/" + arch_family, "bsps/" + arch_family, ... as discussed in the other thread? If you are happy with the change as shown please push. Yes, this is good and matches with our directory layout. I checked it in with this change. We could also merge the default-by-family and default-by-variant lists with this approach, I am not sure. My initial reaction was "yes" but how would different settings for a BSP and a family be handled? I am assuming a BSP variant setting is able to override a family setting. Is that possible if they are merged? Yes, a BSP variant would have higher priority, this is enforced by the search order: for default in self.data["default-by-variant"]: if OptionItem._is_variant(default["variants"], variant): value = default["value"] break for default in self.data["default-by-family"]: if OptionItem._is_variant(default["families"], family): value = default["value"] break for example: diff --git a/spec/build/bsps/optconsolebaud.yml b/spec/build/bsps/optconsolebaud.yml index 4b0869beca..0233fdd61b 100644 --- a/spec/build/bsps/optconsolebaud.yml +++ b/spec/build/bsps/optconsolebaud.yml @@ -6,13 +6,10 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: 115200 -default-by-family: -- value: 9600 - families: - - powerpc/motorola_powerpc default-by-variant: - value: 9600 variants: + - bsps/powerpc/motorola_powerpc Oh I think my patch piece may have been wrong. This has two `/` and so three components. We _must_ have unique family names The BSP family names are just names in an architecture directory, so this rule would be not enforced by the directory layout. and so the arch part is not really needed. My concern is this type code ... https://git.rtems.org/rtems_waf/tree/rtems.py#n758 that breaks. Is this an issue? I think a single `/` in a BSP or family is cleaner. Why is this an issue? This BSP family stuff is local to the RTEMS build system. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] build: Add "family/" prefix to BSP familiy enable
On 22/07/2021 02:39, Chris Johns wrote: On 22/7/21 5:22 am, Sebastian Huber wrote: BSP family and BSP variant names may be equal. This prefix avoids ambiguity in the enabled-by expressions. --- wscript | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wscript b/wscript index f27dba6831..b7a0412150 100755 --- a/wscript +++ b/wscript @@ -1394,7 +1394,7 @@ def configure_variant(conf, cp, bsp_map, path_list, top_group, variant): conf.env["ENABLE"] = [ get_compiler(conf, cp, variant), arch, -arch_family, +"family/" + arch_family, "bsps/" + arch_family, ... as discussed in the other thread? If you are happy with the change as shown please push. Yes, this is good and matches with our directory layout. I checked it in with this change. We could also merge the default-by-family and default-by-variant lists with this approach, for example: diff --git a/spec/build/bsps/optconsolebaud.yml b/spec/build/bsps/optconsolebaud.yml index 4b0869beca..0233fdd61b 100644 --- a/spec/build/bsps/optconsolebaud.yml +++ b/spec/build/bsps/optconsolebaud.yml @@ -6,13 +6,10 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: 115200 -default-by-family: -- value: 9600 - families: - - powerpc/motorola_powerpc default-by-variant: - value: 9600 variants: + - bsps/powerpc/motorola_powerpc - m68k/m5484FireEngine - powerpc/hsc_cm01 - powerpc/beatnik -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] build: Add "family/" prefix to BSP familiy enable
BSP family and BSP variant names may be equal. This prefix avoids ambiguity in the enabled-by expressions. --- wscript | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wscript b/wscript index f27dba6831..b7a0412150 100755 --- a/wscript +++ b/wscript @@ -1394,7 +1394,7 @@ def configure_variant(conf, cp, bsp_map, path_list, top_group, variant): conf.env["ENABLE"] = [ get_compiler(conf, cp, variant), arch, -arch_family, +"family/" + arch_family, arch_bsp, ] -- 2.26.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] build: Add the BSP family to the enable set
On 21/07/2021 21:05, Gedare Bloom wrote:
The problem is that one BSP which supports SMP "riscv/griscv" is identical to
the family "riscv/griscv" which contains BSPs which do not support SMP
("riscv/grv32i" and riscv/grv32im").
Hmm, tricky. Can the BSPs that do not support SMP disable SMP in the BSP
specific config, ie override/specialise in the BSP?
Or, can we avoid having duplication between BSP names and family names?
Yes, good idea. We could use a "family/" prefix for example
("family//").
--
embedded brains GmbH
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
https://embedded-brains.de/datenschutzerklaerung/
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 20/41] sparc/irq: Implement new interrupt directives
On 21/07/2021 21:04, Gedare Bloom wrote: On Wed, Jul 21, 2021 at 12:31 PM Sebastian Huber wrote: On 21/07/2021 20:28, Gedare Bloom wrote: Why not throw an error here instead? In production, you wouldn't want this code... The main issue is the bad chip design. If we don't have this code, we can't test the extended interrupts. In production, you want tested code. ok, thanks. My comments are all pretty minor, except for the terminology issues of "cause" but that wording already exists. post the v2 series, but I probably won't review it and you can check it in if no one complains. It's up to you if you want to work a different wording than "cause" -- I prefer "raise" Thanks a lot for the review. Joel, what is your opinion with respect to "cause" vs. "raise"? -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 20/41] sparc/irq: Implement new interrupt directives
On 21/07/2021 20:28, Gedare Bloom wrote: Why not throw an error here instead? In production, you wouldn't want this code... The main issue is the bad chip design. If we don't have this code, we can't test the extended interrupts. In production, you want tested code. +rtems_interrupt_lock_context lock_context; + +/* + * This is a very dangerous operation and should only be used for test + * software. We may accidentally clear the pending state set by + * peripherals with this read-modify-write operation. + */ +LEON3_IRQCTRL_ACQUIRE(_context); +LEON3_IrqCtrl_Regs->ipend |= bit; +LEON3_IRQCTRL_RELEASE(_context); + } + + return RTEMS_SUCCESSFUL; } -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 19/41] bsps/irq: Implement new directives for GICv2/3
On 21/07/2021 20:25, Gedare Bloom wrote: As far as I'm aware, SGIs can be enabled or disabled using GICD_ISENABLER0 just like PPI or SPI interrupts for both GICv2 and GICv3. Section 3.1.2 of the GICv2 architecture spec (IHI0048B) references this, though I have seen implementations where certain SGI and PPI interrupts are hard-wired enabled or disabled and that state can't be changed (which is also covered in this section). Ok, on Qemu and the i.MX7D the SGI are always enabled. I would keep the attributes like this until we have a system which is different. Should a comment be added that says this? Yes, in case someone else comes along to add support for a system that is different, it will help to give them some pointers. I addressed this with new attributes in the v2 patch versions: https://lists.rtems.org/pipermail/devel/2021-July/068276.html -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 13/41] bsps/irq: Add rtems_interrupt_get_attributes()
On 21/07/2021 20:14, Gedare Bloom wrote:
+ memset( attributes, 0, sizeof( *attributes ) );
+
+ if ( !bsp_interrupt_is_valid_vector( vector ) ) {
+return RTEMS_INVALID_ID;
+ }
I think do the error checking first, before changing the out parameters?
Some users ignore return values. This way they get at least a
deterministic result from the directive. See:
https://lists.rtems.org/pipermail/devel/2021-March/065840.html
--
embedded brains GmbH
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
https://embedded-brains.de/datenschutzerklaerung/
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 06/41] rtems: Add rtems_interrupt_get_attributes()
On 21/07/2021 20:00, Gedare Bloom wrote: + /** + * @brief This member is true, if the interrupt vector may be enabled by + * rtems_interrupt_vector_enable(), otherwise it is false. + * + * When an interrupt vector may be enabled, this means that the enabled state + * may be changed from disabled to enabled and from enabled to enabled. The s/may/might It is more proper to say "might" when something "might not". "may" and "can" are close synonyms, but "maybe" is closer to "might" in usage. English is still terrible. For the tests we need two variants. One (currently "can") for which it is certain that the operation is successful. Another one (currently "maybe") for which the the operation could be successful or unsatisfied. For the "may_be_triggered_by_message" I would like to express that messages can trigger the interrupt, however, there may be also other triggers like signals or software. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 05/41] rtems: Generate
On 21/07/2021 19:50, Gedare Bloom wrote: /* - * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette. We lose some kind of historical record / attribution here. I wonder if, based on the other discussion about sponsor attribution, there should be something in the generated header for any non-copyright attribution (e.g., if someone wants their authorship reflected)? I don't think it matters so much. Those three guys have their contributions well-reflected in other parts of RTEMS. The concept of the interrupt manager extension API is based on a mailing list discussion. From my point of view there is no copyrightable content from these three persons in the header file. With respect to the attribution, I would be in favour of a general RTEMS contributors file. We already have something like this in "c/ACKNOWLEDGEMENTS", but it is not up to date. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 04/41] rtems: Add rtems_interrupt_cause_on()
On 21/07/2021 19:43, Gedare Bloom wrote: Before we bake this into the API forever, I want to ask if "cause" is the right word to use here? Often, "interrupt cause" is thought of as a noun to mean what caused the interrupt, while the verb is usually "raise" or post, trigger, etc. Because "cause" is both a noun and a verb that mean something in this context, it may be better to use a different verb. English is pretty much terrible. I don't have a major problem with sticking to "cause" but thought I'd bring this up. I just used the existing (not implemented) directive. We can also use rtems_interrupt_raise() (similar to the signal raise()). In this case we should remove rtems_interrupt_cause(). -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 00/41] Document, enhance, and test Interrupt Manager Extension
Hello, are there any comments with respect to the API additions and the documentation changes in general? -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH rtems] bsps/imxrt: Add attribution in file headers
On 21/07/2021 02:46, Chris Johns wrote: On 21/7/21 6:47 am, Gedare Bloom wrote: This seems fine to me. We don't have any standard way to document this kind of attribution. However, we have had individual authors add their names below their company's copyright. It might make sense to put the sponsorship part beneath the copyright of the sponsored company/person? Make sense. The copyright block should be limited to just copyrights and sponsor acknowledgements should in a separate block, maybe after the license block. Yes, I also think it should be outside the license comment block. Not a big deal, but it might help for some kind of consistent guidance if we do this more in the future. I think we need some guidelines. I do not agree with URL links, email addresses, phone numbers or street addreses appearing in the source. I also think a sponsor acknowledgement is never updated or changed even if a company changes name. What I am not sure about is the areas of the source we allow this to happen in, ie score ...? We could add some text here: https://docs.rtems.org/branches/master/eng/coding-file-hdr.html -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] bsp: Remove fatal from exit(0). Add extended heap error output
Hello Chris,
thanks, this is a nice improvement.
On 21/07/2021 07:17, chr...@rtems.org wrote:
--- a/bsps/shared/start/bspfatal-default.c
+++ b/bsps/shared/start/bspfatal-default.c
@@ -22,15 +22,24 @@ void bsp_fatal_extension(
{
#if BSP_VERBOSE_FATAL_EXTENSION
Thread_Control *executing;
+const char* TYPE = "*** FATAL ***\n";
+const char* type = "fatal";
+
+if ( source == RTEMS_FATAL_SOURCE_EXIT ) {
+ TYPE = "";
It would be good to still have a unique pattern which starts the fatal
extension message. The "***" is also used for the test begin/end
marker. What about "*** SYSTEM TERMINATED ***"?
--
embedded brains GmbH
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
https://embedded-brains.de/datenschutzerklaerung/
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] Fixes for TMS570 BSP
On 16/07/2021 13:59, Robin Müller wrote: I think this patch was forgotten. Pushing it up :-) Thanks, I checked it in. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] STM32H7 ethernet pin corrections
On 16/07/2021 14:32, Robin Mueller wrote: These patches were submitted a few months ago, but it was found out that the default-by-family: [] were missing in the GPIO .yml lines. This was fixed in this patch. This patch accounts for different pins for the ETH peripheral on STM32H7 devices. For example, the Nucleo H743ZI has slightly different pins than other STM32H7 boards. Thanks, I checked it in. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] build: Add the BSP family to the enable set
On 15/07/2021 08:19, Sebastian Huber wrote:
This makes it possible to use the BSP family in expressions of the enabled-by
attribute.
---
wscript | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/wscript b/wscript
index 487951fdba..1331ae149e 100755
--- a/wscript
+++ b/wscript
@@ -1387,7 +1387,12 @@ def configure_variant(conf, cp, bsp_map, path_list,
top_group, variant):
# For the enabled-by evaluation we have to use the base BSP defined by the
# build specification and not the BSP name provided by the user.
-conf.env["ENABLE"] = [get_compiler(conf, cp, variant), arch, arch_bsp]
+conf.env["ENABLE"] = [
+get_compiler(conf, cp, variant),
+arch,
+arch_family,
+arch_bsp,
+]
conf.env["TOP"] = conf.path.abspath()
conf.env["TOPGROUP"] = top_group
This actually broke some riscv BSPs which do not support SMP. We have
cat spec/build/cpukit/optsmp.yml
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- get-boolean: null
- env-enable: null
- define-condition: null
build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant: []
description: |
Enable the Symmetric Multiprocessing (SMP) support
enabled-by:
- arm/altcycv_devkit
- arm/fvp_cortex_r52
- arm/imx7
- arm/raspberrypi2
- arm/realview_pbx_a9_qemu
- arm/xilinx_zynq_a9_qemu
- arm/xilinx_zynqmp_ultra96
- arm/xilinx_zynq_zc702
- arm/xilinx_zynq_zc706
- arm/xilinx_zynq_zedboard
- powerpc/qoriq_e500
- powerpc/qoriq_e6500_32
- powerpc/qoriq_e6500_64
- riscv/griscv
- riscv/grv32imac
- riscv/grv32imafdc
- riscv/rv32iac
- riscv/rv32imac
- riscv/rv32imafc
- riscv/rv32imafd
- riscv/rv32imafdc
- riscv/rv64imac
- riscv/rv64imac_medany
- riscv/rv64imafd
- riscv/rv64imafdc
- riscv/rv64imafdc_medany
- riscv/rv64imafd_medany
- sparc/erc32
- sparc/gr712rc
- sparc/gr740
- sparc/leon3
links: []
name: RTEMS_SMP
type: build
The problem is that one BSP which supports SMP "riscv/griscv" is
identical to the family "riscv/griscv" which contains BSPs which do not
support SMP ("riscv/grv32i" and riscv/grv32im").
--
embedded brains GmbH
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
https://embedded-brains.de/datenschutzerklaerung/
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
Re: Help with RTEMS Tester Results for uC5282
Hello, On 20/07/2021 00:43, gerberh...@gmail.com wrote: Dr. Bloom mentioned that some of these results could likely be due to flawed TLS implementation of m68k. this could be also an issue with the linker command file. If I can run the test myself on Qemu I could try to debug the sptls02. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] bsp/leon3: Remove include form
The header file contains a lot of implementation details. Hide them
from .
---
bsps/sparc/leon3/btimer/btimer.c | 2 +-
bsps/sparc/leon3/console/console.c | 1 +
bsps/sparc/leon3/include/bsp.h | 1 -
bsps/sparc/leon3/include/tm27.h| 3 +++
bsps/sparc/leon3/start/bspclean.c | 2 ++
bsps/sparc/leon3/start/bspdelay.c | 1 +
6 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/bsps/sparc/leon3/btimer/btimer.c b/bsps/sparc/leon3/btimer/btimer.c
index 40bdeb87bb..9e9f2b02fc 100644
--- a/bsps/sparc/leon3/btimer/btimer.c
+++ b/bsps/sparc/leon3/btimer/btimer.c
@@ -18,7 +18,7 @@
*/
-#include
+#include
#include
#if defined(RTEMS_MULTIPROCESSING)
diff --git a/bsps/sparc/leon3/console/console.c
b/bsps/sparc/leon3/console/console.c
index d5fff88d18..153907840f 100644
--- a/bsps/sparc/leon3/console/console.c
+++ b/bsps/sparc/leon3/console/console.c
@@ -28,6 +28,7 @@
#include
#include
+#include
#include
#include
#include
diff --git a/bsps/sparc/leon3/include/bsp.h b/bsps/sparc/leon3/include/bsp.h
index 850220d70d..d47f5d2cdf 100644
--- a/bsps/sparc/leon3/include/bsp.h
+++ b/bsps/sparc/leon3/include/bsp.h
@@ -32,7 +32,6 @@
#include
#include
-#include
#include
#ifdef __cplusplus
diff --git a/bsps/sparc/leon3/include/tm27.h b/bsps/sparc/leon3/include/tm27.h
index 7b73bc4dbd..dda21f558f 100644
--- a/bsps/sparc/leon3/include/tm27.h
+++ b/bsps/sparc/leon3/include/tm27.h
@@ -20,6 +20,9 @@
#ifndef __tm27_h
#define __tm27_h
+#include
+#include
+
/*
* Define the interrupt mechanism for Time Test 27
*
diff --git a/bsps/sparc/leon3/start/bspclean.c
b/bsps/sparc/leon3/start/bspclean.c
index e2dff91888..a818e99631 100644
--- a/bsps/sparc/leon3/start/bspclean.c
+++ b/bsps/sparc/leon3/start/bspclean.c
@@ -23,6 +23,8 @@
#include
#include
+#include
+
void bsp_fatal_extension(
rtems_fatal_source source,
bool always_set_to_false,
diff --git a/bsps/sparc/leon3/start/bspdelay.c
b/bsps/sparc/leon3/start/bspdelay.c
index 938a8bdccb..c4a880be6d 100644
--- a/bsps/sparc/leon3/start/bspdelay.c
+++ b/bsps/sparc/leon3/start/bspdelay.c
@@ -14,6 +14,7 @@
*/
#include
+#include
void rtems_bsp_delay(int usecs)
{
--
2.26.2
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH] cpukit: occured -> occurred
--- cpukit/include/rtems/score/coremsgimpl.h | 8 cpukit/include/rtems/score/corerwlockimpl.h | 2 +- cpukit/include/rtems/score/coresemimpl.h | 2 +- cpukit/include/rtems/score/heapimpl.h| 2 +- cpukit/include/rtems/score/mrspimpl.h| 4 ++-- cpukit/include/rtems/score/objectimpl.h | 8 cpukit/include/rtems/score/profiling.h | 2 +- cpukit/include/rtems/score/protectedheap.h | 2 +- cpukit/libblock/src/bdbuf.c | 2 +- cpukit/libdrvmgr/drvmgr.c| 2 +- cpukit/libdrvmgr/drvmgr_unregister.c | 2 +- cpukit/libfs/src/dosfs/fat.c | 16 cpukit/libfs/src/dosfs/fat_fat_operations.c | 8 cpukit/libfs/src/dosfs/fat_file.c| 20 ++-- cpukit/libfs/src/dosfs/msdos_create.c| 2 +- cpukit/libfs/src/dosfs/msdos_dir.c | 4 ++-- cpukit/libfs/src/dosfs/msdos_file.c | 10 +- cpukit/libfs/src/dosfs/msdos_init.c | 2 +- cpukit/libfs/src/dosfs/msdos_initsupp.c | 2 +- cpukit/libfs/src/dosfs/msdos_misc.c | 18 +- cpukit/score/cpu/mips/cpu_asm.S | 4 ++-- cpukit/score/cpu/nios2/nios2-iic-low-level.S | 4 ++-- cpukit/score/src/heapallocate.c | 2 +- 23 files changed, 64 insertions(+), 64 deletions(-) diff --git a/cpukit/include/rtems/score/coremsgimpl.h b/cpukit/include/rtems/score/coremsgimpl.h index 6f6a01bea6..161cf8f124 100644 --- a/cpukit/include/rtems/score/coremsgimpl.h +++ b/cpukit/include/rtems/score/coremsgimpl.h @@ -261,7 +261,7 @@ Status_Control _CORE_message_queue_Broadcast( * @retval STATUS_MESSAGE_INVALID_SIZE The message size was too big. * @retval STATUS_TOO_MANY No message buffers were available. * @retval STATUS_MESSAGE_QUEUE_WAIT_IN_ISR The caller is in an ISR, do not block! - * @retval STATUS_TIMEOUT A timeout occured. + * @retval STATUS_TIMEOUT A timeout occurred. */ Status_Control _CORE_message_queue_Submit( CORE_message_queue_Control *the_message_queue, @@ -298,7 +298,7 @@ Status_Control _CORE_message_queue_Submit( * * @retval STATUS_SUCCESSFUL The message was successfully seized from the message queue. * @retval STATUS_UNSATISFIED Wait was set to false and there is currently no pending message. - * @retval STATUS_TIMEOUT A timeout occured. + * @retval STATUS_TIMEOUT A timeout occurred. * * @note Returns message priority via return area in TCB. * @@ -351,7 +351,7 @@ void _CORE_message_queue_Insert_message( * @retval STATUS_MESSAGE_INVALID_SIZE The message size was too big. * @retval STATUS_TOO_MANY No message buffers were available. * @retval STATUS_MESSAGE_QUEUE_WAIT_IN_ISR The caller is in an ISR, do not block! - * @retval STATUS_TIMEOUT A timeout occured. + * @retval STATUS_TIMEOUT A timeout occurred. */ RTEMS_INLINE_ROUTINE Status_Control _CORE_message_queue_Send( CORE_message_queue_Control *the_message_queue, @@ -387,7 +387,7 @@ RTEMS_INLINE_ROUTINE Status_Control _CORE_message_queue_Send( * @retval STATUS_MESSAGE_INVALID_SIZE The message size was too big. * @retval STATUS_TOO_MANY No message buffers were available. * @retval STATUS_MESSAGE_QUEUE_WAIT_IN_ISR The caller is in an ISR, do not block! - * @retval STATUS_TIMEOUT A timeout occured. + * @retval STATUS_TIMEOUT A timeout occurred. */ RTEMS_INLINE_ROUTINE Status_Control _CORE_message_queue_Urgent( CORE_message_queue_Control *the_message_queue, diff --git a/cpukit/include/rtems/score/corerwlockimpl.h b/cpukit/include/rtems/score/corerwlockimpl.h index b182ebeeeb..dc1f375be6 100644 --- a/cpukit/include/rtems/score/corerwlockimpl.h +++ b/cpukit/include/rtems/score/corerwlockimpl.h @@ -169,7 +169,7 @@ RTEMS_INLINE_ROUTINE void _CORE_RWLock_Release( * @retval STATUS_SUCCESSFUL The RWlock was successfully seized. * @retval STATUS_UNAVAILABLE The RWlock is currently locked for writing * and the calling thread is not willing to wait. - * @retval STATUS_TIMEOUT A timeout occured. + * @retval STATUS_TIMEOUT A timeout occurred. */ Status_Control _CORE_RWLock_Seize_for_reading( diff --git a/cpukit/include/rtems/score/coresemimpl.h b/cpukit/include/rtems/score/coresemimpl.h index 587afc6ff3..40b58cbda7 100644 --- a/cpukit/include/rtems/score/coresemimpl.h +++ b/cpukit/include/rtems/score/coresemimpl.h @@ -193,7 +193,7 @@ RTEMS_INLINE_ROUTINE uint32_t _CORE_semaphore_Get_count( * @retval STATUS_SUCCESSFUL The semaphore was successfully seized. * @retval STATUS_UNSATISFIED The semaphore is currently not free and the * calling thread not willing to wait. - * @retval STATUS_TIMEOUT A timeout occured. + * @retval STATUS_TIMEOUT A timeout occurred. */ RTEMS_INLINE_ROUTINE Status_Control _CORE_semaphore_Seize( CORE_semaphore_Control*the_semaphore, diff --git a/cpukit/include/rtems/score/heapimpl.h b/cpukit/include/rtems/score/heapimpl.h index
[PATCH] sparc: Prefer RTEMS_FATAL_SOURCE_EXCEPTION
Prefer RTEMS_FATAL_SOURCE_EXCEPTION over
INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT since the fatal code
(rtems_exception_frame) provides more context.
---
cpukit/score/cpu/sparc/sparc-bad-trap.S | 14 --
testsuites/sptests/spfatal30/init.c | 37 +++--
testsuites/sptests/spfatal31/init.c | 35 +--
3 files changed, 55 insertions(+), 31 deletions(-)
diff --git a/cpukit/score/cpu/sparc/sparc-bad-trap.S
b/cpukit/score/cpu/sparc/sparc-bad-trap.S
index 2e73a4a7da..c20a97889f 100644
--- a/cpukit/score/cpu/sparc/sparc-bad-trap.S
+++ b/cpukit/score/cpu/sparc/sparc-bad-trap.S
@@ -208,20 +208,6 @@ SYM(_SPARC_Bad_trap):
std %f30, [%l7 + SPARC_EXCEPTION_OFFSET_FP(15)]
#endif
-#if !defined(SPARC_USE_LAZY_FP_SWITCH)
-/*
- * Call
- * _Internal_error( INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT )
- * if necessary.
- */
-cmp %l3, 4
-bne .Lno_fp_disable_trap
- nop
-callSYM(_Internal_error)
- set38, %o0
-.Lno_fp_disable_trap:
-#endif
-
/*
* Call _Terminate( RTEMS_FATAL_SOURCE_EXCEPTION, %l0 ).
*/
diff --git a/testsuites/sptests/spfatal30/init.c
b/testsuites/sptests/spfatal30/init.c
index a02bf062f4..a76fe1f309 100644
--- a/testsuites/sptests/spfatal30/init.c
+++ b/testsuites/sptests/spfatal30/init.c
@@ -22,9 +22,28 @@
const char rtems_test_name[] = "SPFATAL 30";
-#if (CPU_HARDWARE_FP == TRUE && CPU_ALL_TASKS_ARE_FP == FALSE) \
- || SPARC_HAS_FPU == 1
-#define EXPECT_ILLEGAL_USE_OF_FLOATING_POINT_UNIT
+#if ( CPU_HARDWARE_FP == TRUE && CPU_ALL_TASKS_ARE_FP == FALSE ) || \
+ defined(SPARC_USE_LAZY_FP_SWITCH)
+
+#define EXPECTED_FATAL_SOURCE INTERNAL_ERROR_CORE
+
+static bool is_expected_fatal_code( rtems_fatal_code code )
+{
+ return code == INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT;
+}
+
+#elif defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
+
+#define EXPECTED_FATAL_SOURCE RTEMS_FATAL_SOURCE_EXCEPTION
+
+static bool is_expected_fatal_code( rtems_fatal_code code )
+{
+ const rtems_exception_frame *frame;
+
+ frame = (const rtems_exception_frame *) code;
+ return frame->trap == 4;
+}
+
#endif
static volatile double f = 1.0;
@@ -35,7 +54,7 @@ static void Init(rtems_task_argument arg)
f *= 123.456;
-#ifdef EXPECT_ILLEGAL_USE_OF_FLOATING_POINT_UNIT
+#ifdef EXPECTED_FATAL_SOURCE
rtems_test_assert(0);
#else
TEST_END();
@@ -43,7 +62,7 @@ static void Init(rtems_task_argument arg)
#endif
}
-#ifdef EXPECT_ILLEGAL_USE_OF_FLOATING_POINT_UNIT
+#ifdef EXPECTED_FATAL_SOURCE
static void fatal_extension(
rtems_fatal_source source,
bool always_set_to_false,
@@ -51,9 +70,9 @@ static void fatal_extension(
)
{
if (
-source == INTERNAL_ERROR_CORE
+source == EXPECTED_FATAL_SOURCE
&& !always_set_to_false
- && code == INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT
+ && is_expected_fatal_code( code )
) {
TEST_END();
}
@@ -63,11 +82,11 @@ static void fatal_extension(
{ .fatal = fatal_extension }, \
RTEMS_TEST_INITIAL_EXTENSION
-#else /* EXPECT_ILLEGAL_USE_OF_FLOATING_POINT_UNIT */
+#else /* EXPECTED_FATAL_SOURCE */
#define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION
-#endif /* EXPECT_ILLEGAL_USE_OF_FLOATING_POINT_UNIT */
+#endif /* EXPECTED_FATAL_SOURCE */
#define CONFIGURE_APPLICATION_DOES_NOT_NEED_CLOCK_DRIVER
diff --git a/testsuites/sptests/spfatal31/init.c
b/testsuites/sptests/spfatal31/init.c
index 5aab6630dc..782e7632cc 100644
--- a/testsuites/sptests/spfatal31/init.c
+++ b/testsuites/sptests/spfatal31/init.c
@@ -22,8 +22,27 @@
const char rtems_test_name[] = "SPFATAL 31";
-#if SPARC_HAS_FPU == 1
-#define EXPECT_ILLEGAL_USE_OF_FLOATING_POINT_UNIT
+#if defined(SPARC_USE_LAZY_FP_SWITCH)
+
+#define EXPECTED_FATAL_SOURCE INTERNAL_ERROR_CORE
+
+static bool is_expected_fatal_code( rtems_fatal_code code )
+{
+ return code == INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT;
+}
+
+#elif defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
+
+#define EXPECTED_FATAL_SOURCE RTEMS_FATAL_SOURCE_EXCEPTION
+
+static bool is_expected_fatal_code( rtems_fatal_code code )
+{
+ const rtems_exception_frame *frame;
+
+ frame = (const rtems_exception_frame *) code;
+ return frame->trap == 4;
+}
+
#endif
static volatile double f = 1.0;
@@ -49,7 +68,7 @@ static void Init(rtems_task_argument arg)
sc = rtems_task_wake_after(2);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
-#ifdef EXPECT_ILLEGAL_USE_OF_FLOATING_POINT_UNIT
+#ifdef EXPECTED_FATAL_SOURCE
rtems_test_assert(0);
#else
TEST_END();
@@ -57,7 +76,7 @@ static void Init(rtems_task_argument arg)
#endif
}
-#ifdef EXPECT_ILLEGAL_USE_OF_FLOATING_POINT_UNIT
+#ifdef EXPECTED_FATAL_SOURCE
static void fatal_extension(
rtems_fatal_source source,
bool always_set_to_false,
@@ -65,9 +84,9 @@ static void fatal_extension(
)
{
if (
-source == INTERNAL_ERROR_CORE
+source
[PATCH] build: Add the BSP family to the enable set
This makes it possible to use the BSP family in expressions of the enabled-by attribute. --- wscript | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/wscript b/wscript index 487951fdba..1331ae149e 100755 --- a/wscript +++ b/wscript @@ -1387,7 +1387,12 @@ def configure_variant(conf, cp, bsp_map, path_list, top_group, variant): # For the enabled-by evaluation we have to use the base BSP defined by the # build specification and not the BSP name provided by the user. -conf.env["ENABLE"] = [get_compiler(conf, cp, variant), arch, arch_bsp] +conf.env["ENABLE"] = [ +get_compiler(conf, cp, variant), +arch, +arch_family, +arch_bsp, +] conf.env["TOP"] = conf.path.abspath() conf.env["TOPGROUP"] = top_group -- 2.26.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v2] bsps/irq: Implement new directives for GICv2/3
On 14/07/2021 21:37, Kinsey Moore wrote: Looks good, minor nits below. Thanks for the review. I will fixed it before I push the commits. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] build: Prefer variant default value over family
Update #4468. --- wscript | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/wscript b/wscript index 1206c4d882..bba0c1502a 100755 --- a/wscript +++ b/wscript @@ -694,14 +694,14 @@ class OptionItem(Item): def default_value(self, variant, family): value = self.data["default"] -for default in self.data["default-by-family"]: -if OptionItem._is_variant(default["families"], family): -value = default["value"] -break for default in self.data["default-by-variant"]: if OptionItem._is_variant(default["variants"], variant): value = default["value"] break +for default in self.data["default-by-family"]: +if OptionItem._is_variant(default["families"], family): +value = default["value"] +break if value is None: return value if isinstance(value, list): -- 2.26.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] spcoverage: Remove test program
This program contained an optional test case. It was enabled by the
RTEMS_COVERAGE define. The functions under test are not implemented by RTEMS.
---
spec/build/testsuites/sptests/grp.yml| 2 -
spec/build/testsuites/sptests/spcoverage.yml | 19
testsuites/sptests/Makefile.am | 9
testsuites/sptests/configure.ac | 1 -
testsuites/sptests/spcoverage/init.c | 50
testsuites/sptests/spcoverage/spcoverage.doc | 22 -
testsuites/sptests/spcoverage/spcoverage.scn | 3 --
7 files changed, 106 deletions(-)
delete mode 100644 spec/build/testsuites/sptests/spcoverage.yml
delete mode 100644 testsuites/sptests/spcoverage/init.c
delete mode 100644 testsuites/sptests/spcoverage/spcoverage.doc
delete mode 100644 testsuites/sptests/spcoverage/spcoverage.scn
diff --git a/spec/build/testsuites/sptests/grp.yml
b/spec/build/testsuites/sptests/grp.yml
index ac2f6626cd..7e7618789c 100644
--- a/spec/build/testsuites/sptests/grp.yml
+++ b/spec/build/testsuites/sptests/grp.yml
@@ -188,8 +188,6 @@ links:
uid: spconsole01
- role: build-dependency
uid: spcontext01
-- role: build-dependency
- uid: spcoverage
- role: build-dependency
uid: spcpucounter01
- role: build-dependency
diff --git a/spec/build/testsuites/sptests/spcoverage.yml
b/spec/build/testsuites/sptests/spcoverage.yml
deleted file mode 100644
index 74705a976e..00
--- a/spec/build/testsuites/sptests/spcoverage.yml
+++ /dev/null
@@ -1,19 +0,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-build-type: test-program
-cflags: []
-copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-cppflags: []
-cxxflags: []
-enabled-by: true
-features: c cprogram
-includes: []
-ldflags: []
-links: []
-source:
-- testsuites/sptests/spcoverage/init.c
-stlib: []
-target: testsuites/sptests/spcoverage.exe
-type: build
-use-after: []
-use-before: []
diff --git a/testsuites/sptests/Makefile.am b/testsuites/sptests/Makefile.am
index 8a9d968925..07d7ee04e9 100644
--- a/testsuites/sptests/Makefile.am
+++ b/testsuites/sptests/Makefile.am
@@ -753,15 +753,6 @@ spcontext01_CPPFLAGS = $(AM_CPPFLAGS)
$(TEST_FLAGS_spcontext01) \
$(support_includes)
endif
-if TEST_spcoverage
-sp_tests += spcoverage
-sp_screens += spcoverage/spcoverage.scn
-sp_docs += spcoverage/spcoverage.doc
-spcoverage_SOURCES = spcoverage/init.c
-spcoverage_CPPFLAGS = $(AM_CPPFLAGS) $(TEST_FLAGS_spcoverage) \
- $(support_includes) -I$(top_srcdir)/include
-endif
-
if TEST_spcpucounter01
sp_tests += spcpucounter01
sp_screens += spcpucounter01/spcpucounter01.scn
diff --git a/testsuites/sptests/configure.ac b/testsuites/sptests/configure.ac
index 4ca55e6a36..36d4519da3 100644
--- a/testsuites/sptests/configure.ac
+++ b/testsuites/sptests/configure.ac
@@ -121,7 +121,6 @@ RTEMS_TEST_CHECK([spconfig01])
RTEMS_TEST_CHECK([spconfig02])
RTEMS_TEST_CHECK([spconsole01])
RTEMS_TEST_CHECK([spcontext01])
-RTEMS_TEST_CHECK([spcoverage])
RTEMS_TEST_CHECK([spcpucounter01])
RTEMS_TEST_CHECK([spcpuset01])
RTEMS_TEST_CHECK([spcxx01])
diff --git a/testsuites/sptests/spcoverage/init.c
b/testsuites/sptests/spcoverage/init.c
deleted file mode 100644
index 7c8e509d74..00
--- a/testsuites/sptests/spcoverage/init.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * COPYRIGHT (c) 1989-2012.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "tmacros.h"
-
-const char rtems_test_name[] = "SPCOVERAGE";
-
-/* forward declarations to avoid warnings */
-rtems_task Init(rtems_task_argument argument);
-
-rtems_task Init(
- rtems_task_argument ignored
-)
-{
- TEST_BEGIN();
-
- puts( "Init - If coverage enabled, call coverage marker methods" );
- #if defined(RTEMS_COVERAGE)
-start_coverage();
-end_coverage();
- #endif
-
- TEST_END();
- rtems_test_exit(0);
-}
-
-/* configuration information */
-
-#define CONFIGURE_APPLICATION_NEEDS_SIMPLE_CONSOLE_DRIVER
-#define CONFIGURE_APPLICATION_DOES_NOT_NEED_CLOCK_DRIVER
-
-#define CONFIGURE_MAXIMUM_TASKS 1
-#define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION
-
-#define CONFIGURE_RTEMS_INIT_TASKS_TABLE
-
-#define CONFIGURE_INIT
-#include
-
-/* global variables */
diff --git a/testsuites/sptests/spcoverage/spcoverage.doc
b/testsuites/sptests/spcoverage/spcoverage.doc
deleted file mode 100644
index 55b605179f..00
--- a/testsuites/sptests/spcoverage/spcoverage.doc
+++ /dev/null
@@ -1,22 +0,0 @@
-# COPYRIGHT (c) 1989-2009.
-# On-Line Applications Research Corporation (OAR).
-#
-# The license and distribution terms for this file may be
-# found in the file LICENSE in this distribution or at
-# http://www.rtems.org/license/LICENSE.
-#
-
-This file describes the directives
Re: How defines RTEMS_COVERAGE?
On 14/07/2021 14:25, Joel Sherrill wrote:
On Wed, Jul 14, 2021, 7:15 AM Sebastian Huber
<mailto:sebastian.hu...@embedded-brains.de>> wrote:
Hello,
I had a bit of time to work on the gcov support for RTEMS:
https://gcc.gnu.org/pipermail/gcc-patches/2021-July/575122.html
<https://gcc.gnu.org/pipermail/gcc-patches/2021-July/575122.html>
I tried to add an RTEMS_COVERAGE build option to enable gcov. Then I
noticed that such a define is already used in RTEMS:
testsuites/sptests/spcoverage/init.c: #if defined(RTEMS_COVERAGE)
Who provides this define?
I have no idea what this does. The covoar reports require no special
defines. The most you might do is use -Os to make the analysis easier
since the code is easier to follow when optimising for size.
What does that test even do?
rtems_task Init(
rtems_task_argument ignored
)
{
TEST_BEGIN();
puts( "Init - If coverage enabled, call coverage marker methods" );
#if defined(RTEMS_COVERAGE)
start_coverage();
end_coverage();
#endif
TEST_END();
rtems_test_exit(0);
}
From looking at the git log, the start_coverage() and end_coverage()
were never defined in RTEMS. I guess we can remove this test program.
--
embedded brains GmbH
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
https://embedded-brains.de/datenschutzerklaerung/
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
How defines RTEMS_COVERAGE?
Hello, I had a bit of time to work on the gcov support for RTEMS: https://gcc.gnu.org/pipermail/gcc-patches/2021-July/575122.html I tried to add an RTEMS_COVERAGE build option to enable gcov. Then I noticed that such a define is already used in RTEMS: testsuites/sptests/spcoverage/init.c: #if defined(RTEMS_COVERAGE) Who provides this define? -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2] rtems: Add rtems_interrupt_get_attributes()
Add a directive to query the attributes of an interrupt vector. This
be used for generic tests and system diagnostics.
Update #3269.
---
cpukit/include/rtems/irq-extension.h | 216 +++
1 file changed, 216 insertions(+)
diff --git a/cpukit/include/rtems/irq-extension.h
b/cpukit/include/rtems/irq-extension.h
index 5f24fb502e..af54002902 100644
--- a/cpukit/include/rtems/irq-extension.h
+++ b/cpukit/include/rtems/irq-extension.h
@@ -419,6 +419,222 @@ rtems_status_code rtems_interrupt_set_affinity(
const cpu_set_t*affinity
);
+/* Generated from spec:/rtems/intr/if/signal-variant */
+
+/**
+ * @ingroup RTEMSAPIClassicIntr
+ *
+ * @brief This enumeration provides interrupt trigger signal variants.
+ */
+typedef enum {
+ /**
+ * @brief This interrupt signal variant indicates that the interrupt trigger
+ * signal is unspecified.
+ */
+ RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL,
+
+ /**
+ * @brief This interrupt signal variant indicates that the interrupt cannot
be
+ * triggered by a signal.
+ */
+ RTEMS_INTERRUPT_NO_SIGNAL,
+
+ /**
+ * @brief This interrupt signal variant indicates that the interrupt is
+ * triggered by a low level signal.
+ */
+ RTEMS_INTERRUPT_SIGNAL_LEVEL_LOW,
+
+ /**
+ * @brief This interrupt signal variant indicates that the interrupt is
+ * triggered by a high level signal.
+ */
+ RTEMS_INTERRUPT_SIGNAL_LEVEL_HIGH,
+
+ /**
+ * @brief This interrupt signal variant indicates that the interrupt is
+ * triggered by a falling edge signal.
+ */
+ RTEMS_INTERRUPT_SIGNAL_EDGE_FALLING,
+
+ /**
+ * @brief This interrupt signal variant indicates that the interrupt is
+ * triggered by a raising edge signal.
+ */
+ RTEMS_INTERRUPT_SIGNAL_EDGE_RAISING
+} rtems_interrupt_signal_variant;
+
+/* Generated from spec:/rtems/intr/if/attributes */
+
+/**
+ * @ingroup RTEMSAPIClassicIntr
+ *
+ * @brief This structure provides the attributes of an interrupt vector.
+ *
+ * The rtems_interrupt_get_attributes() directive may be used to obtain the
+ * attributes of an interrupt vector.
+ */
+typedef struct {
+ /**
+ * @brief This member is true, if the interrupt vector is maskable by
+ * rtems_interrupt_local_disable(), otherwise it is false.
+ *
+ * Interrupt vectors which are not maskable by
rtems_interrupt_local_disable()
+ * should be used with care since they cannot use most operating system
+ * services.
+ */
+ bool is_maskable;
+
+ /**
+ * @brief This member is true, if the interrupt vector is always enabled,
+ * otherwise it is false.
+ *
+ * For an always enabled interrupt vector it follows that it can be enabled
and
+ * that it cannot be disabled.
+ */
+ bool always_enabled;
+
+ /**
+ * @brief This member is true, if the interrupt vector can be enabled by
+ * rtems_interrupt_vector_enable(), otherwise it is false.
+ *
+ * When an interrupt vector can be enabled, this means that the enabled state
+ * can always be changed from disabled to enabled. For an interrupt vector
+ * which can be enabled it follows that it may be enabled.
+ */
+ bool can_enable;
+
+ /**
+ * @brief This member is true, if the interrupt vector may be enabled by
+ * rtems_interrupt_vector_enable(), otherwise it is false.
+ *
+ * When an interrupt vector may be enabled, this means that the enabled state
+ * may be changed from disabled to enabled. The requested enabled state
change
+ * should be checked by rtems_interrupt_vector_is_enabled(). Some interrupt
+ * vectors may be optionally avaialable and cannot be enabled on a particular
+ * target.
+ */
+ bool maybe_enable;
+
+ /**
+ * @brief This member is true, if the interrupt vector can be disabled by
+ * rtems_interrupt_vector_disable(), otherwise it is false.
+ *
+ * When an interrupt vector can be disabled, this means that the enabled
state
+ * can be changed from enabled to disabled. For an interrupt vector which
can
+ * be disabled it follows that it may be disabled.
+ */
+ bool can_disable;
+
+ /**
+ * @brief This member is true, if the interrupt vector may be disabled by
+ * rtems_interrupt_vector_disable(), otherwise it is false.
+ *
+ * When an interrupt vector may be disabled, this means that the enabled
state
+ * may be changed from enabled to disabled. The requested enabled state
change
+ * should be checked by rtems_interrupt_vector_is_enabled(). Some interrupt
+ * vectors may be always enabled and cannot be disabled on a particular
target.
+ */
+ bool maybe_disable;
+
+ /**
+ * @brief This member is true, if the interrupt vector can be caused by
+ * rtems_interrupt_cause(), otherwise it is false.
+ */
+ bool can_cause;
+
+ /**
+ * @brief This member is true, if the interrupt vector can be caused on a
+ * processor by rtems_interrupt_cause_on(), otherwise it is false.
+ */
+ bool can_cause_on;
+
+ /**
+ * @brief This member is true,
[PATCH v2] bsps/irq: Implement new directives for GICv2/3
Update #3269.
---
bsps/include/dev/irq/arm-gic-irq.h | 3 +
bsps/shared/dev/irq/arm-gicv2.c| 83 +++
bsps/shared/dev/irq/arm-gicv3.c| 125 +
3 files changed, 180 insertions(+), 31 deletions(-)
diff --git a/bsps/include/dev/irq/arm-gic-irq.h
b/bsps/include/dev/irq/arm-gic-irq.h
index 68e0247fd8..398fd8bceb 100644
--- a/bsps/include/dev/irq/arm-gic-irq.h
+++ b/bsps/include/dev/irq/arm-gic-irq.h
@@ -46,6 +46,9 @@ extern "C" {
#define ARM_GIC_IRQ_SGI_13 13
#define ARM_GIC_IRQ_SGI_14 14
#define ARM_GIC_IRQ_SGI_15 15
+#define ARM_GIC_IRQ_SGI_LAST 15
+
+#define ARM_GIC_IRQ_PPI_LAST 31
#define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE)
diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c
index a1ba5e9112..83422218da 100644
--- a/bsps/shared/dev/irq/arm-gicv2.c
+++ b/bsps/shared/dev/irq/arm-gicv2.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013, 2021 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -69,6 +69,28 @@ rtems_status_code bsp_interrupt_get_attributes(
rtems_interrupt_attributes *attributes
)
{
+ attributes->is_maskable = true;
+ attributes->maybe_enable = true;
+ attributes->maybe_disable = true;
+
+ if ( vector <= ARM_GIC_IRQ_SGI_LAST ) {
+attributes->can_cause = true;
+attributes->can_cause_on = true;
+attributes->cleared_by_acknowledge = true;
+attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL;
+ } else {
+attributes->can_disable = true;
+attributes->can_cause = true;
+attributes->can_clear = true;
+attributes->trigger_signal = RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL;
+
+if ( vector > ARM_GIC_IRQ_PPI_LAST ) {
+ /* SPI */
+ attributes->can_get_affinity = true;
+ attributes->can_set_affinity = true;
+}
+ }
+
return RTEMS_SUCCESSFUL;
}
@@ -77,16 +99,25 @@ rtems_status_code bsp_interrupt_is_pending(
bool *pending
)
{
- bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
- bsp_interrupt_assert(pending != NULL);
- *pending = false;
- return RTEMS_UNSATISFIED;
+ volatile gic_dist *dist = ARM_GIC_DIST;
+
+ *pending = gic_id_is_pending(dist, vector);
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_cause(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
- return RTEMS_UNSATISFIED;
+
+ if (vector <= ARM_GIC_IRQ_SGI_LAST) {
+arm_gic_trigger_sgi(vector, 1U << _SMP_Get_current_processor());
+ } else {
+volatile gic_dist *dist = ARM_GIC_DIST;
+
+gic_id_set_pending(dist, vector);
+ }
+
+ return RTEMS_SUCCESSFUL;
}
#if defined(RTEMS_SMP)
@@ -95,15 +126,27 @@ rtems_status_code bsp_interrupt_cause_on(
uint32_tcpu_index
)
{
- bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
- return RTEMS_UNSATISFIED;
+ if (vector >= 16) {
+return RTEMS_UNSATISFIED;
+ }
+
+ arm_gic_trigger_sgi(vector, 1U << cpu_index);
+ return RTEMS_SUCCESSFUL;
}
#endif
rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
{
+ volatile gic_dist *dist = ARM_GIC_DIST;
+
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
- return RTEMS_UNSATISFIED;
+
+ if (vector <= ARM_GIC_IRQ_SGI_LAST) {
+return RTEMS_UNSATISFIED;
+ }
+
+ gic_id_clear_pending(dist, vector);
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_vector_is_enabled(
@@ -111,10 +154,13 @@ rtems_status_code bsp_interrupt_vector_is_enabled(
bool *enabled
)
{
+ volatile gic_dist *dist = ARM_GIC_DIST;
+
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
bsp_interrupt_assert(enabled != NULL);
- *enabled = false;
- return RTEMS_UNSATISFIED;
+
+ *enabled = gic_id_is_enabled(dist, vector);
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
@@ -207,8 +253,8 @@ BSP_START_TEXT_SECTION void
arm_gic_irq_initialize_secondary_cpu(void)
dist->icdigr[0] = 0x;
#endif
- /* Initialize Peripheral Private Interrupts (PPIs) */
- for (id = 0; id < 32; ++id) {
+ /* Initialize priority of SGIs and PPIs */
+ for (id = 0; id <= ARM_GIC_IRQ_PPI_LAST; ++id) {
gic_id_set_priority(dist, id, PRIORITY_DEFAULT);
}
@@ -300,6 +346,10 @@ rtems_status_code bsp_interrupt_set_affinity(
volatile gic_dist *dist = ARM_GIC_DIST;
uint8_t targets = (uint8_t) _Processor_mask_To_uint32_t(affinity, 0);
+ if ( vector <= ARM_GIC_IRQ_PPI_LAST ) {
+return RTEMS_UNSATISFIED;
+ }
+
gic_id_set_targets(dist, vector, targets);
return RTEMS_SUCCESSFUL;
}
@@ -310,8 +360,13 @@ rtems_status_code bsp_interrupt_get_affinity(
)
{
volatile gic_dist *dist = ARM_GIC_DIST;
- uint8_t targets = gic_id_get_targets(dist, vector);
+ uint8_t targets;
+
+ if ( vector <= ARM_GIC_IRQ_PPI_LAST ) {
+return
Re: [PATCH v2] build: Use BSP family for options
On 14/07/2021 10:44, Chris Johns wrote: Can I add `default-by-family: []` before `default-by-variant` in the spec files? Yes, the attributes should alphabetically sorted. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v2] build: Use BSP family for options
On 14/07/2021 09:21, Chris Johns wrote: Is there a nice way to catch any missing fields and report them? The waf conf is not present and I am not sure if we catch any standard python exception and report them by waf? The current approach is to check the user input (e.g. config.ini) and report configuration errors. For errors in the build specification which is supposed to be maintained by experts you get exceptions. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v2] build: Use BSP family for options
On 14/07/2021 08:51, chr...@rtems.org wrote: @@ -695,12 +692,18 @@ class OptionItem(Item): return True return False -def default_value(self, variant): +def default_value(self, variant, family): value = self.data["default"] for default in self.data["default-by-variant"]: if OptionItem._is_variant(default["variants"], variant): value = default["value"] break +if 'default-by-family' in self.data: +for default in self.data["default-by-family"]: +if 'families' in default: +if OptionItem._is_variant(default["families"], family): +value = default["value"] +break During the discussion of the build items, we agreed that all attributes should be explicit in the items. So, a "default-by-family: []" should be added to all BSP items. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] build: Use BSP family for options
Close #4468.
---
wscript | 51 ---
1 file changed, 28 insertions(+), 23 deletions(-)
diff --git a/wscript b/wscript
index 6626fafb74..357e8918df 100755
--- a/wscript
+++ b/wscript
@@ -203,11 +203,11 @@ class Item(object):
def get_enabled_by(self):
return self.data["enabled-by"]
-def defaults(self, enable, variant):
+def defaults(self, enable, variant, family):
if _is_enabled(enable, self.get_enabled_by()):
for p in self.links():
-p.defaults(enable, variant)
-self.do_defaults(variant)
+p.defaults(enable, variant, family)
+self.do_defaults(variant, family)
def configure(self, conf, cic):
if _is_enabled(conf.env.ENABLE, self.get_enabled_by()):
@@ -223,7 +223,7 @@ class Item(object):
p.build(bld, bic)
self.do_build(bld, bic)
-def do_defaults(self, variant):
+def do_defaults(self, variant, family):
return
def prepare_configure(self, conf, cic):
@@ -592,9 +592,6 @@ class BSPItem(Item):
arch_bsps = bsps.setdefault(data["arch"].strip(), {})
arch_bsps[data["bsp"].strip()] = self
-def prepare_configure(self, conf, cic):
-conf.env.BSP_FAMILY = self.data["family"]
-
def prepare_build(self, bld, bic):
return BuildItemContext(
bic.includes + bld.env.BSP_INCLUDES.split(), [], [], []
@@ -689,16 +686,18 @@ class OptionItem(Item):
super(OptionItem, self).__init__(uid, data)
@staticmethod
-def _is_variant(variants, variant):
+def _is_variant(variants, variant, family):
for pattern in variants:
if re.match(pattern + "$", variant):
return True
+if re.match(pattern + "$", family):
+return True
return False
-def default_value(self, variant):
+def default_value(self, variant, family):
value = self.data["default"]
for default in self.data["default-by-variant"]:
-if OptionItem._is_variant(default["variants"], variant):
+if OptionItem._is_variant(default["variants"], variant, family):
value = default["value"]
break
if value is None:
@@ -709,8 +708,8 @@ class OptionItem(Item):
return value
return self.data["format"].format(value)
-def do_defaults(self, variant):
-value = self.default_value(variant)
+def do_defaults(self, variant, family):
+value = self.default_value(variant, family)
if value is None:
return
description = self.data["description"]
@@ -917,7 +916,7 @@ class OptionItem(Item):
value = cic.cp.getboolean(conf.variant, name)
cic.add_option(name)
except configparser.NoOptionError:
-value = self.default_value(conf.env.ARCH_BSP)
+value = self.default_value(conf.env.ARCH_BSP, conf.env.ARCH_FAMILY)
except ValueError as ve:
conf.fatal(
"Invalid value for configuration option {}: {}".format(name,
ve)
@@ -933,7 +932,7 @@ class OptionItem(Item):
value = cic.cp.get(conf.variant, name)
cic.add_option(name)
except configparser.NoOptionError:
-value = self.default_value(conf.env.ARCH_BSP)
+value = self.default_value(conf.env.ARCH_BSP, conf.env.ARCH_FAMILY)
if value is None:
return value
try:
@@ -952,7 +951,7 @@ class OptionItem(Item):
cic.add_option(name)
value = no_unicode(value)
except configparser.NoOptionError:
-value = self.default_value(conf.env.ARCH_BSP)
+value = self.default_value(conf.env.ARCH_BSP, conf.env.ARCH_FAMILY)
return value
def _script(self, conf, cic, value, arg):
@@ -1365,11 +1364,20 @@ def configure_variant(conf, cp, bsp_map, path_list,
top_group, variant):
conf.setenv(variant)
arch, bsp_name = variant.split("/")
bsp_base = bsp_map.get(bsp_name, bsp_name)
-arch_bsp = arch + "/" + bsp_base
+try:
+bsp_item = bsps[arch][bsp_base]
+except KeyError:
+conf.fatal("No such base BSP: '{}'".format(variant))
+
+bsp_family = self.data["family"]
+arch_bsp = arch + "/" + bsp_base
+arch_family = arch + "/" + bsp_family
conf.env["ARCH"] = arch
conf.env["ARCH_BSP"] = arch_bsp
+conf.env["ARCH_FAMILY"] = arch_family
conf.env["BSP_BASE"] = bsp_base
+conf.env["BSP_FAMILY"] = bsp_family
conf.env["BSP_NAME"] = bsp_name
conf.env["DEST_OS"] = "rtems"
@@ -1384,11 +1392,6 @@ def configure_variant(conf, cp, bsp_map, path_list,
top_group, variant):
cic = ConfigItemContext(cp, path_list)
items[conf.env.TOPGROUP].configure(conf, cic)
-
-try:
-bsp_item = bsps[arch][bsp_base]
-except KeyError:
-
Re: [PATCH 19/41] bsps/irq: Implement new directives for GICv2/3
I_LAST ) {
+ return RTEMS_UNSATISFIED;
+ }
+
gic_id_set_targets(dist, vector, targets);
return RTEMS_SUCCESSFUL;
}
@@ -310,8 +370,13 @@ rtems_status_code bsp_interrupt_get_affinity(
)
{
volatile gic_dist *dist = ARM_GIC_DIST;
- uint8_t targets = gic_id_get_targets(dist, vector);
+ uint8_t targets;
+
+ if ( vector <= ARM_GIC_IRQ_PPI_LAST ) {
+ return RTEMS_UNSATISFIED;
+ }
+ targets = gic_id_get_targets(dist, vector);
_Processor_mask_From_uint32_t(affinity, targets, 0);
return RTEMS_SUCCESSFUL;
}
diff --git a/bsps/shared/dev/irq/arm-gicv3.c
b/bsps/shared/dev/irq/arm-gicv3.c
index 8db3053ffd..211f4d35c4 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -169,6 +169,25 @@ rtems_status_code bsp_interrupt_get_attributes(
rtems_interrupt_attributes *attributes
)
{
+ attributes->is_maskable = true;
+ attributes->can_enable = true;
+
+ if ( vector <= ARM_GIC_IRQ_SGI_LAST ) {
+ attributes->can_cause = true;
+ attributes->can_cause_on = true;
+ attributes->cleared_by_acknowledge = true;
+ } else {
+ attributes->can_disable = true;
+ attributes->can_cause = true;
+ attributes->can_clear = true;
+
+ if ( vector > ARM_GIC_IRQ_PPI_LAST ) {
+ /* SPI */
The actual number of SPI interrupts supported by GICv3 can vary
depending on the configuration
of the IP. This should check that the provided vector is within that range.
Yes, I will change this to
attributes->maybe_enable = true;
I would not do the probing here, since this would require to do it also
in bsp_interrupt_vector_is_valid(). The probing could be done using
bsp_interrupt_vector_enable() and bsp_interrupt_vector_is_enabled().
--
embedded brains GmbH
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
https://embedded-brains.de/datenschutzerklaerung/
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 26/41] bsp/raspberrypi: Add interrupt get/set affinity
Add default implementations for bsp_interrupt_get_affinity() and
bsp_interrupt_set_affinity() which are required to link all tests in SMP
configurations.
Update #3269.
---
bsps/arm/raspberrypi/include/bsp/irq.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/bsps/arm/raspberrypi/include/bsp/irq.h
b/bsps/arm/raspberrypi/include/bsp/irq.h
index a363e7ce90..6801b01d84 100644
--- a/bsps/arm/raspberrypi/include/bsp/irq.h
+++ b/bsps/arm/raspberrypi/include/bsp/irq.h
@@ -25,6 +25,10 @@
#include
#include
+#if defined(RTEMS_SMP)
+#include
+#endif
+
/**
* @defgroup raspberrypi_interrupt Interrrupt Support
*
@@ -74,5 +78,27 @@
#define BSP_IRQ_COUNT (BCM2835_INTC_TOTAL_IRQ)
+#if defined(RTEMS_SMP)
+static inline rtems_status_code bsp_interrupt_set_affinity(
+ rtems_vector_number vector,
+ const Processor_mask *affinity
+)
+{
+ (void) vector;
+ (void) affinity;
+ return RTEMS_UNSATISFIED;
+}
+
+static inline rtems_status_code bsp_interrupt_get_affinity(
+ rtems_vector_number vector,
+ Processor_mask *affinity
+)
+{
+ (void) vector;
+ _Processor_mask_From_index( affinity, 0 );
+ return RTEMS_UNSATISFIED;
+}
+#endif
+
#endif /* ASM */
#endif /* LIBBSP_ARM_RASPBERRYPI_IRQ_H */
--
2.26.2
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 32/41] validation: Test rtems_interrupt_vector_enable()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
testsuites/validation/tc-intr-vector-enable.c | 641 ++
2 files changed, 642 insertions(+)
create mode 100644 testsuites/validation/tc-intr-vector-enable.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 0fbd4d808f..36d2a0f388 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -16,6 +16,7 @@ source:
- testsuites/validation/tc-barrier-release.c
- testsuites/validation/tc-barrier-wait.c
- testsuites/validation/tc-intr-get-attributes.c
+- testsuites/validation/tc-intr-vector-enable.c
- testsuites/validation/tc-intr-vector-is-enabled.c
- testsuites/validation/tc-message-construct-errors.c
- testsuites/validation/tc-object.c
diff --git a/testsuites/validation/tc-intr-vector-enable.c
b/testsuites/validation/tc-intr-vector-enable.c
new file mode 100644
index 00..47f53b4728
--- /dev/null
+++ b/testsuites/validation/tc-intr-vector-enable.c
@@ -0,0 +1,641 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqVectorEnable
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqVectorEnable \
+ * spec:/rtems/intr/req/vector-enable
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqVectorEnable_Pre_Vector_Valid,
+ RtemsIntrReqVectorEnable_Pre_Vector_Invalid,
+ RtemsIntrReqVectorEnable_Pre_Vector_NA
+} RtemsIntrReqVectorEnable_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqVectorEnable_Pre_IsEnabled_Yes,
+ RtemsIntrReqVectorEnable_Pre_IsEnabled_No,
+ RtemsIntrReqVectorEnable_Pre_IsEnabled_NA
+} RtemsIntrReqVectorEnable_Pre_IsEnabled;
+
+typedef enum {
+ RtemsIntrReqVectorEnable_Pre_CanEnable_Yes,
+ RtemsIntrReqVectorEnable_Pre_CanEnable_Maybe,
+ RtemsIntrReqVectorEnable_Pre_CanEnable_No,
+ RtemsIntrReqVectorEnable_Pre_CanEnable_NA
+} RtemsIntrReqVectorEnable_Pre_CanEnable;
+
+typedef enum {
+ RtemsIntrReqVectorEnable_Post_Status_Ok,
+ RtemsIntrReqVectorEnable_Post_Status_InvId,
+ RtemsIntrReqVectorEnable_Post_Status_Unsat,
+ RtemsIntrReqVectorEnable_Post_Status_NA
+} RtemsIntrReqVectorEnable_Post_Status;
+
+typedef enum {
+ RtemsIntrReqVectorEnable_Post_IsEnabled_Nop,
+ RtemsIntrReqVectorEnable_Post_IsEnabled_Yes,
+ RtemsIntrReqVectorEnable_Post_IsEnabled_Maybe,
+ RtemsIntrReqVectorEnable_Post_IsEnabled_NA
+} RtemsIntrReqVectorEnable_Post_IsEnabled;
+
+/**
+ * @brief Test context for spec:/rtems/intr/req/vector-enable test case.
+ */
+typedef struct {
+ /**
+ * @brief If this member is true, then an interrupt occurred.
+ */
+ bool interrupt_occurred;
+
+ /**
+ * @brief This member contains the current vector number.
+
[PATCH 39/41] validation: Test rtems_interrupt_cause_on()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
testsuites/validation/tc-intr-cause-on.c | 710 ++
testsuites/validation/ts-default.h| 12 +-
testsuites/validation/ts-validation-0.c | 2 +-
4 files changed, 723 insertions(+), 2 deletions(-)
create mode 100644 testsuites/validation/tc-intr-cause-on.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index f432b89191..eba0954182 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -16,6 +16,7 @@ source:
- testsuites/validation/tc-barrier-release.c
- testsuites/validation/tc-barrier-wait.c
- testsuites/validation/tc-intr-cause.c
+- testsuites/validation/tc-intr-cause-on.c
- testsuites/validation/tc-intr-clear.c
- testsuites/validation/tc-intr-entry-install.c
- testsuites/validation/tc-intr-entry-remove.c
diff --git a/testsuites/validation/tc-intr-cause-on.c
b/testsuites/validation/tc-intr-cause-on.c
new file mode 100644
index 00..d404a255e7
--- /dev/null
+++ b/testsuites/validation/tc-intr-cause-on.c
@@ -0,0 +1,710 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqCauseOn
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqCauseOn spec:/rtems/intr/req/cause-on
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqCauseOn_Pre_Vector_Valid,
+ RtemsIntrReqCauseOn_Pre_Vector_Invalid,
+ RtemsIntrReqCauseOn_Pre_Vector_NA
+} RtemsIntrReqCauseOn_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqCauseOn_Pre_CPU_Online,
+ RtemsIntrReqCauseOn_Pre_CPU_NotOnline,
+ RtemsIntrReqCauseOn_Pre_CPU_NotConf,
+ RtemsIntrReqCauseOn_Pre_CPU_NA
+} RtemsIntrReqCauseOn_Pre_CPU;
+
+typedef enum {
+ RtemsIntrReqCauseOn_Pre_CanCauseOn_Yes,
+ RtemsIntrReqCauseOn_Pre_CanCauseOn_No,
+ RtemsIntrReqCauseOn_Pre_CanCauseOn_NA
+} RtemsIntrReqCauseOn_Pre_CanCauseOn;
+
+typedef enum {
+ RtemsIntrReqCauseOn_Post_Status_Ok,
+ RtemsIntrReqCauseOn_Post_Status_InvId,
+ RtemsIntrReqCauseOn_Post_Status_NotConf,
+ RtemsIntrReqCauseOn_Post_Status_IncStat,
+ RtemsIntrReqCauseOn_Post_Status_Unsat,
+ RtemsIntrReqCauseOn_Post_Status_NA
+} RtemsIntrReqCauseOn_Post_Status;
+
+typedef enum {
+ RtemsIntrReqCauseOn_Post_Pending_Yes,
+ RtemsIntrReqCauseOn_Post_Pending_No,
+ RtemsIntrReqCauseOn_Post_Pending_NA
+} RtemsIntrReqCauseOn_Post_Pending;
+
+/**
+ * @brief Test context for spec:/rtems/intr/req/cause-on test case.
+ */
+typedef struct {
+ /**
+ * @brief This member contains the count of serviced interrupts.
+ */
+ volatile uint32_t interrupt_count;
+
+ /**
+ * @brief If this member is true, then the interrupt shall be cleared.
+ */
+ bool
[PATCH 37/41] validation: Test rtems_interrupt_clear()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
testsuites/validation/tc-intr-clear.c | 586 ++
2 files changed, 587 insertions(+)
create mode 100644 testsuites/validation/tc-intr-clear.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index fc7b2830e4..c47cd93234 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -16,6 +16,7 @@ source:
- testsuites/validation/tc-barrier-release.c
- testsuites/validation/tc-barrier-wait.c
- testsuites/validation/tc-intr-cause.c
+- testsuites/validation/tc-intr-clear.c
- testsuites/validation/tc-intr-entry-install.c
- testsuites/validation/tc-intr-entry-remove.c
- testsuites/validation/tc-intr-get-attributes.c
diff --git a/testsuites/validation/tc-intr-clear.c
b/testsuites/validation/tc-intr-clear.c
new file mode 100644
index 00..6fc917e2ad
--- /dev/null
+++ b/testsuites/validation/tc-intr-clear.c
@@ -0,0 +1,586 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqClear
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqClear spec:/rtems/intr/req/clear
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqClear_Pre_Vector_Valid,
+ RtemsIntrReqClear_Pre_Vector_Invalid,
+ RtemsIntrReqClear_Pre_Vector_NA
+} RtemsIntrReqClear_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqClear_Pre_CanClear_Yes,
+ RtemsIntrReqClear_Pre_CanClear_No,
+ RtemsIntrReqClear_Pre_CanClear_NA
+} RtemsIntrReqClear_Pre_CanClear;
+
+typedef enum {
+ RtemsIntrReqClear_Post_Status_Ok,
+ RtemsIntrReqClear_Post_Status_InvId,
+ RtemsIntrReqClear_Post_Status_Unsat,
+ RtemsIntrReqClear_Post_Status_NA
+} RtemsIntrReqClear_Post_Status;
+
+typedef enum {
+ RtemsIntrReqClear_Post_Cleared_Yes,
+ RtemsIntrReqClear_Post_Cleared_No,
+ RtemsIntrReqClear_Post_Cleared_NA
+} RtemsIntrReqClear_Post_Cleared;
+
+/**
+ * @brief Test context for spec:/rtems/intr/req/clear test case.
+ */
+typedef struct {
+ /**
+ * @brief This member contains the count of serviced interrupts.
+ */
+ volatile uint32_t interrupt_count;
+
+ /**
+ * @brief If this member is true, then the interrupt shall be cleared.
+ */
+ bool do_clear;
+
+ /**
+ * @brief This member contains the current vector number.
+ */
+ rtems_vector_number vector;
+
+ /**
+ * @brief If this member is true, then the ``vector`` parameter shall be
+ * valid.
+ */
+ bool valid_vector;
+
+ /**
+ * @brief This member contains the return value of the
+ * rtems_interrupt_clear() call.
+ */
+ rtems_status_code status;
+
+ /**
+ * @brief This member defines the pre-condition states for the next action.
+
[PATCH 35/41] validation: Test rtems_interrupt_entry_remove()
Update #3269.
---
.../testsuites/validation/validation-0.yml|1 +
testsuites/validation/tc-intr-entry-remove.c | 1302 +
2 files changed, 1303 insertions(+)
create mode 100644 testsuites/validation/tc-intr-entry-remove.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index c536779f2d..08ef145c82 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -16,6 +16,7 @@ source:
- testsuites/validation/tc-barrier-release.c
- testsuites/validation/tc-barrier-wait.c
- testsuites/validation/tc-intr-entry-install.c
+- testsuites/validation/tc-intr-entry-remove.c
- testsuites/validation/tc-intr-get-attributes.c
- testsuites/validation/tc-intr-vector-disable.c
- testsuites/validation/tc-intr-vector-enable.c
diff --git a/testsuites/validation/tc-intr-entry-remove.c
b/testsuites/validation/tc-intr-entry-remove.c
new file mode 100644
index 00..90f3701ef0
--- /dev/null
+++ b/testsuites/validation/tc-intr-entry-remove.c
@@ -0,0 +1,1302 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqEntryRemove
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqEntryRemove \
+ * spec:/rtems/intr/req/entry-remove
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_Vector_Valid,
+ RtemsIntrReqEntryRemove_Pre_Vector_Invalid,
+ RtemsIntrReqEntryRemove_Pre_Vector_NA
+} RtemsIntrReqEntryRemove_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_Entry_Obj,
+ RtemsIntrReqEntryRemove_Pre_Entry_Null,
+ RtemsIntrReqEntryRemove_Pre_Entry_NA
+} RtemsIntrReqEntryRemove_Pre_Entry;
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_Routine_Valid,
+ RtemsIntrReqEntryRemove_Pre_Routine_Null,
+ RtemsIntrReqEntryRemove_Pre_Routine_NA
+} RtemsIntrReqEntryRemove_Pre_Routine;
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_EntryObj_Installed,
+ RtemsIntrReqEntryRemove_Pre_EntryObj_Match,
+ RtemsIntrReqEntryRemove_Pre_EntryObj_NoMatch,
+ RtemsIntrReqEntryRemove_Pre_EntryObj_NA
+} RtemsIntrReqEntryRemove_Pre_EntryObj;
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_Init_Yes,
+ RtemsIntrReqEntryRemove_Pre_Init_No,
+ RtemsIntrReqEntryRemove_Pre_Init_NA
+} RtemsIntrReqEntryRemove_Pre_Init;
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_ISR_Yes,
+ RtemsIntrReqEntryRemove_Pre_ISR_No,
+ RtemsIntrReqEntryRemove_Pre_ISR_NA
+} RtemsIntrReqEntryRemove_Pre_ISR;
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_First_Yes,
+ RtemsIntrReqEntryRemove_Pre_First_No,
+ RtemsIntrReqEntryRemove_Pre_First_NA
+} RtemsIntrReqEntryRemove_Pre_First;
+
+typedef enum {
+ RtemsIntrReqEntryRemove_Pre_Last_Yes,
+
[PATCH 41/41] validation: Test rtems_interrupt_set_affinity()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
testsuites/validation/tc-intr-set-affinity.c | 670 ++
2 files changed, 671 insertions(+)
create mode 100644 testsuites/validation/tc-intr-set-affinity.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 89c0f408d6..6778a5ec25 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -23,6 +23,7 @@ source:
- testsuites/validation/tc-intr-get-affinity.c
- testsuites/validation/tc-intr-get-attributes.c
- testsuites/validation/tc-intr-is-pending.c
+- testsuites/validation/tc-intr-set-affinity.c
- testsuites/validation/tc-intr-vector-disable.c
- testsuites/validation/tc-intr-vector-enable.c
- testsuites/validation/tc-intr-vector-is-enabled.c
diff --git a/testsuites/validation/tc-intr-set-affinity.c
b/testsuites/validation/tc-intr-set-affinity.c
new file mode 100644
index 00..b2b47baea8
--- /dev/null
+++ b/testsuites/validation/tc-intr-set-affinity.c
@@ -0,0 +1,670 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqSetAffinity
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqSetAffinity \
+ * spec:/rtems/intr/req/set-affinity
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqSetAffinity_Pre_Vector_Valid,
+ RtemsIntrReqSetAffinity_Pre_Vector_Invalid,
+ RtemsIntrReqSetAffinity_Pre_Vector_NA
+} RtemsIntrReqSetAffinity_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqSetAffinity_Pre_CPUSetKind_Valid,
+ RtemsIntrReqSetAffinity_Pre_CPUSetKind_Huge,
+ RtemsIntrReqSetAffinity_Pre_CPUSetKind_Askew,
+ RtemsIntrReqSetAffinity_Pre_CPUSetKind_NA
+} RtemsIntrReqSetAffinity_Pre_CPUSetKind;
+
+typedef enum {
+ RtemsIntrReqSetAffinity_Pre_CPUSet_Valid,
+ RtemsIntrReqSetAffinity_Pre_CPUSet_Null,
+ RtemsIntrReqSetAffinity_Pre_CPUSet_NA
+} RtemsIntrReqSetAffinity_Pre_CPUSet;
+
+typedef enum {
+ RtemsIntrReqSetAffinity_Pre_CanSetAffinity_Yes,
+ RtemsIntrReqSetAffinity_Pre_CanSetAffinity_No,
+ RtemsIntrReqSetAffinity_Pre_CanSetAffinity_NA
+} RtemsIntrReqSetAffinity_Pre_CanSetAffinity;
+
+typedef enum {
+ RtemsIntrReqSetAffinity_Post_Status_Ok,
+ RtemsIntrReqSetAffinity_Post_Status_InvAddr,
+ RtemsIntrReqSetAffinity_Post_Status_InvId,
+ RtemsIntrReqSetAffinity_Post_Status_InvNum,
+ RtemsIntrReqSetAffinity_Post_Status_Unsat,
+ RtemsIntrReqSetAffinity_Post_Status_NA
+} RtemsIntrReqSetAffinity_Post_Status;
+
+typedef enum {
+ RtemsIntrReqSetAffinity_Post_SetAffinity_Yes,
+ RtemsIntrReqSetAffinity_Post_SetAffinity_Nop,
+ RtemsIntrReqSetAffinity_Post_SetAffinity_NA
+} RtemsIntrReqSetAffinity_Post_SetAffinity;
+
+/**
+ * @brief Test context for
[PATCH 40/41] validation: Test rtems_interrupt_get_affinity()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
testsuites/validation/tc-intr-get-affinity.c | 639 ++
2 files changed, 640 insertions(+)
create mode 100644 testsuites/validation/tc-intr-get-affinity.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index eba0954182..89c0f408d6 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -20,6 +20,7 @@ source:
- testsuites/validation/tc-intr-clear.c
- testsuites/validation/tc-intr-entry-install.c
- testsuites/validation/tc-intr-entry-remove.c
+- testsuites/validation/tc-intr-get-affinity.c
- testsuites/validation/tc-intr-get-attributes.c
- testsuites/validation/tc-intr-is-pending.c
- testsuites/validation/tc-intr-vector-disable.c
diff --git a/testsuites/validation/tc-intr-get-affinity.c
b/testsuites/validation/tc-intr-get-affinity.c
new file mode 100644
index 00..43d8c75fec
--- /dev/null
+++ b/testsuites/validation/tc-intr-get-affinity.c
@@ -0,0 +1,639 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqGetAffinity
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqGetAffinity \
+ * spec:/rtems/intr/req/get-affinity
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqGetAffinity_Pre_Vector_Valid,
+ RtemsIntrReqGetAffinity_Pre_Vector_Invalid,
+ RtemsIntrReqGetAffinity_Pre_Vector_NA
+} RtemsIntrReqGetAffinity_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqGetAffinity_Pre_CPUSetSize_Valid,
+ RtemsIntrReqGetAffinity_Pre_CPUSetSize_TooSmall,
+ RtemsIntrReqGetAffinity_Pre_CPUSetSize_Askew,
+ RtemsIntrReqGetAffinity_Pre_CPUSetSize_NA
+} RtemsIntrReqGetAffinity_Pre_CPUSetSize;
+
+typedef enum {
+ RtemsIntrReqGetAffinity_Pre_CPUSet_Valid,
+ RtemsIntrReqGetAffinity_Pre_CPUSet_Null,
+ RtemsIntrReqGetAffinity_Pre_CPUSet_NA
+} RtemsIntrReqGetAffinity_Pre_CPUSet;
+
+typedef enum {
+ RtemsIntrReqGetAffinity_Pre_CanGetAffinity_Yes,
+ RtemsIntrReqGetAffinity_Pre_CanGetAffinity_No,
+ RtemsIntrReqGetAffinity_Pre_CanGetAffinity_NA
+} RtemsIntrReqGetAffinity_Pre_CanGetAffinity;
+
+typedef enum {
+ RtemsIntrReqGetAffinity_Post_Status_Ok,
+ RtemsIntrReqGetAffinity_Post_Status_InvAddr,
+ RtemsIntrReqGetAffinity_Post_Status_InvId,
+ RtemsIntrReqGetAffinity_Post_Status_InvSize,
+ RtemsIntrReqGetAffinity_Post_Status_Unsat,
+ RtemsIntrReqGetAffinity_Post_Status_NA
+} RtemsIntrReqGetAffinity_Post_Status;
+
+typedef enum {
+ RtemsIntrReqGetAffinity_Post_CPUSetObj_Set,
+ RtemsIntrReqGetAffinity_Post_CPUSetObj_Nop,
+ RtemsIntrReqGetAffinity_Post_CPUSetObj_NA
+} RtemsIntrReqGetAffinity_Post_CPUSetObj;
+
+/**
+ * @brief Test context for
[PATCH 09/41] rtems: Add rtems_interrupt_is_pending()
Update #3269. --- cpukit/include/rtems/irq-extension.h | 54 1 file changed, 54 insertions(+) diff --git a/cpukit/include/rtems/irq-extension.h b/cpukit/include/rtems/irq-extension.h index 4a8f0b7879..c96dfd7d5c 100644 --- a/cpukit/include/rtems/irq-extension.h +++ b/cpukit/include/rtems/irq-extension.h @@ -453,6 +453,60 @@ rtems_status_code rtems_interrupt_vector_enable( rtems_vector_number vector ); */ rtems_status_code rtems_interrupt_vector_disable( rtems_vector_number vector ); +/* Generated from spec:/rtems/intr/if/is-pending */ + +/** + * @ingroup RTEMSAPIClassicIntr + * + * @brief Checks if the interrupt is pending. + * + * @param vector is the interrupt vector number. + * + * @param[out] pending is the pointer to a ``bool`` object. When the directive + * call is successful, the pending status of the interrupt associated with + * the interrupt vector specified by ``vector`` will be stored in this + * object. When the interrupt was pending for the processor executing the + * directive call at some time point during the call, the object value will + * be set to true, otherwise to false. + * + * The directive checks if the interrupt associated with the interrupt vector + * specified by ``vector`` was pending for the processor executing the + * directive call at some time point during the call. + * + * @retval ::RTEMS_SUCCESSFUL The requested operation was successful. + * + * @retval ::RTEMS_INVALID_ADDRESS The ``pending`` parameter was NULL. + * + * @retval ::RTEMS_INVALID_ID There was no interrupt vector associated with the + * number specified by ``vector``. + * + * @retval ::RTEMS_UNSATISFIED The request to get the pending status has not + * been satisfied. + * + * @par Notes + * Interrupts may be made pending by calling the rtems_interrupt_cause() or + * rtems_interrupt_cause_on() directives or due to exernal signals or messages. + * The pending state may be cleared by rtems_interrupt_clear(). + * + * @par Constraints + * @parblock + * The following constraints apply to this directive: + * + * * The directive may be called from within interrupt context. + * + * * The directive may be called from within device driver initialization + * context. + * + * * The directive may be called from within task context. + * + * * The directive will not cause the calling task to be preempted. + * @endparblock + */ +rtems_status_code rtems_interrupt_is_pending( + rtems_vector_number vector, + bool *pending +); + /* Generated from spec:/rtems/intr/if/get-affinity */ /** -- 2.26.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 33/41] validation: Test rtems_interrupt_vector_disable()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
.../validation/tc-intr-vector-disable.c | 608 ++
2 files changed, 609 insertions(+)
create mode 100644 testsuites/validation/tc-intr-vector-disable.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 36d2a0f388..78633bebe5 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -16,6 +16,7 @@ source:
- testsuites/validation/tc-barrier-release.c
- testsuites/validation/tc-barrier-wait.c
- testsuites/validation/tc-intr-get-attributes.c
+- testsuites/validation/tc-intr-vector-disable.c
- testsuites/validation/tc-intr-vector-enable.c
- testsuites/validation/tc-intr-vector-is-enabled.c
- testsuites/validation/tc-message-construct-errors.c
diff --git a/testsuites/validation/tc-intr-vector-disable.c
b/testsuites/validation/tc-intr-vector-disable.c
new file mode 100644
index 00..a926febf73
--- /dev/null
+++ b/testsuites/validation/tc-intr-vector-disable.c
@@ -0,0 +1,608 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqVectorDisable
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqVectorDisable \
+ * spec:/rtems/intr/req/vector-disable
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqVectorDisable_Pre_Vector_Valid,
+ RtemsIntrReqVectorDisable_Pre_Vector_Invalid,
+ RtemsIntrReqVectorDisable_Pre_Vector_NA
+} RtemsIntrReqVectorDisable_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqVectorDisable_Pre_IsEnabled_Yes,
+ RtemsIntrReqVectorDisable_Pre_IsEnabled_No,
+ RtemsIntrReqVectorDisable_Pre_IsEnabled_NA
+} RtemsIntrReqVectorDisable_Pre_IsEnabled;
+
+typedef enum {
+ RtemsIntrReqVectorDisable_Pre_CanDisable_Yes,
+ RtemsIntrReqVectorDisable_Pre_CanDisable_No,
+ RtemsIntrReqVectorDisable_Pre_CanDisable_NA
+} RtemsIntrReqVectorDisable_Pre_CanDisable;
+
+typedef enum {
+ RtemsIntrReqVectorDisable_Post_Status_Ok,
+ RtemsIntrReqVectorDisable_Post_Status_InvId,
+ RtemsIntrReqVectorDisable_Post_Status_Unsat,
+ RtemsIntrReqVectorDisable_Post_Status_NA
+} RtemsIntrReqVectorDisable_Post_Status;
+
+typedef enum {
+ RtemsIntrReqVectorDisable_Post_IsEnabled_Nop,
+ RtemsIntrReqVectorDisable_Post_IsEnabled_No,
+ RtemsIntrReqVectorDisable_Post_IsEnabled_NA
+} RtemsIntrReqVectorDisable_Post_IsEnabled;
+
+/**
+ * @brief Test context for spec:/rtems/intr/req/vector-disable test case.
+ */
+typedef struct {
+ /**
+ * @brief If this member is true, then an interrupt occurred.
+ */
+ bool interrupt_occurred;
+
+ /**
+ * @brief This member contains the current vector number.
+ */
+ rtems_vector_number vector;
+
+ /**
+ *
[PATCH 14/41] bsps/irq: Add rtems_interrupt_is_pending()
Add a default implementation which just returns RTEMS_UNSATISFIED.
Update #3269.
---
bsps/arm/beagle/irq/irq.c | 11 ++
bsps/arm/csb336/irq/irq.c | 11 ++
bsps/arm/csb337/irq/irq.c | 11 ++
bsps/arm/edb7312/irq/irq.c| 11 ++
bsps/arm/gumstix/irq/irq.c| 11 ++
bsps/arm/lpc24xx/irq/irq.c| 11 ++
bsps/arm/lpc32xx/irq/irq.c| 11 ++
bsps/arm/raspberrypi/irq/irq.c| 11 ++
bsps/arm/rtl22xx/irq/irq.c| 11 ++
bsps/arm/shared/irq/irq-armv7m.c | 11 ++
bsps/arm/smdk2410/irq/irq.c | 11 ++
bsps/arm/tms570/irq/irq.c | 11 ++
bsps/i386/shared/irq/irq.c| 11 ++
bsps/include/bsp/irq-generic.h| 26 +++
bsps/lm32/shared/irq/irq.c| 11 ++
bsps/m68k/genmcf548x/irq/irq.c| 11 ++
bsps/mips/shared/irq/irq.c| 11 ++
bsps/powerpc/gen5200/irq/irq.c| 11 ++
bsps/powerpc/gen83xx/irq/irq.c| 11 ++
bsps/powerpc/mpc55xxevb/start/irq.c | 11 ++
bsps/powerpc/mpc8260ads/irq/irq.c | 11 ++
bsps/powerpc/psim/irq/irq_init.c | 11 ++
bsps/powerpc/qemuppc/irq/irq_init.c | 11 ++
bsps/powerpc/qoriq/irq/irq.c | 22 +++
bsps/powerpc/shared/irq/ppc-irq-generic.c | 11 ++
bsps/powerpc/t32mppc/irq/irq.c| 11 ++
bsps/powerpc/tqm8xx/irq/irq.c | 11 ++
bsps/powerpc/virtex/irq/irq_init.c| 11 ++
bsps/riscv/griscv/irq/irq.c | 11 ++
bsps/riscv/riscv/irq/irq.c| 11 ++
bsps/shared/dev/irq/arm-gicv2.c | 11 ++
bsps/shared/dev/irq/arm-gicv3.c | 11 ++
bsps/shared/irq/irq-cause-clear.c | 16 ++
bsps/shared/irq/irq-default.c | 11 ++
bsps/sparc/leon3/start/eirq.c | 11 ++
bsps/sparc/shared/irq/irq-shared.c| 11 ++
bsps/x86_64/amd64/interrupts/idt.c| 11 ++
37 files changed, 438 insertions(+)
diff --git a/bsps/arm/beagle/irq/irq.c b/bsps/arm/beagle/irq/irq.c
index d54b49f0ca..e34a89afff 100644
--- a/bsps/arm/beagle/irq/irq.c
+++ b/bsps/arm/beagle/irq/irq.c
@@ -103,6 +103,17 @@ rtems_status_code bsp_interrupt_get_attributes(
return RTEMS_SUCCESSFUL;
}
+rtems_status_code bsp_interrupt_is_pending(
+ rtems_vector_number vector,
+ bool *pending
+)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ bsp_interrupt_assert(pending != NULL);
+ *pending = false;
+ return RTEMS_UNSATISFIED;
+}
+
rtems_status_code bsp_interrupt_cause(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
diff --git a/bsps/arm/csb336/irq/irq.c b/bsps/arm/csb336/irq/irq.c
index 2cc4f5bb5c..13f094e1fb 100644
--- a/bsps/arm/csb336/irq/irq.c
+++ b/bsps/arm/csb336/irq/irq.c
@@ -34,6 +34,17 @@ rtems_status_code bsp_interrupt_get_attributes(
return RTEMS_SUCCESSFUL;
}
+rtems_status_code bsp_interrupt_is_pending(
+ rtems_vector_number vector,
+ bool *pending
+)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ bsp_interrupt_assert(pending != NULL);
+ *pending = false;
+ return RTEMS_UNSATISFIED;
+}
+
rtems_status_code bsp_interrupt_cause(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
diff --git a/bsps/arm/csb337/irq/irq.c b/bsps/arm/csb337/irq/irq.c
index 1679b89dc3..1b13f0b461 100644
--- a/bsps/arm/csb337/irq/irq.c
+++ b/bsps/arm/csb337/irq/irq.c
@@ -35,6 +35,17 @@ rtems_status_code bsp_interrupt_get_attributes(
return RTEMS_SUCCESSFUL;
}
+rtems_status_code bsp_interrupt_is_pending(
+ rtems_vector_number vector,
+ bool *pending
+)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ bsp_interrupt_assert(pending != NULL);
+ *pending = false;
+ return RTEMS_UNSATISFIED;
+}
+
rtems_status_code bsp_interrupt_cause(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
diff --git a/bsps/arm/edb7312/irq/irq.c b/bsps/arm/edb7312/irq/irq.c
index 573e4f015d..75dffdec9f 100644
--- a/bsps/arm/edb7312/irq/irq.c
+++ b/bsps/arm/edb7312/irq/irq.c
@@ -35,6 +35,17 @@ rtems_status_code bsp_interrupt_get_attributes(
return RTEMS_SUCCESSFUL;
}
+rtems_status_code bsp_interrupt_is_pending(
+ rtems_vector_number vector,
+ bool *pending
+)
+{
+ bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+ bsp_interrupt_assert(pending != NULL);
+ *pending = false;
+ return RTEMS_UNSATISFIED;
+}
+
rtems_status_code bsp_interrupt_cause(rtems_vector_number vector)
{
[PATCH 28/41] validation: HasInterruptVectorEntriesInstalled()
Update #3269.
---
.../testsuites/validation/libvalidation.yml | 1 +
testsuites/validation/tx-interrupt.c | 79 +++
testsuites/validation/tx-support.h| 2 +
3 files changed, 82 insertions(+)
create mode 100644 testsuites/validation/tx-interrupt.c
diff --git a/spec/build/testsuites/validation/libvalidation.yml
b/spec/build/testsuites/validation/libvalidation.yml
index 54c7ae0ac0..98dd2e3623 100644
--- a/spec/build/testsuites/validation/libvalidation.yml
+++ b/spec/build/testsuites/validation/libvalidation.yml
@@ -12,6 +12,7 @@ install-path: null
links: []
source:
- testsuites/validation/tx-call-within-isr.c
+- testsuites/validation/tx-interrupt.c
- testsuites/validation/tx-support.c
target: validation
type: build
diff --git a/testsuites/validation/tx-interrupt.c
b/testsuites/validation/tx-interrupt.c
new file mode 100644
index 00..d056af5abc
--- /dev/null
+++ b/testsuites/validation/tx-interrupt.c
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestSuites
+ *
+ * @brief This source file contains the implementation of
+ * HasInterruptVectorEntriesInstalled().
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "tx-support.h"
+
+#include
+#include
+
+static void HasInstalled(
+ void *arg,
+ const char *info,
+ rtems_optionoptions,
+ rtems_interrupt_handler handler_routine,
+ void *handler_arg
+)
+{
+ bool *has_installed_entries;
+
+ (void) info;
+ (void) options;
+ (void) handler_routine;
+ (void) handler_arg;
+
+ has_installed_entries = arg;
+ *has_installed_entries = true;
+}
+
+bool HasInterruptVectorEntriesInstalled( rtems_vector_number vector )
+{
+ bool has_installed_entries;
+ rtems_status_code sc;
+
+ has_installed_entries = false;
+ sc = rtems_interrupt_handler_iterate(
+vector,
+HasInstalled,
+_installed_entries
+ );
+ T_quiet_rsc_success( sc );
+
+ return has_installed_entries;
+}
diff --git a/testsuites/validation/tx-support.h
b/testsuites/validation/tx-support.h
index 9d5a51e461..378e98ee3f 100644
--- a/testsuites/validation/tx-support.h
+++ b/testsuites/validation/tx-support.h
@@ -113,6 +113,8 @@ void CallWithinISRSubmit( CallWithinISRRequest *request );
void CallWithinISRWait( const CallWithinISRRequest *request );
+bool HasInterruptVectorEntriesInstalled( rtems_vector_number vector );
+
/** @} */
#ifdef __cplusplus
--
2.26.2
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 30/41] validation: Test rtems_interrupt_get_attributes()
Update #3269.
---
.../testsuites/validation/validation-0.yml| 1 +
.../validation/tc-intr-get-attributes.c | 445 ++
2 files changed, 446 insertions(+)
create mode 100644 testsuites/validation/tc-intr-get-attributes.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 653872320c..4e8ecfe1a0 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -15,6 +15,7 @@ source:
- testsuites/validation/tc-barrier-delete.c
- testsuites/validation/tc-barrier-release.c
- testsuites/validation/tc-barrier-wait.c
+- testsuites/validation/tc-intr-get-attributes.c
- testsuites/validation/tc-message-construct-errors.c
- testsuites/validation/tc-object.c
- testsuites/validation/tc-signal-catch.c
diff --git a/testsuites/validation/tc-intr-get-attributes.c
b/testsuites/validation/tc-intr-get-attributes.c
new file mode 100644
index 00..f5ce962b2b
--- /dev/null
+++ b/testsuites/validation/tc-intr-get-attributes.c
@@ -0,0 +1,445 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrReqGetAttributes
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+#include
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrReqGetAttributes \
+ * spec:/rtems/intr/req/get-attributes
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @{
+ */
+
+typedef enum {
+ RtemsIntrReqGetAttributes_Pre_Vector_Valid,
+ RtemsIntrReqGetAttributes_Pre_Vector_Invalid,
+ RtemsIntrReqGetAttributes_Pre_Vector_NA
+} RtemsIntrReqGetAttributes_Pre_Vector;
+
+typedef enum {
+ RtemsIntrReqGetAttributes_Pre_Attributes_Obj,
+ RtemsIntrReqGetAttributes_Pre_Attributes_Null,
+ RtemsIntrReqGetAttributes_Pre_Attributes_NA
+} RtemsIntrReqGetAttributes_Pre_Attributes;
+
+typedef enum {
+ RtemsIntrReqGetAttributes_Post_Status_Ok,
+ RtemsIntrReqGetAttributes_Post_Status_InvAddr,
+ RtemsIntrReqGetAttributes_Post_Status_InvId,
+ RtemsIntrReqGetAttributes_Post_Status_NA
+} RtemsIntrReqGetAttributes_Post_Status;
+
+typedef enum {
+ RtemsIntrReqGetAttributes_Post_Attributes_Nop,
+ RtemsIntrReqGetAttributes_Post_Attributes_Zero,
+ RtemsIntrReqGetAttributes_Post_Attributes_Set,
+ RtemsIntrReqGetAttributes_Post_Attributes_NA
+} RtemsIntrReqGetAttributes_Post_Attributes;
+
+/**
+ * @brief Test context for spec:/rtems/intr/req/get-attributes test case.
+ */
+typedef struct {
+ /**
+ * @brief This member provides the rtems_interrupt_attributes object.
+ */
+ rtems_interrupt_attributes attributes_obj;
+
+ /**
+ * @brief If this member is true, then the ``vector`` parameter shall be
+ * valid.
+ */
+ bool valid_vector;
+
+ /**
+ * @brief This member specifies if the ``attributes`` parameter value.
+ */
+ rtems_interrupt_attributes *attributes;;
+
+ /**
+ * @brief This member
[PATCH 24/41] bsps/irq: Move bsp_interrupt_handler_is_empty()
This function is only used by one BSP.
Update #3269.
---
bsps/i386/shared/irq/irq.c | 11 +++
bsps/include/bsp/irq-generic.h | 11 ---
bsps/shared/irq/irq-generic.c | 19 ---
3 files changed, 11 insertions(+), 30 deletions(-)
diff --git a/bsps/i386/shared/irq/irq.c b/bsps/i386/shared/irq/irq.c
index 9aab9d27f2..d0004698e7 100644
--- a/bsps/i386/shared/irq/irq.c
+++ b/bsps/i386/shared/irq/irq.c
@@ -351,6 +351,17 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
return RTEMS_SUCCESSFUL;
}
+static bool bsp_interrupt_handler_is_empty(rtems_vector_number vector)
+{
+ rtems_vector_number index;
+ rtems_interrupt_entry *head;
+
+ index = bsp_interrupt_handler_index(vector);
+ head = _interrupt_handler_table[index];
+
+ return bsp_interrupt_is_empty_handler_entry(head);
+}
+
/*
* Global so the asm handler can call it.
*/
diff --git a/bsps/include/bsp/irq-generic.h b/bsps/include/bsp/irq-generic.h
index 9babc4cfb5..3b2998f533 100644
--- a/bsps/include/bsp/irq-generic.h
+++ b/bsps/include/bsp/irq-generic.h
@@ -415,17 +415,6 @@ static inline void bsp_interrupt_handler_dispatch(
rtems_vector_number vector )
}
}
-/**
- * @brief Is interrupt handler empty.
- *
- * This routine returns true if the handler is empty and has not been
- * initialised else false is returned. The interrupt lock is not used
- * so this call can be used from within interrupts.
- *
- * @return If empty true shall be returned else false is returned.
- */
-bool bsp_interrupt_handler_is_empty(rtems_vector_number vector);
-
/** @} */
/* For internal use only */
diff --git a/bsps/shared/irq/irq-generic.c b/bsps/shared/irq/irq-generic.c
index 59963182ab..df57c99ae3 100644
--- a/bsps/shared/irq/irq-generic.c
+++ b/bsps/shared/irq/irq-generic.c
@@ -462,22 +462,3 @@ rtems_status_code rtems_interrupt_handler_remove(
{
return bsp_interrupt_handler_remove(vector, handler, arg);
}
-
-bool bsp_interrupt_handler_is_empty(rtems_vector_number vector)
-{
- rtems_vector_number index = 0;
- rtems_interrupt_entry *head = NULL;
- bool empty;
-
- /* For use in interrupts so no lock. */
-
- /* Get handler table index */
- index = bsp_interrupt_handler_index(vector);
-
- /* Get head entry of the handler list for the vector */
- head = _interrupt_handler_table [index];
-
- empty = bsp_interrupt_is_empty_handler_entry(head);
-
- return empty;
-}
--
2.26.2
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 29/41] validation: GetValidInterruptVectorNumber()
Update #3269.
---
testsuites/validation/tx-interrupt.c | 26 ++
testsuites/validation/tx-support.h | 5 +
2 files changed, 31 insertions(+)
diff --git a/testsuites/validation/tx-interrupt.c
b/testsuites/validation/tx-interrupt.c
index d056af5abc..0ff5ec017f 100644
--- a/testsuites/validation/tx-interrupt.c
+++ b/testsuites/validation/tx-interrupt.c
@@ -43,6 +43,32 @@
#include
#include
+#include
+
+rtems_vector_number GetValidInterruptVectorNumber(
+ const rtems_interrupt_attributes *required
+)
+{
+ rtems_vector_number vector;
+
+ for ( vector = 0; vector < BSP_INTERRUPT_VECTOR_COUNT; ++vector ) {
+rtems_status_code sc;
+rtems_interrupt_attributes attr;
+
+sc = rtems_interrupt_get_attributes( vector, );
+
+if (
+ sc == RTEMS_SUCCESSFUL &&
+( required == NULL ||
+ !required->can_get_affinity || attr.can_get_affinity )
+ ) {
+ break;
+}
+ }
+
+ return vector;
+}
+
static void HasInstalled(
void *arg,
const char *info,
diff --git a/testsuites/validation/tx-support.h
b/testsuites/validation/tx-support.h
index 378e98ee3f..20006f5dd8 100644
--- a/testsuites/validation/tx-support.h
+++ b/testsuites/validation/tx-support.h
@@ -38,6 +38,7 @@
#define _TX_SUPPORT_H
#include
+#include
#include
#ifdef __cplusplus
@@ -113,6 +114,10 @@ void CallWithinISRSubmit( CallWithinISRRequest *request );
void CallWithinISRWait( const CallWithinISRRequest *request );
+rtems_vector_number GetValidInterruptVectorNumber(
+ const rtems_interrupt_attributes *required
+);
+
bool HasInterruptVectorEntriesInstalled( rtems_vector_number vector );
/** @} */
--
2.26.2
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 23/41] bsps/irq: Add bsp_interrupt_check_and_lock()
Return RTEMS_INCORRECT_STATE instead of RTEMS_INCORRECT_STATE in case the
interrupt support is not initialized. This is similar to
rtems_timer_server_fire_after() for example.
Update #3269.
---
bsps/include/bsp/irq-generic.h| 25 +++
bsps/shared/irq/irq-generic.c | 60 ---
bsps/shared/irq/irq-handler-iterate.c | 51 +++
3 files changed, 75 insertions(+), 61 deletions(-)
diff --git a/bsps/include/bsp/irq-generic.h b/bsps/include/bsp/irq-generic.h
index b553ac30bf..9babc4cfb5 100644
--- a/bsps/include/bsp/irq-generic.h
+++ b/bsps/include/bsp/irq-generic.h
@@ -434,6 +434,31 @@ void bsp_interrupt_lock(void);
/* For internal use only */
void bsp_interrupt_unlock(void);
+/**
+ * @brief Checks the vector and routine. When the checks were successful, the
+ * interrupt support lock will be obtained.
+ *
+ * @param vector is the interrupt vector number to check.
+ *
+ * @param routine is the routine to check.
+ *
+ * @retval ::RTEMS_SUCCESSFUL The requested operation was successful.
+ *
+ * @retval ::RTEMS_INCORRECT_STATE The interrupt support was not initialized.
+ *
+ * @retval ::RTEMS_CALLED_FROM_ISR The function was called from within
+ * interrupt context.
+ *
+ * @retval ::RTEMS_INVALID_ADDRESS The ``routine`` parameter was NULL.
+ *
+ * @retval ::RTEMS_INVALID_ID There was no interrupt vector associated with the
+ * number specified by ``vector``.
+ */
+rtems_status_code bsp_interrupt_check_and_lock(
+ rtems_vector_number vector,
+ rtems_interrupt_handler handler
+);
+
/**
* @brief This table contains a bit map which indicates if an entry is unique
* or shared.
diff --git a/bsps/shared/irq/irq-generic.c b/bsps/shared/irq/irq-generic.c
index a7e8c1163f..59963182ab 100644
--- a/bsps/shared/irq/irq-generic.c
+++ b/bsps/shared/irq/irq-generic.c
@@ -122,6 +122,32 @@ static inline bool bsp_interrupt_allocate_handler_index(
#endif
}
+rtems_status_code bsp_interrupt_check_and_lock(
+ rtems_vector_number vector,
+ rtems_interrupt_handler handler
+)
+{
+ if ( !bsp_interrupt_is_initialized() ) {
+return RTEMS_INCORRECT_STATE;
+ }
+
+ if ( handler == NULL ) {
+return RTEMS_INVALID_ADDRESS;
+ }
+
+ if ( !bsp_interrupt_is_valid_vector( vector ) ) {
+return RTEMS_INVALID_ID;
+ }
+
+ if ( rtems_interrupt_is_in_progress() ) {
+return RTEMS_CALLED_FROM_ISR;
+ }
+
+ bsp_interrupt_lock();
+
+ return RTEMS_SUCCESSFUL;
+}
+
void bsp_interrupt_initialize(void)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
@@ -162,25 +188,18 @@ static rtems_status_code bsp_interrupt_handler_install(
void *arg
)
{
+ rtems_status_code sc;
rtems_interrupt_level level;
rtems_vector_number index = 0;
rtems_interrupt_entry *head = NULL;
bool enable_vector = false;
bool replace = RTEMS_INTERRUPT_IS_REPLACE(options);
- /* Check parameters and system state */
- if (!bsp_interrupt_is_initialized()) {
-return RTEMS_INTERNAL_ERROR;
- } else if (!bsp_interrupt_is_valid_vector(vector)) {
-return RTEMS_INVALID_ID;
- } else if (handler == NULL) {
-return RTEMS_INVALID_ADDRESS;
- } else if (rtems_interrupt_is_in_progress()) {
-return RTEMS_CALLED_FROM_ISR;
- }
+ sc = bsp_interrupt_check_and_lock( vector, handler );
- /* Lock */
- bsp_interrupt_lock();
+ if ( sc != RTEMS_SUCCESSFUL ) {
+return sc;
+ }
/* Get handler table index */
index = bsp_interrupt_handler_index(vector);
@@ -325,6 +344,7 @@ static rtems_status_code bsp_interrupt_handler_remove(
void *arg
)
{
+ rtems_status_code sc;
rtems_interrupt_level level;
rtems_vector_number index = 0;
rtems_interrupt_entry *head = NULL;
@@ -332,19 +352,11 @@ static rtems_status_code bsp_interrupt_handler_remove(
rtems_interrupt_entry *previous = NULL;
rtems_interrupt_entry *match = NULL;
- /* Check parameters and system state */
- if (!bsp_interrupt_is_initialized()) {
-return RTEMS_INTERNAL_ERROR;
- } else if (!bsp_interrupt_is_valid_vector(vector)) {
-return RTEMS_INVALID_ID;
- } else if (handler == NULL) {
-return RTEMS_INVALID_ADDRESS;
- } else if (rtems_interrupt_is_in_progress()) {
-return RTEMS_CALLED_FROM_ISR;
- }
+ sc = bsp_interrupt_check_and_lock( vector, handler );
- /* Lock */
- bsp_interrupt_lock();
+ if ( sc != RTEMS_SUCCESSFUL ) {
+return sc;
+ }
/* Get handler table index */
index = bsp_interrupt_handler_index(vector);
diff --git a/bsps/shared/irq/irq-handler-iterate.c
b/bsps/shared/irq/irq-handler-iterate.c
index 3c642b075e..385cb8db2d 100644
--- a/bsps/shared/irq/irq-handler-iterate.c
+++ b/bsps/shared/irq/irq-handler-iterate.c
@@ -36,39 +36,26 @@
#include
-/**
- * @brief Iterates over all installed interrupt handler of a vector.
- *
- * @ingroup bsp_interrupt
- *
- * @return In addition to the standard status codes this function returns
- * RTEMS_INTERNAL_ERROR if the BSP interrupt support is not initialized.
- *
- * @see
[PATCH 16/41] bsps/irq: bsp_interrupt_vector_disable()
Return a status code for bsp_interrupt_vector_disable().
Update #3269.
---
bsps/arm/beagle/irq/irq.c | 3 ++-
bsps/arm/csb336/irq/irq.c | 4 +++-
bsps/arm/csb337/irq/irq.c | 3 ++-
bsps/arm/edb7312/irq/irq.c| 4 +++-
bsps/arm/gumstix/irq/irq.c| 3 ++-
bsps/arm/lpc24xx/irq/irq.c| 3 ++-
bsps/arm/lpc32xx/irq/irq.c| 4 +++-
bsps/arm/raspberrypi/irq/irq.c| 3 ++-
bsps/arm/rtl22xx/irq/irq.c| 3 ++-
bsps/arm/shared/irq/irq-armv7m.c | 3 ++-
bsps/arm/smdk2410/irq/irq.c | 3 ++-
bsps/arm/tms570/irq/irq.c | 3 ++-
bsps/i386/shared/irq/irq.c| 3 ++-
bsps/include/bsp/irq-generic.h| 16 ++--
bsps/lm32/shared/irq/irq.c| 3 ++-
bsps/m68k/genmcf548x/irq/irq.c| 4 +++-
bsps/mips/shared/irq/irq.c| 3 ++-
bsps/powerpc/gen5200/irq/irq.c| 4 +++-
bsps/powerpc/gen83xx/irq/irq.c| 4 +++-
bsps/powerpc/mpc55xxevb/start/irq.c | 3 ++-
bsps/powerpc/mpc8260ads/irq/irq.c | 4 +++-
bsps/powerpc/psim/irq/irq_init.c | 3 ++-
bsps/powerpc/qemuppc/irq/irq_init.c | 3 ++-
bsps/powerpc/qoriq/irq/irq.c | 5 +++--
bsps/powerpc/shared/irq/ppc-irq-generic.c | 3 ++-
bsps/powerpc/t32mppc/irq/irq.c| 3 ++-
bsps/powerpc/tqm8xx/irq/irq.c | 4 +++-
bsps/powerpc/virtex/irq/irq_init.c| 4 +++-
bsps/riscv/griscv/irq/irq.c | 3 ++-
bsps/riscv/riscv/irq/irq.c| 4 +++-
bsps/shared/dev/irq/arm-gicv2.c | 3 ++-
bsps/shared/dev/irq/arm-gicv3.c | 4 +++-
bsps/shared/irq/irq-default.c | 3 ++-
bsps/shared/irq/irq-enable-disable.c | 4 +---
bsps/sparc/leon3/start/eirq.c | 3 ++-
bsps/sparc/shared/irq/irq-shared.c| 3 ++-
bsps/x86_64/amd64/interrupts/idt.c| 3 ++-
37 files changed, 93 insertions(+), 45 deletions(-)
diff --git a/bsps/arm/beagle/irq/irq.c b/bsps/arm/beagle/irq/irq.c
index 7953a2fe1f..7db3428499 100644
--- a/bsps/arm/beagle/irq/irq.c
+++ b/bsps/arm/beagle/irq/irq.c
@@ -150,7 +150,7 @@ rtems_status_code
bsp_interrupt_vector_enable(rtems_vector_number vector)
return RTEMS_SUCCESSFUL;
}
-void bsp_interrupt_vector_disable(rtems_vector_number vector)
+rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
{
uint32_t mask, cur;
uint32_t mir_reg = omap_get_mir_reg(vector, );
@@ -160,6 +160,7 @@ void bsp_interrupt_vector_disable(rtems_vector_number
vector)
cur = mmio_read(omap_intr.base + mir_reg);
mmio_write(omap_intr.base + mir_reg, cur | mask);
flush_data_cache();
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_facility_initialize(void)
diff --git a/bsps/arm/csb336/irq/irq.c b/bsps/arm/csb336/irq/irq.c
index d47f0362e8..2cf142100a 100644
--- a/bsps/arm/csb336/irq/irq.c
+++ b/bsps/arm/csb336/irq/irq.c
@@ -78,12 +78,14 @@ rtems_status_code
bsp_interrupt_vector_enable(rtems_vector_number vector)
return RTEMS_SUCCESSFUL;
}
-void bsp_interrupt_vector_disable(rtems_vector_number vector)
+rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
if (vector < MC9328MXL_NUM_INTS)
MC9328MXL_AITC_INTDISNUM = vector;
+
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_facility_initialize(void)
diff --git a/bsps/arm/csb337/irq/irq.c b/bsps/arm/csb337/irq/irq.c
index a4bfb1f83b..b999841751 100644
--- a/bsps/arm/csb337/irq/irq.c
+++ b/bsps/arm/csb337/irq/irq.c
@@ -76,10 +76,11 @@ rtems_status_code
bsp_interrupt_vector_enable(rtems_vector_number vector)
return RTEMS_SUCCESSFUL;
}
-void bsp_interrupt_vector_disable(rtems_vector_number vector)
+rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
AIC_CTL_REG(AIC_IDCR) = 1 << vector;
+ return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_facility_initialize(void)
diff --git a/bsps/arm/edb7312/irq/irq.c b/bsps/arm/edb7312/irq/irq.c
index 3cff5bfff2..ec50443775 100644
--- a/bsps/arm/edb7312/irq/irq.c
+++ b/bsps/arm/edb7312/irq/irq.c
@@ -97,7 +97,7 @@ rtems_status_code
bsp_interrupt_vector_enable(rtems_vector_number vector)
return RTEMS_SUCCESSFUL;
}
-void bsp_interrupt_vector_disable(rtems_vector_number vector)
+rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
@@ -121,6 +121,8 @@ void bsp_interrupt_vector_disable(rtems_vector_number
vector)
/* interrupt managed by INTMR3 and INTSR3 */
*EP7312_INTMR3 &= ~(1 << (vector - 21));
}
+
+return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_facility_initialize(void)
diff
