I don't know why but I don't see any code on this.
On 7/3/2014 4:39 AM, Daniel Cederman wrote:
> When entering up state, but before enabling interrupts,
> the icaches are flushed to make sure that changes to the trap
> table are visible. After up state the SMP cache manager is
> used to order cach
When entering up state, but before enabling interrupts,
the icaches are flushed to make sure that changes to the trap
table are visible. After up state the SMP cache manager is
used to order cache flushes whenever the trap table is altered.
Daniel Cederman (2):
bsp/sparc: Flush icache before fir
