On Mon, Sep 30, 2019 at 12:03 PM Hesham Almatary
wrote:
>
> Hi Pragnesh,
>
> That's a so much better refined patch, thanks! Please find my minor
> comments inlined below.
>
> After the patch gets merged, could you please add a new section about
> that BSP to the RISC-V chapter doc here [1]?
>
> [1
Hi Pragnesh,
That's a so much better refined patch, thanks! Please find my minor
comments inlined below.
After the patch gets merged, could you please add a new section about
that BSP to the RISC-V chapter doc here [1]?
[1] https://docs.rtems.org/branches/master/user/bsps/bsps-riscv.html
On Fri
Hello Pragnesh Patel,
could you please use this license for new code:
https://git.rtems.org/rtems/tree/LICENSE.BSD-2-Clause
It would be nice if you could use a coding style close to the existing
code in this BSP (only if you have time).
Please don't change the default values in configure.ac
Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board.
Update #3785.
Signed-off-by: Pragnesh Patel
---
Changes in v3:
- Remove bsps/riscv/frdme310arty/ directory and added support for
Freedom FE310 soc in common bsps/riscv/riscv/ directory
- Added #define RISCV_ENABLE_FRDME31
