Re: New RISC-V BSP variant (Kendryte K210)
On Thu, Dec 1, 2022 at 6:06 PM Joel Sherrill wrote: > > I'm going to say enthusiastically yes. > > I suspect that other boards will be very similar so this is likely a good > basis to go from. > > If you have links where it is actually for sale and not just described, that > would be great. Seeed Studio: https://www.seeedstudio.com/Sipeed-Maixduino-Kit-for-RISC-V-AI-IoT-p-4047.html?queryID=86b62e47589a0b56236a5c29ab704818=4047=bazaar_retailer_products They have a number of other boards and modules, but most have not been in stock for a while. I'm not sure if it's a supply chain problem like the Raspberry Pi, or they are no longer available. Also here: https://www.dfrobot.com/product-1985.html https://www.dfrobot.com/product-1972.html Boards and modules are also available on Aliexpress. > > Chris would likely encourage you to post rtems-tester results. :) I have been using the Rednode.io test framework. I'm currently running a dozen tests, but I would like to try using rtems-tester. > > And perhaps we can reach out and let them know RTEMS is available on their > hardware. Chris might enjoy poking that bear. lol I'm sure they would not mind. There are ports of rt-thread, nuttx, and no-mmu linux to the SoC. Kendrtye offers a bare metal SDK with the Apache 2.0 license: https://github.com/kendryte/kendryte-standalone-sdk They did have a FreeRTOS SDK, but it is no longer maintained: https://github.com/kendryte/kendryte-freertos-sdk I don't think there are any binary blobs needed, and an RTEMS image can just be flashed to the boards using a "kflash.py" utility that is available through pip, so getting started is easy: Just build RTEMS images and either run on renode or flash via USB cable. Alan > > On Thu, Dec 1, 2022, 1:46 PM Alan Cudmore wrote: >> >> Hi, >> I have been working on a basic BSP for the Kendryte K210 RISC-V CPU, >> and I was wondering if the community members would like me to submit >> it. >> The Kendryte K210 is a dual core 64 bit RISC-V processor with a wealth >> of peripheral I/O, a built-in AI NPU, and 8 Megabytes of on-chip SRAM. >> I like it because it is one of the lowest cost RISC-V CPUs available, >> and it appears to run RTEMS well. >> In addition, my BSP works on the K210 model on the renode.io >> simulator. I believe it would work on QEMU, but it is very close to >> the rv64imafdc_medany riscv BSP variant. >> The changes consist of: >> - A new riscv/riscv variant and associated build option files >> - A new DTB header, since the DTB is included in the BSP similar to >> the polarfire BSP >> - Some code to detect the frequency in bspstart.c >> - A new header file for the k210 >> Because the console uses the same sifive uart as the frdme310arty BSP, >> I factored that out so the Sifive UART can be used in multiple BSP >> variants. It is able to use the existing timer and interrupt code. >> >> In addition to the renode.io simulator, I have run it on the following >> boards: >> - Sipeed MAIX Bit >> - Sipeed MAIXduino (arduino form factor board with ESP32) >> - Sipeed Grove AI hat for Raspberry Pi >> >> Potential negatives: >> - I do not have a BSD licensed device tree source, I created the >> device tree binary from the u-boot distribution. Is it OK to just >> include the device tree binary (similar to the microblaze)? >> - The availability of these boards has not been as good for the last >> year or so, but you can still find them at a relatively low cost. The >> Sipeed company seems to be focusing on another low cost RISC-V SoC, >> which is very interesting as well: The Bouffalo Lab BL808 (example >> here: >> https://wiki.pine64.org/wiki/Ox64) >> >> Is this worth submitting? I don't want to clutter up the tree with >> devices that may become obsolete - we could focus on the upcoming >> round of low cost RISC-V SoCs like the BL808. >> I don't have a specific application I am using it for, but I used it >> as a very inexpensive way to learn RISC-V on a real board. It may be >> of some value to integrate additional peripheral support including the >> AI NPU. >> >> If anyone is interested, I can submit the patches or even provide a >> branch on github. >> >> Thanks, >> Alan >> ___ >> devel mailing list >> devel@rtems.org >> http://lists.rtems.org/mailman/listinfo/devel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: New RISC-V BSP variant (Kendryte K210)
I'm going to say enthusiastically yes. I suspect that other boards will be very similar so this is likely a good basis to go from. If you have links where it is actually for sale and not just described, that would be great. Chris would likely encourage you to post rtems-tester results. :) And perhaps we can reach out and let them know RTEMS is available on their hardware. Chris might enjoy poking that bear. lol On Thu, Dec 1, 2022, 1:46 PM Alan Cudmore wrote: > Hi, > I have been working on a basic BSP for the Kendryte K210 RISC-V CPU, > and I was wondering if the community members would like me to submit > it. > The Kendryte K210 is a dual core 64 bit RISC-V processor with a wealth > of peripheral I/O, a built-in AI NPU, and 8 Megabytes of on-chip SRAM. > I like it because it is one of the lowest cost RISC-V CPUs available, > and it appears to run RTEMS well. > In addition, my BSP works on the K210 model on the renode.io > simulator. I believe it would work on QEMU, but it is very close to > the rv64imafdc_medany riscv BSP variant. > The changes consist of: > - A new riscv/riscv variant and associated build option files > - A new DTB header, since the DTB is included in the BSP similar to > the polarfire BSP > - Some code to detect the frequency in bspstart.c > - A new header file for the k210 > Because the console uses the same sifive uart as the frdme310arty BSP, > I factored that out so the Sifive UART can be used in multiple BSP > variants. It is able to use the existing timer and interrupt code. > > In addition to the renode.io simulator, I have run it on the following > boards: > - Sipeed MAIX Bit > - Sipeed MAIXduino (arduino form factor board with ESP32) > - Sipeed Grove AI hat for Raspberry Pi > > Potential negatives: > - I do not have a BSD licensed device tree source, I created the > device tree binary from the u-boot distribution. Is it OK to just > include the device tree binary (similar to the microblaze)? > - The availability of these boards has not been as good for the last > year or so, but you can still find them at a relatively low cost. The > Sipeed company seems to be focusing on another low cost RISC-V SoC, > which is very interesting as well: The Bouffalo Lab BL808 (example > here: > https://wiki.pine64.org/wiki/Ox64) > > Is this worth submitting? I don't want to clutter up the tree with > devices that may become obsolete - we could focus on the upcoming > round of low cost RISC-V SoCs like the BL808. > I don't have a specific application I am using it for, but I used it > as a very inexpensive way to learn RISC-V on a real board. It may be > of some value to integrate additional peripheral support including the > AI NPU. > > If anyone is interested, I can submit the patches or even provide a > branch on github. > > Thanks, > Alan > ___ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
New RISC-V BSP variant (Kendryte K210)
Hi, I have been working on a basic BSP for the Kendryte K210 RISC-V CPU, and I was wondering if the community members would like me to submit it. The Kendryte K210 is a dual core 64 bit RISC-V processor with a wealth of peripheral I/O, a built-in AI NPU, and 8 Megabytes of on-chip SRAM. I like it because it is one of the lowest cost RISC-V CPUs available, and it appears to run RTEMS well. In addition, my BSP works on the K210 model on the renode.io simulator. I believe it would work on QEMU, but it is very close to the rv64imafdc_medany riscv BSP variant. The changes consist of: - A new riscv/riscv variant and associated build option files - A new DTB header, since the DTB is included in the BSP similar to the polarfire BSP - Some code to detect the frequency in bspstart.c - A new header file for the k210 Because the console uses the same sifive uart as the frdme310arty BSP, I factored that out so the Sifive UART can be used in multiple BSP variants. It is able to use the existing timer and interrupt code. In addition to the renode.io simulator, I have run it on the following boards: - Sipeed MAIX Bit - Sipeed MAIXduino (arduino form factor board with ESP32) - Sipeed Grove AI hat for Raspberry Pi Potential negatives: - I do not have a BSD licensed device tree source, I created the device tree binary from the u-boot distribution. Is it OK to just include the device tree binary (similar to the microblaze)? - The availability of these boards has not been as good for the last year or so, but you can still find them at a relatively low cost. The Sipeed company seems to be focusing on another low cost RISC-V SoC, which is very interesting as well: The Bouffalo Lab BL808 (example here: https://wiki.pine64.org/wiki/Ox64) Is this worth submitting? I don't want to clutter up the tree with devices that may become obsolete - we could focus on the upcoming round of low cost RISC-V SoCs like the BL808. I don't have a specific application I am using it for, but I used it as a very inexpensive way to learn RISC-V on a real board. It may be of some value to integrate additional peripheral support including the AI NPU. If anyone is interested, I can submit the patches or even provide a branch on github. Thanks, Alan ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
