Re: fenv on RISC-V

On Fri, Aug 16, 2019 at 9:44 AM Gedare Bloom wrote: > > On Thu, Aug 15, 2019 at 3:58 PM Joel Sherrill wrote: > > > > OK. I am going to through an issue out and then paste another email > > from Jim Wilson. Let's see if we can figure this one out portably. > > > > (1) Every architecture now will h

Re: fenv on RISC-V

On Thu, Aug 15, 2019 at 3:58 PM Joel Sherrill wrote: > > OK. I am going to through an issue out and then paste another email > from Jim Wilson. Let's see if we can figure this one out portably. > > (1) Every architecture now will have an implementation of fenv. It may > be a stub, non-functional f

Re: fenv on RISC-V

OK. I am going to through an issue out and then paste another email from Jim Wilson. Let's see if we can figure this one out portably. (1) Every architecture now will have an implementation of fenv. It may be a stub, non-functional fenv implementation. If this is the case, many methods return "-EN

Re: fenv on RISC-V

On 16/8/19 1:38 am, Gedare Bloom wrote: > On Wed, Aug 14, 2019 at 12:44 PM Joel Sherrill wrote: >> >> Hi >> >> I emailed Jim Wilson of SiFive and got a quick response. Much thanks >> to him and this is his reply: >> >> == >> I don't have any embedded hardware that I can use for tes

Re: fenv on RISC-V

On Wed, Aug 14, 2019 at 12:44 PM Joel Sherrill wrote: > > Hi > > I emailed Jim Wilson of SiFive and got a quick response. Much thanks > to him and this is his reply: > > == > I don't have any embedded hardware that I can use for testing. I just > have linux and simulators (qemu, g

Re: fenv on RISC-V

Having said that, I will check if the generation of FP exception flag for RISC-V in sis are as accurate as for SPARC. Generating the wrong flags could cause the type of failures we are seeing ... On 8/14/19 10:42 PM, Jiri Gaisler wrote: > Interesting. I can confirm that the griscv bsp is using h

Re: fenv on RISC-V

Interesting. I can confirm that the griscv bsp is using hard floats and doubles, it is compiled with -march=rv32imafd -mabi=ilp32d. The paranoia benchmark runs successfully and uses float instructions and registers. The sis simulator emulates all float and double instructions as define in the RI

fenv on RISC-V

Hi I emailed Jim Wilson of SiFive and got a quick response. Much thanks to him and this is his reply: == I don't have any embedded hardware that I can use for testing. I just have linux and simulators (qemu, gdb sim). I haven't seen gcc testsuite failures related to fenv, but no