, 2018 6:53 AM
To: devel@sel4.systems
Subject: Re: [seL4] seL4 on Heterogeneous Processing Architectures (Zynq
UltraScale+ MPSoCs)
On 6 Nov 2018, at 22:27, Blam Kiwi wrote:
I wasn't fully appreciating the difference between the MPU and MMU in relation
to seL4. If the R5's can't
On 6 Nov 2018, at 22:27, Blam Kiwi
mailto:blam.k...@gmail.com>> wrote:
I wasn't fully appreciating the difference between the MPU and MMU in relation
to seL4. If the R5's can't be supported then that simplifies the decision space
somewhat. Guess I'll evaluate the RTOSes before throwing my
----
> *From:* Devel on behalf of Blam Kiwi <
> blam.k...@gmail.com>
> *Sent:* Thursday, October 11, 2018 1:48 PM
> *To:* devel@sel4.systems
> *Subject:* [seL4] seL4 on Heterogeneous Processing Architectures (Zynq
> UltraScale+ MPSoCs)
>
> I am invest
Processing Architectures (Zynq
UltraScale+ MPSoCs)
I am investigating the use of seL4 on heterogeneous architectures such as the
Zynq UltraScale+ MPSoCs. I have a non-trivial use-case I'm investigating that
involves utilising both the Cortex-R5 cores and Core-A53 cores for different
applications
I am investigating the use of seL4 on heterogeneous architectures such as
the Zynq UltraScale+ MPSoCs. I have a non-trivial use-case I'm
investigating that involves utilising both the Cortex-R5 cores and Core-A53
cores for different applications. I'm rather new to seL4 development so I'm
a bit
