Upstreaming MMP clock devicetree support
Hi Mitch, As mentioned, upstream now has APBC/APMU clock drivers, and I think there are a couple of things in way that clock-dt.c interacts with the common clock framework that upstream wouldn't approve of. Here is my first attempt at a new approach, using the new upstream clock drivers, and using the common clock framework in a way that is more according to its design and use on other SoCs. Tested on XO-1.75 and XO-4. If you have some time for some quick comments on my DT design before I submit this, it would be much appreciated. DT tweaks and kernel patch follow. : +string encode-string encode+ ; : +int encode-int encode+ ; : +phandle encode-phandle encode+ ; \ APBC CLOCKS dev / new-device \ a.k.a. fast clock vctcxo device-name fixed-clock +compatible 0 #clock-cells integer-property d# 2600 clock-frequency integer-property finish-device new-device clk32 device-name fixed-clock +compatible 0 #clock-cells integer-property d# 3200 clock-frequency integer-property finish-device new-device apb-clock device-name h# d4015000 h# 1000 reg new-device twsi-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property 0 0 encode-bytes TWSI1 +string \ 0 TWSI2 +string \ 1 TWSI3 +string \ 2 TWSI4 +string \ 3 TWSI5 +string \ 4 TWSI6 +string \ 5 clock-output-names property 0 0 encode-bytes h# 04 +int h# 08 +int h# 0c +int h# 10 +int h# 7c +int h# 80 +int reg property finish-device new-device uart-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property 0 0 encode-bytes UART1 +string \ 0 UART2 +string \ 1 UART3 +string \ 2 UART4 +string \ 3 clock-output-names property 0 0 encode-bytes h# 2c +int h# 30 +int h# 34 +int h# 88 +int reg property finish-device new-device ssp-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property 0 0 encode-bytes SSP0 +string \ 0 SSP1 +string \ 1 SSP2 +string \ 2 SSP3 +string \ 3 SSP4 +string \ 4 SSP5 +string \ 5 clock-output-names property 0 0 encode-bytes h# 4c +int h# 50 +int h# 54 +int h# 58 +int h# 5c +int h# 60 +int reg property finish-device new-device misc-vctcxo-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property GPIO clock-output-names string-property 38 reg integer-property finish-device new-device thsens-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property 0 0 encode-bytes THSENS1 +string \ 0 THSENS2 +string \ 1 THSENS3 +string \ 2 THSENS4 +string \ 3 clock-output-names property 0 0 encode-bytes h# 90 +int h# 98 +int h# 9c +int h# a0 +int reg property finish-device new-device rtc-clock device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /clk32 encode-phandle clocks property RTC clock-output-names string-property 0 reg integer-property finish-device finish-device device-end dev /i2c@d4011000 \ point to TWSI1 /apb-clock/twsi-clocks encode-phandle d# 0 +int clocks property device-end dev /i2c@d4031000 \ point to TWSI2 /apb-clock/twsi-clocks encode-phandle d# 1 +int clocks property device-end dev /i2c@d4033000 \ point to TWSI4 /apb-clock/twsi-clocks encode-phandle d# 3 +int clocks property device-end dev /i2c@d4034000 \ point to TWSI6 /apb-clock/twsi-clocks encode-phandle d# 5 +int clocks property device-end dev /uart@d4018000 \ point to UART3 /apb-clock/uart-clocks encode-phandle d# 2 +int clocks property device-end dev /uart@d4017000 \ point to UART2 /apb-clock/uart-clocks encode-phandle d# 1 +int clocks property device-end dev /uart@d403 \ point to UART1 /apb-clock/uart-clocks encode-phandle d# 0 +int clocks property device-end dev /uart@d4016000 \ point to UART4 /apb-clock/uart-clocks encode-phandle d# 3 +int clocks property device-end dev /gpio \ point to GPIO /apb-clock/misc-vctcxo-clocks encode-phandle d# 0 +int clocks property device-end dev /flash \ point to SSP1 /apb-clock/ssp-clocks encode-phandle d# 1 +int clocks property device-end dev /ec-spi \ point to SSP3 /apb-clock/ssp-clocks encode-phandle d# 3 +int clocks property device-end dev
Re: Upstreaming MMP clock devicetree support
daniel wrote: Hi Mitch, As mentioned, upstream now has APBC/APMU clock drivers, and I think there are a couple of things in way that clock-dt.c interacts with the common clock framework that upstream wouldn't approve of. Here is my first attempt at a new approach, using the new upstream clock drivers, and using the common clock framework in a way that is more according to its design and use on other SoCs. Tested on XO-1.75 and XO-4. If you have some time for some quick comments on my DT design before I submit this, it would be much appreciated. does this imply a future flag day, at which time new firmware will be incompatible with old kernels, and vice-versa? paul DT tweaks and kernel patch follow. : +string encode-string encode+ ; : +int encode-int encode+ ; : +phandle encode-phandle encode+ ; \ APBC CLOCKS dev / new-device \ a.k.a. fast clock vctcxo device-name fixed-clock +compatible 0 #clock-cells integer-property d# 2600 clock-frequency integer-property finish-device new-device clk32 device-name fixed-clock +compatible 0 #clock-cells integer-property d# 3200 clock-frequency integer-property finish-device new-device apb-clock device-name h# d4015000 h# 1000 reg new-device twsi-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property 0 0 encode-bytes TWSI1 +string \ 0 TWSI2 +string \ 1 TWSI3 +string \ 2 TWSI4 +string \ 3 TWSI5 +string \ 4 TWSI6 +string \ 5 clock-output-names property 0 0 encode-bytes h# 04 +int h# 08 +int h# 0c +int h# 10 +int h# 7c +int h# 80 +int reg property finish-device new-device uart-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property 0 0 encode-bytes UART1 +string \ 0 UART2 +string \ 1 UART3 +string \ 2 UART4 +string \ 3 clock-output-names property 0 0 encode-bytes h# 2c +int h# 30 +int h# 34 +int h# 88 +int reg property finish-device new-device ssp-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property 0 0 encode-bytes SSP0 +string \ 0 SSP1 +string \ 1 SSP2 +string \ 2 SSP3 +string \ 3 SSP4 +string \ 4 SSP5 +string \ 5 clock-output-names property 0 0 encode-bytes h# 4c +int h# 50 +int h# 54 +int h# 58 +int h# 5c +int h# 60 +int reg property finish-device new-device misc-vctcxo-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property GPIO clock-output-names string-property 38 reg integer-property finish-device new-device thsens-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property 0 0 encode-bytes THSENS1 +string \ 0 THSENS2 +string \ 1 THSENS3 +string \ 2 THSENS4 +string \ 3 clock-output-names property 0 0 encode-bytes h# 90 +int h# 98 +int h# 9c +int h# a0 +int reg property finish-device new-device rtc-clock device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /clk32 encode-phandle clocks property RTC clock-output-names string-property 0 reg integer-property finish-device finish-device device-end dev /i2c@d4011000 \ point to TWSI1 /apb-clock/twsi-clocks encode-phandle d# 0 +int clocks property device-end dev /i2c@d4031000 \ point to TWSI2 /apb-clock/twsi-clocks encode-phandle d# 1 +int clocks property device-end dev /i2c@d4033000 \ point to TWSI4 /apb-clock/twsi-clocks encode-phandle d# 3 +int clocks property device-end dev /i2c@d4034000 \ point to TWSI6 /apb-clock/twsi-clocks encode-phandle d# 5 +int clocks property device-end dev /uart@d4018000 \ point to UART3 /apb-clock/uart-clocks encode-phandle d# 2 +int clocks property device-end dev /uart@d4017000 \ point to UART2 /apb-clock/uart-clocks encode-phandle d# 1 +int clocks property device-end dev /uart@d403 \ point to UART1 /apb-clock/uart-clocks encode-phandle d# 0 +int clocks property device-end dev /uart@d4016000 \
Re: Upstreaming MMP clock devicetree support
On Thu, Jun 13, 2013 at 11:56 AM, Paul Fox p...@laptop.org wrote: does this imply a future flag day, at which time new firmware will be incompatible with old kernels, and vice-versa? Unfortunately even without the DT changes described here, old firmware versions already will not be able to boot new/upstream kernels, once we get to that point. The DT is missing regulator information so the MMC controller doesn't get powered up. This is the old firmware, new kernel problem. The DT clock changes described here would also mean that new firmwares become incompatible with released kernels. This is the new firmware, old kernel problem. I think this will also be unavoidable. So yes, we are looking at both of those problems. There are some thoughts and possibilities here: http://wiki.laptop.org/go/Device_tree_upgrade_considerations https://lists.ozlabs.org/pipermail/devicetree-discuss/2012-August/019024.html but no definite, attractive solution. I suspect it is something we are just going to have to live with. I think the old firmware, new kernel is the most painful of the two problems. Maybe we can fix that up with a bootwrapper type solution mentioned in the mail linked to above (and maybe I already half-wrote the bootwrapper in my previous mail). There is also the possibility that the kernel will accept bindings for old/imperfect DTs once good bindings are put in place - or alternatively we could patch them in. I'm working on the good bindings aspect at the moment. Daniel ___ Devel mailing list Devel@lists.laptop.org http://lists.laptop.org/listinfo/devel
Re: Upstreaming MMP clock devicetree support
It seems okay to me on first reading. On 6/13/2013 7:53 AM, Daniel Drake wrote: Hi Mitch, As mentioned, upstream now has APBC/APMU clock drivers, and I think there are a couple of things in way that clock-dt.c interacts with the common clock framework that upstream wouldn't approve of. Here is my first attempt at a new approach, using the new upstream clock drivers, and using the common clock framework in a way that is more according to its design and use on other SoCs. Tested on XO-1.75 and XO-4. If you have some time for some quick comments on my DT design before I submit this, it would be much appreciated. DT tweaks and kernel patch follow. : +string encode-string encode+ ; : +int encode-int encode+ ; : +phandle encode-phandle encode+ ; \ APBC CLOCKS dev / new-device \ a.k.a. fast clock vctcxo device-name fixed-clock +compatible 0 #clock-cells integer-property d# 2600 clock-frequency integer-property finish-device new-device clk32 device-name fixed-clock +compatible 0 #clock-cells integer-property d# 3200 clock-frequency integer-property finish-device new-device apb-clock device-name h# d4015000 h# 1000 reg new-device twsi-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property 0 0 encode-bytes TWSI1 +string \ 0 TWSI2 +string \ 1 TWSI3 +string \ 2 TWSI4 +string \ 3 TWSI5 +string \ 4 TWSI6 +string \ 5 clock-output-names property 0 0 encode-bytes h# 04 +int h# 08 +int h# 0c +int h# 10 +int h# 7c +int h# 80 +int reg property finish-device new-device uart-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property 0 0 encode-bytes UART1 +string \ 0 UART2 +string \ 1 UART3 +string \ 2 UART4 +string \ 3 clock-output-names property 0 0 encode-bytes h# 2c +int h# 30 +int h# 34 +int h# 88 +int reg property finish-device new-device ssp-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property 0 0 encode-bytes SSP0 +string \ 0 SSP1 +string \ 1 SSP2 +string \ 2 SSP3 +string \ 3 SSP4 +string \ 4 SSP5 +string \ 5 clock-output-names property 0 0 encode-bytes h# 4c +int h# 50 +int h# 54 +int h# 58 +int h# 5c +int h# 60 +int reg property finish-device new-device misc-vctcxo-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property GPIO clock-output-names string-property 38 reg integer-property finish-device new-device thsens-clocks device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /vctcxo encode-phandle clocks property 0 0 encode-bytes THSENS1 +string \ 0 THSENS2 +string \ 1 THSENS3 +string \ 2 THSENS4 +string \ 3 clock-output-names property 0 0 encode-bytes h# 90 +int h# 98 +int h# 9c +int h# a0 +int reg property finish-device new-device rtc-clock device-name marvell,mmp-apb-clock +compatible 1 #clock-cells integer-property /clk32 encode-phandle clocks property RTC clock-output-names string-property 0 reg integer-property finish-device finish-device device-end dev /i2c@d4011000 \ point to TWSI1 /apb-clock/twsi-clocks encode-phandle d# 0 +int clocks property device-end dev /i2c@d4031000 \ point to TWSI2 /apb-clock/twsi-clocks encode-phandle d# 1 +int clocks property device-end dev /i2c@d4033000 \ point to TWSI4 /apb-clock/twsi-clocks encode-phandle d# 3 +int clocks property device-end dev /i2c@d4034000 \ point to TWSI6 /apb-clock/twsi-clocks encode-phandle d# 5 +int clocks property device-end dev /uart@d4018000 \ point to UART3 /apb-clock/uart-clocks encode-phandle d# 2 +int clocks property device-end dev /uart@d4017000 \ point to UART2 /apb-clock/uart-clocks encode-phandle d# 1 +int clocks property device-end dev /uart@d403 \ point to UART1 /apb-clock/uart-clocks encode-phandle d# 0 +int clocks property device-end dev /uart@d4016000 \ point to UART4 /apb-clock/uart-clocks encode-phandle d# 3 +int clocks property device-end dev /gpio \ point to GPIO /apb-clock/misc-vctcxo-clocks encode-phandle d# 0 +int clocks property
