Branch: refs/heads/master Home: https://github.com/OpenSIPS/opensips Commit: 26f6c1bacb33ddf0bcbd54ccffc65bee8754e01d https://github.com/OpenSIPS/opensips/commit/26f6c1bacb33ddf0bcbd54ccffc65bee8754e01d Author: Razvan Crainea <raz...@opensips.org> Date: 2016-09-19 (Mon, 19 Sep 2016)
Changed paths: M modules/usrloc/ureplication.c Log Message: ----------- usrloc: fix race between update for different registers In case there are two REGISTER messages with incremental CSEQ are replicated in a different order, skip the processing, since this has already been resolved by the master instance. Thanks to Deniz Beskök for reporing this Closes #956
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