Re: [PATCH 1/2] bsps/aarch64: Ensure FPU trap state is consistent

2022-10-27 Thread Chris Johns 
On 28/10/2022 9:57 am, Kinsey Moore wrote:
> 
> On Thu, Oct 27, 2022 at 5:46 PM Chris Johns  > wrote:
> 
> On 28/10/2022 9:25 am, Kinsey Moore wrote:
> > On Thu, Oct 27, 2022 at 5:10 PM Chris Johns  
> > >> wrote:
> >
> >     On 28/10/2022 9:05 am, Kinsey Moore wrote:
> >     > RTEMS may be booted from a dirty environment. Ensure that FPU trap
> >     > settings are consistent.
> >     > ---
> >     >  bsps/aarch64/shared/start/start.S | 10 ++
> >     >  1 file changed, 10 insertions(+)
> >     >
> >     > diff --git a/bsps/aarch64/shared/start/start.S
> >     b/bsps/aarch64/shared/start/start.S
> >     > index 8bd4f86f4e..de0fdf4c80 100644
> >     > --- a/bsps/aarch64/shared/start/start.S
> >     > +++ b/bsps/aarch64/shared/start/start.S
> >     > @@ -307,6 +307,16 @@ _el1_start:
> >     > 
> >     >    /* FPU does not need to be enabled on AArch64 */
> >     > 
> >     > +  /* Ensure FPU traps are disabled by default */
> >     > +  mrs x0, FPCR
> >     > +  bic x0, x0, #(1 << 8)
> >     > +  bic x0, x0, #(1 << 9)
> >     > +  bic x0, x0, #(1 << 10)
> >     > +  bic x0, x0, #(1 << 11)
> >     > +  bic x0, x0, #(1 << 12)
> >     > +  bic x0, x0, #(1 << 15)
> >
> >     Does `bic x0, x0, #((1 << 8) | (1 << 9) | (1 << 10) | ...)` work?
> >
> > The assembler complains about the operand being out of range. I can 
> split it
> > into 8-12 in one and 15 by itself and everything seems to work.
> 
> Huh? If you use a hex value does it work?
> 
> I think the equivalent value would be 0x9f00. That generates the same error as
> putting all the components on the same line. I think there's a 6-bit immediate
> involved that's the limitation.

Ah, must be an aarch64 thing. I have been using ARM and thumb mode asm this 
week :)

I will leave this with you to sort out which is best.

Chris
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Re: [PATCH 1/2] bsps/aarch64: Ensure FPU trap state is consistent

2022-10-27 Thread Kinsey Moore 
On Thu, Oct 27, 2022 at 5:46 PM Chris Johns  wrote:

> On 28/10/2022 9:25 am, Kinsey Moore wrote:
> > On Thu, Oct 27, 2022 at 5:10 PM Chris Johns  > > wrote:
> >
> > On 28/10/2022 9:05 am, Kinsey Moore wrote:
> > > RTEMS may be booted from a dirty environment. Ensure that FPU trap
> > > settings are consistent.
> > > ---
> > >  bsps/aarch64/shared/start/start.S | 10 ++
> > >  1 file changed, 10 insertions(+)
> > >
> > > diff --git a/bsps/aarch64/shared/start/start.S
> > b/bsps/aarch64/shared/start/start.S
> > > index 8bd4f86f4e..de0fdf4c80 100644
> > > --- a/bsps/aarch64/shared/start/start.S
> > > +++ b/bsps/aarch64/shared/start/start.S
> > > @@ -307,6 +307,16 @@ _el1_start:
> > >
> > >/* FPU does not need to be enabled on AArch64 */
> > >
> > > +  /* Ensure FPU traps are disabled by default */
> > > +  mrs x0, FPCR
> > > +  bic x0, x0, #(1 << 8)
> > > +  bic x0, x0, #(1 << 9)
> > > +  bic x0, x0, #(1 << 10)
> > > +  bic x0, x0, #(1 << 11)
> > > +  bic x0, x0, #(1 << 12)
> > > +  bic x0, x0, #(1 << 15)
> >
> > Does `bic x0, x0, #((1 << 8) | (1 << 9) | (1 << 10) | ...)` work?
> >
> > The assembler complains about the operand being out of range. I can
> split it
> > into 8-12 in one and 15 by itself and everything seems to work.
>
> Huh? If you use a hex value does it work?
>
> I think the equivalent value would be 0x9f00. That generates the same
error as putting all the components on the same line. I think there's a
6-bit immediate involved that's the limitation.

Kinsey
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Re: [PATCH 1/2] bsps/aarch64: Ensure FPU trap state is consistent

2022-10-27 Thread Chris Johns 
On 28/10/2022 9:25 am, Kinsey Moore wrote:
> On Thu, Oct 27, 2022 at 5:10 PM Chris Johns  > wrote:
> 
> On 28/10/2022 9:05 am, Kinsey Moore wrote:
> > RTEMS may be booted from a dirty environment. Ensure that FPU trap
> > settings are consistent.
> > ---
> >  bsps/aarch64/shared/start/start.S | 10 ++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/bsps/aarch64/shared/start/start.S
> b/bsps/aarch64/shared/start/start.S
> > index 8bd4f86f4e..de0fdf4c80 100644
> > --- a/bsps/aarch64/shared/start/start.S
> > +++ b/bsps/aarch64/shared/start/start.S
> > @@ -307,6 +307,16 @@ _el1_start:
> > 
> >    /* FPU does not need to be enabled on AArch64 */
> > 
> > +  /* Ensure FPU traps are disabled by default */
> > +  mrs x0, FPCR
> > +  bic x0, x0, #(1 << 8)
> > +  bic x0, x0, #(1 << 9)
> > +  bic x0, x0, #(1 << 10)
> > +  bic x0, x0, #(1 << 11)
> > +  bic x0, x0, #(1 << 12)
> > +  bic x0, x0, #(1 << 15)
> 
> Does `bic x0, x0, #((1 << 8) | (1 << 9) | (1 << 10) | ...)` work?
> 
> The assembler complains about the operand being out of range. I can split it
> into 8-12 in one and 15 by itself and everything seems to work.

Huh? If you use a hex value does it work?

Chris
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Re: [PATCH 1/2] bsps/aarch64: Ensure FPU trap state is consistent

2022-10-27 Thread Kinsey Moore 
On Thu, Oct 27, 2022 at 5:10 PM Chris Johns  wrote:

> On 28/10/2022 9:05 am, Kinsey Moore wrote:
> > RTEMS may be booted from a dirty environment. Ensure that FPU trap
> > settings are consistent.
> > ---
> >  bsps/aarch64/shared/start/start.S | 10 ++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/bsps/aarch64/shared/start/start.S
> b/bsps/aarch64/shared/start/start.S
> > index 8bd4f86f4e..de0fdf4c80 100644
> > --- a/bsps/aarch64/shared/start/start.S
> > +++ b/bsps/aarch64/shared/start/start.S
> > @@ -307,6 +307,16 @@ _el1_start:
> >
> >/* FPU does not need to be enabled on AArch64 */
> >
> > +  /* Ensure FPU traps are disabled by default */
> > +  mrs x0, FPCR
> > +  bic x0, x0, #(1 << 8)
> > +  bic x0, x0, #(1 << 9)
> > +  bic x0, x0, #(1 << 10)
> > +  bic x0, x0, #(1 << 11)
> > +  bic x0, x0, #(1 << 12)
> > +  bic x0, x0, #(1 << 15)
>
> Does `bic x0, x0, #((1 << 8) | (1 << 9) | (1 << 10) | ...)` work?
>
The assembler complains about the operand being out of range. I can split
it into 8-12 in one and 15 by itself and everything seems to work.

Kinsey
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Re: [PATCH 1/2] bsps/aarch64: Ensure FPU trap state is consistent

2022-10-27 Thread Chris Johns 
On 28/10/2022 9:05 am, Kinsey Moore wrote:
> RTEMS may be booted from a dirty environment. Ensure that FPU trap
> settings are consistent.
> ---
>  bsps/aarch64/shared/start/start.S | 10 ++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/bsps/aarch64/shared/start/start.S 
> b/bsps/aarch64/shared/start/start.S
> index 8bd4f86f4e..de0fdf4c80 100644
> --- a/bsps/aarch64/shared/start/start.S
> +++ b/bsps/aarch64/shared/start/start.S
> @@ -307,6 +307,16 @@ _el1_start:
>  
>/* FPU does not need to be enabled on AArch64 */
>  
> +  /* Ensure FPU traps are disabled by default */
> +  mrs x0, FPCR
> +  bic x0, x0, #(1 << 8)
> +  bic x0, x0, #(1 << 9)
> +  bic x0, x0, #(1 << 10)
> +  bic x0, x0, #(1 << 11)
> +  bic x0, x0, #(1 << 12)
> +  bic x0, x0, #(1 << 15)

Does `bic x0, x0, #((1 << 8) | (1 << 9) | (1 << 10) | ...)` work?

The operand2 is a mask of bits to clear.

Chris
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