On 13/10/2016 20:26, Pavel Pisa wrote:
I have tuneled to school an manager remote PC test system
to run the build on actual HW. So some following results have
been captured over serial port from PC box controlled by
project written by my colleague
https://github.com/wentasah/novaboot
to report
On Wed, Oct 12, 2016 at 4:26 AM, wrote:
> From: Pavel Pisa
>
> The single write to memory or ioport output are mostly
> atomic operations already. The proper memory synchronization barrier
> should be used around them to guarantee ordering (sync or eieio
> on PowerPC for example) but because I h
Some typo corrections of e-mail written when I have returned
late in night from meeting with friends.
And some more clarification as well.
On Thursday 13 of October 2016 01:55:30 Pavel Pisa wrote:
> Hello Chris,
>
> On Wednesday 12 of October 2016 23:05:30 Chris Johns wrote:
> > On 13/10/2016 03:
Hello Chris,
On Wednesday 12 of October 2016 23:05:30 Chris Johns wrote:
> On 13/10/2016 03:22, Pavel Pisa wrote:
> > But RTEMS i8269 support has been broken to disable
> > vector for level triggered interrupts in generic
> > IRQ processing code.
>
> I am not sure where the blame should be placed.
On 13/10/2016 03:22, Pavel Pisa wrote:
But RTEMS i8269 support has been broken to disable
vector for level triggered interrupts in generic
IRQ processing code.
I am not sure where the blame should be placed. We need to disable at
the PIC when using libbsd with shared PCI interrupts because an
Hello Gedare,
On Wednesday 12 of October 2016 18:10:19 Gedare Bloom wrote:
> On Wed, Oct 12, 2016 at 4:26 AM, wrote:
> > From: Pavel Pisa
> >
> > The single write to memory or ioport output are mostly
> > atomic operations already. The proper memory synchronization barrier
> > should be used ar