* Andreas Fenkart afenk...@gmail.com [140629 12:43]:
2014-06-28 9:23 GMT+02:00 Tony Lindgren t...@atomide.com:
* James Cameron qu...@laptop.org [140628 08:24]:
On Fri, Jun 27, 2014 at 04:39:42PM +0200, Andreas Fenkart wrote:
I have an mwifiex module(sd8787) behind omap_hsmmc(am33xx-soc)
On Sunday 29 June 2014 20:35:10 Vince Bridgers wrote:
The synopsys EMAC can be configured for different numbers of multicast hash
bins and perfect filter entries at device creation time and there's no way
to query this configuration information at runtime. As a result, a devicetree
parameter
On Sunday 29 June 2014 20:32:20 Robert Jarzmik wrote:
As the RFC posted in [1] didn't meet an unrivaled success for
review, I'm posting this serie for PXA27x transition to clock
framework.
This transition is needed :
- to enable device-tree drivers port, as clocks are needed almost
On Sunday 29 June 2014 16:01:12 Robert Jarzmik wrote:
+Required properties:
+ - compatible: Should be marvell,pxa270-udc for USB controllers
+ used in device mode.
+ - reg: usb device MMIO address space
+ - interrupts: single interrupt generated by the UDC IP
+ - clocks: input clock of the
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.
Signed-off-by: Jaehoon
Since used the mmc_of_parse(), didn't parse the sub-node.
So we can remove the sub-node, because almost SoC used the only one card per a
host.
And supports-highspeed can be replaced to cap-mmc/sd-highspeed property.
Jaehoon Chung (4):
mmc: dw_mmc: modify the dt-binding for removing slot-node
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.
Signed-off-by: Jaehoon
Almost Soc is used the slot per a host.
Don't use the slot-node and deprecated the supports-highsped property.
Instead, use the cap-mmc/sd-highspeed.
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.
Signed-off-by: Jaehoon
Hello,
(2014/06/26 21:34), Sergei Shtylyov wrote:
Hello.
On 06/26/2014 07:37 AM, Yoshihiro Shimoda wrote:
From: Ben Dooks ben.do...@codethink.co.uk
Add device nodes for the R8A7790 internal PCI bridge devices.
Signed-off-by: Ben Dooks ben.do...@codethink.co.uk
Reviewed-by: Ian
This series patches add the support for NAND controller of hisilicon
hip04 Soc. These patches are base on branch integration-hilt-working-v3.14
in linaro landing-team git repository[1].
The NAND controller IP was developed by hisilicon and need a new driver
to support. The driver is usable and I
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
arch/arm/boot/dts/hip04.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index abb42ca..e63fc61 100644
--- a/arch/arm/boot/dts/hip04.dtsi
+++
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
.../devicetree/bindings/mtd/hisi-nand.txt | 38
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/hisi-nand.txt
diff --git
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
drivers/mtd/nand/Kconfig |5 +
drivers/mtd/nand/Makefile|1 +
drivers/mtd/nand/hisi_nand.c | 847 ++
3 files changed, 853 insertions(+)
create mode 100644 drivers/mtd/nand/hisi_nand.c
On 29-06-14 16:16, Hans de Goede wrote:
From: Arend van Spriel ar...@broadcom.com
The Broadcom bcm43xx sdio devices are fullmac devices that may be
integrated in ARM platforms. Currently, the brcmfmac driver for
these devices support use of platform data. This patch specifies
the bindings
On Sun, Jun 29, 2014 at 10:29:49AM +0100, Robert Jarzmik wrote:
Mark Rutland mark.rutl...@arm.com writes:
On Wed, Jun 25, 2014 at 08:54:01PM +0100, Robert Jarzmik wrote:
The name of the clock input doesn't make sense.
I don't understand. With [1] does it make any more sense ? If not
Hi Inki,
On Mon, Jun 30, 2014 at 11:01 AM, Andrzej Hajda a.ha...@samsung.com wrote:
On 06/30/2014 03:14 AM, Jingoo Han wrote:
On Friday, June 27, 2014 10:03 PM, Ajay kumar wrote:
On Fri, Jun 27, 2014 at 6:14 PM, Andrzej Hajda a.ha...@samsung.com wrote:
On 06/27/2014 01:48 PM, Ajay kumar
Overall a very nice driver. I didn't find any real bugs, but a few things
that could be changed for readability and micro-optimizations:
On Monday 30 June 2014 16:03:28 Zhou Wang wrote:
+#define hinfc_read(_host, _reg) readl(_host-iobase + (_reg))
+#define hinfc_write(_host, _value,
Hi All,
Here is a resend of 3 of my submission of Sascha Hauer's
mmc: Add SDIO function devicetree subnode parsing patch.
Can we please get some movement on these patches, either a review specifying
why this cannot go upstream, or else queuing it up for next / 3.17 ?
Changes since v1:
- Submit
From: Sascha Hauer s.ha...@pengutronix.de
This adds SDIO devicetree subnode parsing to the mmc core. While
SDIO devices are runtime probable they sometimes need nonprobable
additional information on embedded systems, like an additional gpio
interrupt or a clock. This patch makes it possible to
From: Sascha Hauer s.ha...@pengutronix.de
While SDIO devices are runtime probable they sometimes need nonprobable
additional information on embedded systems, like an additional gpio
interrupt or a clock. This binding describes how to add child nodes to the
devicetree to supply this information.
Hi,
On 06/30/2014 10:31 AM, Arend van Spriel wrote:
On 29-06-14 16:16, Hans de Goede wrote:
From: Arend van Spriel ar...@broadcom.com
The Broadcom bcm43xx sdio devices are fullmac devices that may be
integrated in ARM platforms. Currently, the brcmfmac driver for
these devices support use
On Fri, Jun 27, 2014 at 02:24:58PM +0100, Gabriel FERNANDEZ wrote:
This patch adds new compatibilities to support STiH407 SoC.
This doesn't seem to match the patch, which seems to relabel nodes,
rename nodes, change clock-output-names, _and_ adds some new compatible
strings.
Therefore this
On Fri, Jun 27, 2014 at 02:25:01PM +0100, Gabriel FERNANDEZ wrote:
A Flexgen structure is composed by:
- a clock cross bar (represented by a mux element)
- a pre and final dividers (represented by a divider and gate elements)
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
On Fri, Jun 27, 2014 at 02:25:07PM +0100, Gabriel FERNANDEZ wrote:
The patch added support for DT registration of ClockGenC0
It includes 2 c32 type PLL and a 660 Quadfs.
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
Signed-off-by: Olivier Bideau olivier.bid...@st.com
On Sun, Jun 29, 2014 at 05:21:41PM +0100, Andre Heider wrote:
Signed-off-by: Andre Heider a.hei...@gmail.com
---
Documentation/devicetree/bindings/misc/ti,pruss.txt | 19 +++
1 file changed, 19 insertions(+)
create mode 100644
Hi Mark,
First of all, thanks for the quick and carefully review.
On Fri, Jun 27, 2014 at 01:35:45PM +0100, Mark Rutland wrote:
On Fri, Jun 27, 2014 at 11:00:44AM +0100, Dong Aisheng wrote:
The patch adds the basic CAN TX/RX function support for Bosch M_CAN
controller.
For TX, only one
On Sun, Jun 29, 2014 at 05:21:43PM +0100, Andre Heider wrote:
Add support to probe via devicetree.
Signed-off-by: Andre Heider a.hei...@gmail.com
---
drivers/uio/uio_pruss.c | 46 +++---
1 file changed, 39 insertions(+), 7 deletions(-)
diff --git
On Sun, Jun 29, 2014 at 05:21:46PM +0100, Andre Heider wrote:
Signed-off-by: Andre Heider a.hei...@gmail.com
---
arch/arm/boot/dts/am33xx.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 4a4e02d..28a7e5d
On Sun, Jun 29, 2014 at 05:21:36PM +0100, Andre Heider wrote:
Replace kzalloc() by devm_kzalloc() and remove the kfree() calls.
Signed-off-by: Andre Heider a.hei...@gmail.com
---
drivers/uio/uio_pruss.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git
On 06/30/2014 11:03 AM, Zhou Wang wrote:
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
drivers/mtd/nand/Kconfig |5 +
drivers/mtd/nand/Makefile|1 +
drivers/mtd/nand/hisi_nand.c | 847 ++
3 files changed, 853 insertions(+)
Remove spaces in between tabs.
Introduced by commit ff4f3eb8b3386208944fe60b85e6cba4d338198e (ARM:
shmobile: r8a7790: add internal PCI bridge nodes).
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
arch/arm/boot/dts/r8a7790.dtsi | 12 ++--
1 file changed, 6 insertions(+),
Hi Olav,
On Fri, Jun 27, 2014 at 11:23:27PM +0100, Olav Haugan wrote:
On 6/25/2014 2:18 AM, Will Deacon wrote:
Why can't it be dynamically detected? Whilst the StreamIDs are fixed in
hardware (from the SMMU architecture perspective), the SMRs are completely
programmable. Why doesn't
When run on *.dtsi or *.dts files, the whitespace checks were skipped,
while they are valid for DTS files. Hence stop skipping them.
I ran checkpatch on all in-tree DTS files, and didn't notice any error or
warning messages that are inappropriate for DTS files.
Signed-off-by: Geert Uytterhoeven
On Fri, Jun 27, 2014 at 08:03:20PM +0200, Oliver Hartkopp wrote:
Hello Dong,
some general remarks from my side ...
On 27.06.2014 12:00, Dong Aisheng wrote:
M_CAN also supports CANFD protocol features like data payload up to 64 bytes
and bitrate switch at runtime, however, this patch
Hi!
Add more error messages making it easier to identify problems.
Signed-off-by: Sebastian Reichel s...@kernel.org
---
sound/soc/omap/rx51.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
+ if (err) {
+ dev_err(card-dev, Failed to add GPIOs\n);
On Mon 2014-04-28 16:07:24, Sebastian Reichel wrote:
Update the driver to get GPIO numbers from the
devm gpiod API instead of requesting hardcoded
GPIO numbers.
Signed-off-by: Sebastian Reichel s...@kernel.org
Acked-by: Pavel Machek pa...@ucw.cz
--
(english)
On Mon 2014-04-28 16:07:23, Sebastian Reichel wrote:
This is a preparation for DT based booting where the McBSP id
is set to -1 for all McBSP instances.
Signed-off-by: Sebastian Reichel s...@kernel.org
Acked-by: Pavel Machek pa...@ucw.cz
--
(english) http://www.livejournal.com/~pavelmachek
] Kernel panic - not syncing: VFS: Unable to mount root
fs on unknown-block(179,35)
[3.277647] CPU: 0 PID: 1 Comm: swapper/0 Tainted: GW
3.16.0-rc3-next-20140630-00049-g6a4f4b293862 #182
[3.288161] [c0014230] (unwind_backtrace) from [c001150c]
(show_stack+0x10/0x14)
[3.295878
Hi Rob,
Nice work!
On Fri, Jun 27, 2014 at 05:15:53PM +0100, Rob Herring wrote:
On 06/27/2014 07:49 AM, Will Deacon wrote:
On Fri, Jun 27, 2014 at 12:03:34PM +0100, Arnd Bergmann wrote:
On Thursday 26 June 2014 19:44:21 Rob Herring wrote:
I don't agree arm32 is harder than microblaze.
Hi,
This patch series add the possibility for the topology code to get the
CPU frequency through a DT clock handle instead of needing a
clock-frequency property.
Indeed, this information can be quite redundant if the clock tree
defined in the DT is already describing the CPU parent clock.
The Cortex-A7 and Cortex-A15 based SoCs need a clock-frequency property in the
topology code.
Allow to use a clock to provide the same information.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/kernel/topology.c | 25 ++---
1 file changed, 18
Setting the clock will make the topology code work, and will remove the
following error at boot
[0.097194] /cpus/cpu@0 missing clock-frequency property
[0.103657] /cpus/cpu@1 missing clock-frequency property
[0.110698] /cpus/cpu@2 missing clock-frequency property
[0.117132]
Hello,
On Tue, Jun 24, 2014 at 05:37:56PM +0530, Varka Bhadram wrote:
On 06/24/2014 05:30 PM, Kishon Vijay Abraham I wrote:
On Monday 16 June 2014 03:56 PM, Antoine Ténart wrote:
+
+static struct phy *phy_berlin_sata_phy_xlate(struct device *dev,
+
On Mon, Jun 30, 2014 at 12:12:22PM +0200, Maxime Ripard wrote:
The Cortex-A7 and Cortex-A15 based SoCs need a clock-frequency property in the
topology code.
Allow to use a clock to provide the same information.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
This looks fine
On 30 June 2014 12:29, Russell King - ARM Linux li...@arm.linux.org.uk wrote:
On Mon, Jun 30, 2014 at 12:12:22PM +0200, Maxime Ripard wrote:
The Cortex-A7 and Cortex-A15 based SoCs need a clock-frequency property in
the
topology code.
Allow to use a clock to provide the same information.
Sudeep Will，
-Original Message-
From: Neil Zhang
Sent: 2014年5月21日 19:47
To: 'Sudeep Holla'; Will Deacon
Cc: 'li...@arm.linux.org.uk'; 'linux-arm-ker...@lists.infradead.org';
'linux-ker...@vger.kernel.org'; 'devicetree@vger.kernel.org'
Subject: RE: [PATCH v4] ARM: perf:
On Sun, 29 Jun 2014 12:06:24 -0700, Laura Abbott lau...@codeaurora.org wrote:
Commit 1c2f87c22566cd057bc8cde10c37ae9da1a1bb76
(ARM: 8025/1: Get rid of meminfo) dropped the upper bound on
the number of memory banks that can be added as there was no
technical need in the kernel. It turns out
Hello Yadwinder,
Thanks a lot for your feedback.
On 06/30/2014 06:01 AM, Yadwinder Singh Brar wrote:
Hi Javier,
On Thu, Jun 26, 2014 at 11:45 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Maxim Integrated Power Management ICs are very similar with
regard to their
Hi Andy,
On Mon, Jun 30, 2014 at 12:11 PM, Andy Whitcroft a...@canonical.com wrote:
On Mon, Jun 30, 2014 at 11:53:31AM +0200, Geert Uytterhoeven wrote:
When run on *.dtsi or *.dts files, the whitespace checks were skipped,
while they are valid for DTS files. Hence stop skipping them.
I ran
On Mon, Jun 30, 2014 at 12:58:57PM +0200, Javier Martinez Canillas wrote:
+ if (!max_gen-lookup)
+ return ERR_PTR(-ENOMEM);
+
+ max_gen-lookup-con_id = hw-init-name;
Also IMO, init-name should be over-written if name is provided in DT,
otherwise generic
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.
Signed-off-by: Jaehoon
Since used the mmc_of_parse(), didn't parse the sub-node.
So we can remove the sub-node, because almost SoC used the only one card per a
host.
And supports-highspeed can be replaced to cap-mmc/sd-highspeed property.
Jaehoon Chung (5):
mmc: dw_mmc: modify the dt-binding for removing slot-node
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.
Signed-off-by: Jaehoon
Replaced the disable-wp into host's quirks.
(Because the slot-node is removed at dt-file.)
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
drivers/mmc/host/dw_mmc.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c
Almost Soc is used the slot per a host.
Don't use the slot-node and deprecated the supports-highsped property.
Instead, use the cap-mmc/sd-highspeed.
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Reviewed-by: Tushar Behera trbli...@gmail.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can be replaced to cap-sd/mmc-highspeed.
Signed-off-by: Jaehoon
On Mon, Jun 30, 2014 at 12:39:26PM +0200, Vincent Guittot wrote:
On 30 June 2014 12:29, Russell King - ARM Linux li...@arm.linux.org.uk
wrote:
On Mon, Jun 30, 2014 at 12:12:22PM +0200, Maxime Ripard wrote:
The Cortex-A7 and Cortex-A15 based SoCs need a clock-frequency property in
the
On Thu, Jun 26, 2014 at 11:59:46PM +0100, Feng Kan wrote:
Documentation for APM X-Gene SoC GPIO controller DTS binding.
Signed-off-by: Feng Kan f...@apm.com
Reviewed-by: Alexandre Courbot acour...@nvidia.com
---
.../devicetree/bindings/gpio/gpio-xgene.txt | 20
This series adds the support for Berlin SoC AHCI controller. The
controller allows to use the SATA host interface and, for example, the
eSATA port on the BG2Q.
The series adds a PHY driver to control the two SATA ports available,
and adds a generic compatible to use the existing ahci_platform
The current implementation of the libahci does not allow to use multiple
PHYs. This patch adds the support of multiple PHYs by the libahci while
keeping the old bindings valid for device tree compatibility.
This introduce a new way of defining SATA ports in the device tree, with
one port per
The libahci now allows to use multiple PHYs and to represent each port
as a sub-node. Add these bindings to the documentation.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
.../devicetree/bindings/ata/ahci-platform.txt | 37 ++
1 file changed, 37
The BG2Q has an AHCI SATA controller. Add the corresponding nodes
(AHCI, PHY) into its device tree.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git
The Berlin SATA PHY drives the PHY related to the SATA interface. Add
the corresponding documentation.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
.../devicetree/bindings/phy/berlin-sata-phy.txt| 34 ++
1 file changed, 34 insertions(+)
create mode
The BG2Q has an AHCI SATA controller with an eSATA interface. Enable it.
Only enable the first port, the BG2Q DMP does not support the second one.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 8
1 file changed, 8
The ahci_platform driver is a generic driver using the libahci_platform
functions. Add a generic compatible to avoid having an endless list of
compatibles with no differences for the same driver.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/ata/ahci_platform.c | 2
The Berlin SoC has a two SATA ports. Add a PHY driver to handle them.
The mode selection can let us think this PHY can be configured to fit
other purposes. But there are reasons to think the SATA mode will be
the only one usable: the PHY registers are only accessible indirectly
through two
Hi,
+Matteo
Am 30.06.2014 07:15, schrieb Olof Johansson:
On Sun, Jun 29, 2014 at 1:50 PM, Andreas Färber afaer...@suse.de wrote:
This allows to boot the Adapteva Parallella board to serial console.
Cc: Andreas Olofsson andr...@adapteva.com
Signed-off-by: Andreas Färber afaer...@suse.de
On 30 June 2014 14:49, Maxime Ripard maxime.rip...@free-electrons.com wrote:
On Mon, Jun 30, 2014 at 12:39:26PM +0200, Vincent Guittot wrote:
On 30 June 2014 12:29, Russell King - ARM Linux li...@arm.linux.org.uk
wrote:
On Mon, Jun 30, 2014 at 12:12:22PM +0200, Maxime Ripard wrote:
The
On 05.06.2014 22:35, Doug Anderson wrote:
The aclk66_peric clock is a gate clock with a whole bunch of gates
underneath it. This big gate isn't very useful to include in our
clock tree. If any of the children need to be turned on then the big
gate will need to be on anyway. ...and there are
On 19.06.2014 07:47, Rahul Sharma wrote:
Change bit from 2 to 9 for tv (mixer) sysmmu clock.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
Based on Kukjin's for-next branch.
drivers/clk/samsung/clk-exynos5250.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Hi Arnd,
On Mon, Jun 30, 2014 at 1:46 AM, Arnd Bergmann a...@arndb.de wrote:
On Sunday 29 June 2014 20:35:10 Vince Bridgers wrote:
The synopsys EMAC can be configured for different numbers of multicast hash
bins and perfect filter entries at device creation time and there's no way
to query
On Mon, Jun 30, 2014 at 03:27:21PM +0200, Vincent Guittot wrote:
- rate = of_get_property(cn, clock-frequency, len);
- if (!rate || len != 4) {
- pr_err(%s missing clock-frequency property\n,
- cn-full_name);
+
On 06/30/2014 11:59 AM, Antoine Ténart wrote:
On Wed, Jun 25, 2014 at 11:03:25PM +0400, Sergei Shtylyov wrote:
On 06/23/2014 05:39 PM, Antoine Ténart wrote:
+ /* set the controller speed */
+ writel(0x31, ctrl_reg + PORT_SCR_CTL);
Value undocumented? Or is this the SATA
On 30 June 2014 16:01, Maxime Ripard maxime.rip...@free-electrons.com wrote:
On Mon, Jun 30, 2014 at 03:27:21PM +0200, Vincent Guittot wrote:
- rate = of_get_property(cn, clock-frequency, len);
- if (!rate || len != 4) {
- pr_err(%s missing
On Mon, Jun 30, 2014 at 04:48:35PM +0200, Vincent Guittot wrote:
On 30 June 2014 16:01, Maxime Ripard maxime.rip...@free-electrons.com wrote:
On Mon, Jun 30, 2014 at 03:27:21PM +0200, Vincent Guittot wrote:
- rate = of_get_property(cn, clock-frequency, len);
- if
On 30 June 2014 16:58, Maxime Ripard maxime.rip...@free-electrons.com wrote:
On Mon, Jun 30, 2014 at 04:48:35PM +0200, Vincent Guittot wrote:
On 30 June 2014 16:01, Maxime Ripard maxime.rip...@free-electrons.com
wrote:
On Mon, Jun 30, 2014 at 03:27:21PM +0200, Vincent Guittot wrote:
-
Hi Sebastian,
On Mon, Jun 30, 2014 at 04:40:49PM +0200, Sebastian Hesselbarth wrote:
On 06/30/2014 11:59 AM, Antoine Ténart wrote:
On Wed, Jun 25, 2014 at 11:03:25PM +0400, Sergei Shtylyov wrote:
On 06/23/2014 05:39 PM, Antoine Ténart wrote:
+ /* set the controller speed */
+ writel(0x31,
Hello Russell,
Thanks a lot for your suggestion.
On 06/30/2014 01:35 PM, Russell King - ARM Linux wrote:
On Mon, Jun 30, 2014 at 12:58:57PM +0200, Javier Martinez Canillas wrote:
+ if (!max_gen-lookup)
+ return ERR_PTR(-ENOMEM);
+
+ max_gen-lookup-con_id =
Hi Pavel,
On 06/28/2014 12:07 PM, Pavel Machek wrote:
Hi!
The non-DT support has to be maintained for now to not break
OMAP3 legacy boot, and the legacy-style code will be cleaned
up once OMAP3 is also converted to DT-boot only.
@@ -587,24 +606,157 @@ static int
On 06/19/2014 05:37 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
The XUSB pad controller found on NVIDIA Tegra SoCs provides several pads
that lanes can be assigned to in order to support a variety of interface
options: USB 2.0, USB 3.0, PCIe and SATA.
In addition to
On Jun 17, 2014, at 2:46 PM, Kumar Gala ga...@codeaurora.org wrote:
Add a driver for the global clock controller found on IPQ8064 based
platforms. This should allow most non-multimedia device drivers to probe
and control their clocks.
This is currently missing clocks for USB HSIC and
2014-06-30 14:31 GMT+09:00 Andrzej Hajda a.ha...@samsung.com:
On 06/30/2014 03:14 AM, Jingoo Han wrote:
On Friday, June 27, 2014 10:03 PM, Ajay kumar wrote:
On Fri, Jun 27, 2014 at 6:14 PM, Andrzej Hajda a.ha...@samsung.com wrote:
On 06/27/2014 01:48 PM, Ajay kumar wrote:
On Fri, Jun 27, 2014
Hi Jassi,
On Thu, 2014-06-12 at 22:28 +0530, Jassi Brar wrote:
Hello,
Here is the next revision of Mailbox framwork.
I'm wondering whether you keep a Git tree with the framework we could
keep the Raspberry Pi mailbox driver based on (bcm2835-mbox)?
Also, from look at the API it does not
On 30 June 2014 21:46, Lubomir Rintel lkund...@v3.sk wrote:
Hi Jassi,
On Thu, 2014-06-12 at 22:28 +0530, Jassi Brar wrote:
Hello,
Here is the next revision of Mailbox framwork.
I'm wondering whether you keep a Git tree with the framework we could
keep the Raspberry Pi mailbox driver
Hi,
On Mon, Jun 23, 2014 at 01:20:57PM -0500, Felipe Balbi wrote:
Hi,
here's v3 of am437x sk support. Patches tested on top of next-20140617.
Note that this series was tested with the following extra patches:
http://marc.info/?l=linux-omapm=140299431732700w=2
Hello.
On 06/30/2014 07:44 PM, Antoine Ténart wrote:
+ /* set the controller speed */
+ writel(0x31, ctrl_reg + PORT_SCR_CTL);
Value undocumented? Or is this the SATA SControl register by chance?
Some magic is still there...
I guess Sergei was referring to AHCI spec
On Zynq I encountered issues due to rounding here and there. Often the
issue would have been resolved by rounding towards the requested
frequency. Unfortunately, the CCF does not specify the behavior of
clk_round_rate() in terms of rounding, making this proposed API
call useful for certain
Due to the clk_find_nearest_rate() API, OPPs can be specified
using proper rounding, now.
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
---
---
arch/arm/boot/dts/zynq-7000.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
Support the TI TAS2552 Class D amplifier.
The TAS2552 is a high efficiency Class-D audio
power amplifier with advanced battery current
management and an integrated Class-G boost
The device constantly measures the
current and voltage across the load and provides a
digital stream of this
On Sun, Jun 29, 2014 at 11:33:52PM +0900, Magnus Damm wrote:
On Sat, Jun 28, 2014 at 12:40 AM, Felipe Balbi ba...@ti.com wrote:
On Wed, Jun 18, 2014 at 02:15:42PM +0900, Magnus Damm wrote:
Hi Felipe,
On Fri, Jun 13, 2014 at 11:25 PM, Felipe Balbi ba...@ti.com wrote:
Hi,
On Fri,
Hi,
On Mon, Jun 30, 2014 at 06:10:59PM +0100, Dan Murphy wrote:
Support the TI TAS2552 Class D amplifier.
The TAS2552 is a high efficiency Class-D audio
power amplifier with advanced battery current
management and an integrated Class-G boost
The device constantly measures the
current and
Hi
On 06/30/2014 12:21 PM, Mark Rutland wrote:
Hi,
On Mon, Jun 30, 2014 at 06:10:59PM +0100, Dan Murphy wrote:
Support the TI TAS2552 Class D amplifier.
The TAS2552 is a high efficiency Class-D audio
power amplifier with advanced battery current
management and an integrated Class-G boost
On Thu, Jun 12, 2014 at 04:09:30PM +0100, Thomas Petazzoni wrote:
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1069,6 +1069,33 @@ static const struct l2c_init_data of_l2c310_data
__initconst = {
};
/*
+ * This is a variant of the of_l2c310_data with .sync set to
On 6/30/2014 3:43 AM, Grant Likely wrote:
Instead of splitting early_init_dt_scan(), the call to
early_init_dt_scan() could probably be moved after the
of_flat_dt_match_machine() call. It's at least worth a try. Looking at
the code I don't see anything obvious that requires the
Arnd Bergmann a...@arndb.de writes:
On Sunday 29 June 2014 20:32:20 Robert Jarzmik wrote:
As the RFC posted in [1] didn't meet an unrivaled success for
review, I'm posting this serie for PXA27x transition to clock
framework.
This transition is needed :
- to enable device-tree drivers
On Wed, Jun 18, 2014 at 06:22:30PM +0200, Sylwester Nawrocki wrote:
+struct odroidx2_drv_data odroidx2_drvdata = {
+ .dapm_widgets = odroidx2_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(odroidx2_dapm_widgets),
+};
+
+struct odroidx2_drv_data odroidu3_drvdata = {
Dear Catalin Marinas,
On Mon, 30 Jun 2014 18:32:17 +0100, Catalin Marinas wrote:
+/*
* Note that the end addresses passed to Linux primitives are
* noninclusive, while the hardware cache range operations use
* inclusive start and end addresses.
@@ -1487,6 +1514,10 @@ int __init
On Fri, Jun 20, 2014 at 01:33:15PM +0530, Tushar Behera wrote:
From: Wonjoon Lee woojoo@samsung.com
The MAX98091 CODEC is the same as MAX98090 CODEC, but with an extra
microphone. Existing driver for MAX98090 CODEC already has support
for MAX98091 CODEC. Adding proper compatible string
On Fri, Jun 20, 2014 at 01:33:16PM +0530, Tushar Behera wrote:
Peach-pi board has MAX98091 CODEC. Extend snow machine driver to support
this board.
Applied, thanks.
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