On Thursday 20 November 2014 06:02:13 Andrew Lunn wrote:
> On Wed, Nov 19, 2014 at 08:55:19PM -0500, Jason Cooper wrote:
> > Andrew,
> >
> > On Wed, Nov 19, 2014 at 12:01:36AM +0100, Arnaud Ebalard wrote:
> > >
> > > As reported by Andrew, the vendor prefix for Seiko Instruments, Inc.
> > > S-353
On Tue, 4 Nov 2014, Vignesh R wrote:
> This patch adds hwmod support for tscadc to work on am43xx-evm. The am33xx
> hwmod structures of tscadc has been moved to ipblock_data so that it can
> be reused in am43xx. The clock domain names are separately set for am33xx
> and am43xx. Thus tscadc dt entr
Hi Bjorn,
On Thu, Nov 20, 2014 at 2:43 AM, Bjorn Andersson wrote:
> I still have a huge problem understanding the awesomeness with the
> "base_id". If you have a SoC with 2 hwlock blocks; say 8+8 locks, used
> for interaction with e.g. a modem and a video core respectively.
> Why would you in eit
On Wed, Nov 19, 2014 at 08:55:19PM -0500, Jason Cooper wrote:
> Andrew,
>
> On Wed, Nov 19, 2014 at 12:01:36AM +0100, Arnaud Ebalard wrote:
> >
> > As reported by Andrew, the vendor prefix for Seiko Instruments, Inc.
> > S-35390A I2C RTC chip in kirkwood-synology.dtsi has a typo (ssi
> > instead
On 2014/11/20 1:18, Marc Zyngier wrote:
> Hi Yingjoe,
>
> On Wed, Nov 19 2014 at 2:14:08 pm GMT, Yingjoe Chen
> wrote:
>> Add support to use gic as a parent for stacked irq domain.
>>
>> Signed-off-by: Yingjoe Chen
>> ---
>> drivers/irqchip/Kconfig | 1 +
>> drivers/irqchip/irq-gic.c | 78
On Wed, Nov 19, 2014 at 05:15:47PM +0100, Nicolas Ferre wrote:
> On 19/11/2014 17:07, Boris Brezillon :
> > Hello,
> >
> > This series adds DT support for the TRNG (True Random Generator) block and
> > adds missing trng nodes to dtsi files.
>
> Nitpicking: subject of this cover letter seems not g
Hi,
On Tuesday 18 November 2014 05:38 PM, Yadwinder Singh Brar wrote:
This patch adds pinctrl configuration for using configuring gpx3-2 as an
external interrupt from max77686. Though max77686 RTC is enabled and gets
probed by default, it doesnt work as its unable to get interrupt.
This patch m
Hi,
On Tuesday 18 November 2014 05:38 PM, Yadwinder Singh Brar wrote:
With default config on smdk5250 latest tree throws below message :
[2.226049] thermal thermal_zone0: critical temperature reached(224
C),shutting down
[2.227840] reboot: Failed to start orderly shutdown: forcing the
Hi Marc,
On Wed, 2014-11-19 at 17:18 +, Marc Zyngier wrote:
> > +static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int
> > virq,
> > + unsigned int nr_irqs, void *arg)
> > +{
> > + int i, ret;
> > + irq_hw_number_t hwirq;
> > + unsigned int t
On Wed, Nov 19, 2014 at 7:04 PM, Brian Norris
wrote:
> On Sat, Nov 15, 2014 at 04:17:24PM -0800, Kevin Cernekee wrote:
>> The lack of a reboot handler is annoying; syscon-reboot probably won't work
>> on STB (because it requires two writes).
>
> Can't you reuse drivers/power/reset/brcmstb-reboot.c
On Wed, 2014-11-19 at 17:49 +, Marc Zyngier wrote:
> On Wed, Nov 19 2014 at 2:14:10 pm GMT, Yingjoe Chen
> wrote:
> > Add sysirq settings for mt6589/mt8135/mt8127
> > This also correct timer interrupt flag. The old setting works
> > because boot loader already set polarity for timer interrup
On Sat, Nov 15, 2014 at 04:17:24PM -0800, Kevin Cernekee wrote:
> The lack of a reboot handler is annoying; syscon-reboot probably won't work
> on STB (because it requires two writes).
Can't you reuse drivers/power/reset/brcmstb-reboot.c ?
Brian
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Andrew,
On Wed, Nov 19, 2014 at 12:01:36AM +0100, Arnaud Ebalard wrote:
>
> As reported by Andrew, the vendor prefix for Seiko Instruments, Inc.
> S-35390A I2C RTC chip in kirkwood-synology.dtsi has a typo (ssi
> instead of sii). This patches fixes it.
>
> Reported-by: Andrew Lunn
> Signed-off-
This adds binding documentation for Rockchip SoC VOP driver.
Signed-off-by: Mark Yao
---
Changes in v2:
- rename "lcdc" to "vop"
- add vop reset
- add iommu node
- add port for display-subsystem
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
Changes in v7: No
This add a display subsystem comprise the all display interface nodes.
Signed-off-by: Mark Yao
---
Changes in v2:
- add DRM master device node to list all display nodes that comprise
the graphics subsystem.
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
Cha
This patch adds the basic structure of a DRM Driver for Rockchip Socs.
Signed-off-by: Mark Yao
Signed-off-by: Daniel Kurtz
Acked-by: Daniel Vetter
Reviewed-by: Rob Clark
---
Changes in v2:
- use the component framework to defer main drm driver probe
until all VOP devices have been probed.
-
This a series of patches is a DRM Driver for Rockchip Socs, add support
for vop devices. Future patches will add additional encoders/connectors,
such as eDP, HDMI.
The basic "crtc" for rockchip is a "VOP" - Video Output Processor.
the vop devices found on Rockchip rk3288 Soc, rk3288 soc have two s
Quoting Scott Branden (2014-10-28 16:15:05)
> From: Jonathan Richardson
>
> Reviewed-by: Arun Parameswaran
> Tested-by: Jonathan Richardson
> Reviewed-by: JD (Jiandong) Zheng
> Reviewed-by: Ray Jui
> Signed-off-by: Scott Branden
Acked-by: Michael Turquette
> ---
> .../devicetree/bindings
On Wed, Nov 12, 2014 at 11:14 AM, Ohad Ben-Cohen wrote:
> Hi Suman,
[..]
>
> Does this mean you allow nodes not to have the base_id property? How
> do we protect against multiple nodes not having a base_id property
> then?
>
> Implicitly assuming a base_id value (zero in this case) may not be alwa
On Wed, Nov 19, 2014 at 07:52:44PM +0100, Kenneth Westfield wrote:
> From: Kenneth Westfield
>
> Add the CPU DAI driver for the QCOM LPASS SOC.
>
> Change-Id: I64ac4407dd32bb9a3066d4b7427292002eaf5d14
> Signed-off-by: Kenneth Westfield
> Signed-off-by: Banajit Goswami
> ---
[...]
> +#include
From: Rajendra Nayak
Document the LPASS (low power audio subsystem) clock controller
found on Qualcomm devices.
Cc:
Signed-off-by: Rajendra Nayak
Signed-off-by: Kumar Gala
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,lcc.txt | 21 +
1 file
This patchset adds support for the low power audio subsystem (lpass)
clock controller hardware. I split out the #define patch so that
it can go through the clock tree and the arm-soc tree in parallel
if desired. I'll be adding the apq/msm drivers shortly, but I wanted
to get this out for any feedba
On 11/20/2014 01:37 AM, Lee Jones wrote:
> On Wed, 19 Nov 2014, Beomho Seo wrote:
>
>> This patch adds a new driver for Richtek RT5033 driver.
>> RT5033 is a Multifunction device which includes battery charger, fuel gauge,
>> flash LED current source, LDO and synchronous Buck converter. It is
>>
This patchset adds common clock framework support for the TZ1090 SoC.
Patches 1 and 2 are generic and switch clk-divider to use masks
internally instead of shifts and width. Patch 1 came from Mike's divider
DT bindings patchset from a while back. This is required by the TZ1090
divider binding (pat
From: Mike Turquette
The forthcoming Device Tree binding for the divider clock type will use
a bitfield mask instead of bitfield width, which is what the current
basic divider implementation uses.
This patch replaces the u8 width in struct clk_divider with a u32 mask.
The divider code is updated
Add simple device tree binding for TZ1090 PLL clock. It takes a couple
of registers, and has a single reference clock source.
Signed-off-by: James Hogan
Cc: Mike Turquette
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: linux-me...@vger.kernel.org
Cc: dev
Expose a new function clk_register_divider_mask to set up a mask based
divider. This will be used by the upcoming TZ1090 divider driver whose
DT binding takes a mask rather than a shift and width.
Signed-off-by: James Hogan
Cc: Mike Turquette
---
drivers/clk/clk-divider.c| 25 ++
Add a driver for the main PLLs in the TZ1090 SoC, the system PLL and the
ADC PLL. The system PLL is used to derive the core Meta clock, the DDR
clock, and the system clock. The ADC PLL can be used for various
purposes, but is usually used for the pixel clock.
The PLL is a True Circuits PLL, but th
Add DT binding for a bank of clock muxes in the TZ1090 SoC. There are
several such registers which contain only bits controlling clock muxes.
The bit-mask property determines the mask of bits of the register which
control muxes. The number of output clocks is equal to the number of set
bits in the
Add a clock driver for banks of clock gates in the TZ1090 SoC. A single
32 bit register controls up to 32 separate clock gates. The driver
instantiates separate generic clock gates. The clock operations are
wrapped in order to acquire and release the Meta global exclusive lock
(__global_lock2) to e
Add DT binding for a bank of clock gates in the TZ1090 SoC. There are
several such registers which contain only bits controlling clock gates.
The bit-mask property determines the mask of bits of the register which
control gates. The number of input (and output) clocks is equal to the
number of set
Add DT binding for the clock deleters in the TZ1090 SoC, which delete up
to 1023 out of every 1024 clock pulses of the input clock.
Signed-off-by: James Hogan
Cc: Mike Turquette
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: linux-me...@vger.kernel.org
C
Add a clock driver for banks of clock muxes in the TZ1090 SoC. A single
32 bit register controls up to 32 separate clock muxes. The driver
instantiates separate generic clock muxes. The clock operations are
wrapped in order to acquire and release the Meta global exclusive lock
(__global_lock2) to e
The TZ1090 PDC (PowerDown Controller) clock should be at 32.768KHz, and
is generated either directly from the XTAL3 clock or by dividing the
XTAL1 clock. Both the divide and the mux are in a single register which
also contains GPIO output data, and may need to be used by other
non-Linux cores and t
The TZ1090 PDC (PowerDown Controller) clock should be at 32.768KHz, and
is generated either directly from the XTAL3 clock or by dividing the
XTAL1 clock. Both the divide and the mux are in a single register which
also contains GPIO output data, and may need to be used by other
non-Linux cores and t
Add driver for TZ1090 clock deleter, which deletes up to 1023 out of
every 1024 clock pulses. Two of these exist, one for the Meta core and
the other for the system clock.
Signed-off-by: James Hogan
Cc: Mike Turquette
Cc: linux-me...@vger.kernel.org
---
drivers/clk/tz1090/Makefile |
Enable the common clock framework for the TZ1090 SoC, add a tz1090_clk
device tree file describing the clocks, and connect the Meta core clock
so that the rate of the Meta timer can be determined.
Most of the clock tree is described apart from some AFE clocks which
aren't usually of much interest
Add binding for TZ1090 divider clock. This supports a subset of the
functionality of the generic divider, and by being specific to the
TZ1090 SoC it allows policy decisions to be made from the driver.
Signed-off-by: James Hogan
Cc: Mike Turquette
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Add driver for TZ1090 clock divider, which divides an input clock by an
integer.
Two policy decisions are made depending on the MMIO address of the
divider:
- The UART clock divider sets CLK_SET_RATE_PARENT so that clock changes
can propagate up to the CLK_UART_SW mux which allows more precision
Naidu,
On Fri, Nov 14, 2014 at 7:37 AM, wrote:
> From: Naidu Tellapati
>
> The Pistachio SOC from Imagination Technologies includes a Pulse Width
> Modulation DAC which produces 1 to 4 digital bit-outputs which represent
> digital waveforms. These PWM outputs are primarily in charge of controll
Daniel,
On Wed, Oct 8, 2014 at 12:33 AM, Sonny Rao wrote:
> From: Doug Anderson
>
> Some 32-bit (ARMv7) systems are architected like this:
>
> * The firmware doesn't know and doesn't care about hypervisor mode and
> we don't want to add the complexity of hypervisor there.
>
> * The firmware is
On Wed, Nov 19, 2014 at 07:52:49PM +0100, Kenneth Westfield wrote:
> From: Kenneth Westfield
>
> Model the LPASS audio hardware for the IPQ806X.
>
> Change-Id: Ide1aa0d09c23d4496aa9c40e3c9878a968261f11
As Kumar mentioned, please exclude this.
> Signed-off-by: Kenneth Westfield
> Signed-off-by
On 11/19/14, 12:52 PM, Kenneth Westfield wrote:
From: Kenneth Westfield
Add the CPU DAI driver for the QCOM LPASS SOC.
Change-Id: I64ac4407dd32bb9a3066d4b7427292002eaf5d14
Signed-off-by: Kenneth Westfield
Signed-off-by: Banajit Goswami
---
sound/soc/qcom/lpass-cpu-dai.c | 307 +
On 11/19/14, 12:52 PM, Kenneth Westfield wrote:
From: Kenneth Westfield
Add PCM platform driver for the LPASS I2S port.
Change-Id: If6516fb615b16551817fd9248c1c704fe521fb32
Signed-off-by: Kenneth Westfield
Signed-off-by: Banajit Goswami
---
sound/soc/qcom/lpass-pcm-mi2s.c | 390 +++
On Nov 19, 2014, at 12:52 PM, Kenneth Westfield wrote:
> From: Kenneth Westfield
>
> This set of patches adds support for audio on the Qualcomm Technologies
> ipq806x SOC.
>
> The ipq806x SOC has audio-related hardware blocks in its low-power audio
> subsystem (or LPASS). One of the relevant
On 11/19/2014 12:03 PM, Frank Rowand wrote:
> On 11/19/2014 11:30 AM, Frank Rowand wrote:
>> On 11/19/2014 5:56 AM, Grant Likely wrote:
>>> On Wed, Nov 19, 2014 at 1:37 AM, Frank Rowand
>>> wrote:
>
> < snip >
>
>> I include a patch below to also drop the *next pointer. Not to actually
>> prop
On 11/19/2014 11:30 AM, Frank Rowand wrote:
> On 11/19/2014 5:56 AM, Grant Likely wrote:
>> On Wed, Nov 19, 2014 at 1:37 AM, Frank Rowand wrote:
< snip >
> I include a patch below to also drop the *next pointer. Not to actually
> propose submitting the patch, but to suggest that Gaurav's patch
Hi Andrew & Ezequiel,
Signed-off-by: Jude Abraham
Signed-off-by: Naidu Tellapati
>>>
>>> checkpatch reports that there's trailing whitespace and that you're
>>> using DOS line endings. Please be sure to fix that with this and your
>>> other patches.
>>>
>>
>> Andrew,
>>
>> Saving
On Wed, Nov 19, 2014 at 11:27 AM, Ezequiel Garcia
wrote:
>
>
> On 11/18/2014 08:12 PM, Andrew Bresticker wrote:
>> Naidu,
>>
>> On Tue, Nov 18, 2014 at 4:07 AM, wrote:
>>> From: Naidu Tellapati
>>>
>>> This commit adds support for ImgTec PowerDown Controller Watchdog Timer.
>>>
>>> Signed-off-b
On 11/19/2014 5:56 AM, Grant Likely wrote:
> On Wed, Nov 19, 2014 at 1:37 AM, Frank Rowand wrote:
>> On 11/18/2014 7:10 AM, Grant Likely wrote:
>>> On Sun, 16 Nov 2014 20:52:56 -0800
>>> , Gaurav Minocha
>>> wrote:
This patch improves the implementation of device tree structure.
T
On 11/18/2014 08:12 PM, Andrew Bresticker wrote:
> Naidu,
>
> On Tue, Nov 18, 2014 at 4:07 AM, wrote:
>> From: Naidu Tellapati
>>
>> This commit adds support for ImgTec PowerDown Controller Watchdog Timer.
>>
>> Signed-off-by: Jude Abraham
>> Signed-off-by: Naidu Tellapati
>
> checkpatch r
Quoting Geert Uytterhoeven (2014-11-10 10:49:34)
> Commit 8e33f91a0b84ae19 ("clk: shmobile: clk-mstp: change to using
> clock-indices") forgot to replace all occurrences of
> "renesas,clock-indices" in the driver-specific binding documentation.
>
> Signed-off-by: Geert Uytterhoeven
> Acked-by: Si
Paolo Pisati writes:
> On Wed, Nov 19, 2014 at 10:35:40AM +0100, Javier Martinez Canillas wrote:
>> Hello Ajay,
>>
>> On 11/18/2014 07:20 AM, Ajay kumar wrote:
>> > On Sat, Nov 15, 2014 at 3:24 PM, Ajay Kumar
>> > wrote:
>> >> This series is based on master branch of Linus tree at:
>> >> git:/
From: Kenneth Westfield
Model the LPASS audio hardware for the IPQ806X.
Change-Id: Ide1aa0d09c23d4496aa9c40e3c9878a968261f11
Signed-off-by: Kenneth Westfield
Signed-off-by: Banajit Goswami
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 33 +
1 file changed, 33 inser
From: Kenneth Westfield
This set of patches adds support for audio on the Qualcomm Technologies
ipq806x SOC.
The ipq806x SOC has audio-related hardware blocks in its low-power audio
subsystem (or LPASS). One of the relevant blocks in the LPASS is its
low-power audio interface (or LPAIF). This
From: Kenneth Westfield
Now all drivers are in place, allow them to build.
Change-Id: I16b9c4c2796bc1cf86aecae5fc500e685906fa8f
Signed-off-by: Kenneth Westfield
Signed-off-by: Banajit Goswami
---
sound/soc/qcom/Kconfig | 43 +++
sound/soc/qcom/Makefile
From: Kenneth Westfield
Add PCM platform driver for the LPASS I2S port.
Change-Id: If6516fb615b16551817fd9248c1c704fe521fb32
Signed-off-by: Kenneth Westfield
Signed-off-by: Banajit Goswami
---
sound/soc/qcom/lpass-pcm-mi2s.c | 390
sound/soc/qcom/lpass
From: Kenneth Westfield
Add documentation to the sound directory of the
device-tree bindings for IPQ806x audio drivers.
Change-Id: I7dd08be2a68579675a6916ecb72b943dea0e352b
Signed-off-by: Kenneth Westfield
Signed-off-by: Banajit Goswami
---
.../bindings/sound/qcom,ipq806x-snd-card.txt |
From: Kenneth Westfield
Add machine driver for the IPQ806X LPASS SOC.
Change-Id: Ica26398fafd3098cdd12dcf45ebccec2ad820002
Signed-off-by: Kenneth Westfield
Signed-off-by: Banajit Goswami
---
sound/soc/qcom/ipq806x.c | 221 +++
1 file changed, 221 in
From: Kenneth Westfield
Change-Id: I3e33dcff96e85c7be790f9b84d7755858a52644e
Signed-off-by: Kenneth Westfield
Signed-off-by: Banajit Goswami
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
e4f712785554a691f7f31dba57b600102b32554e..fe9
From: Kenneth Westfield
Allow for the QCOM LPASS drivers to build.
Change-Id: Ic870d8e9487cebe634c8bd2f1c7263c27237febc
Signed-off-by: Kenneth Westfield
Signed-off-by: Banajit Goswami
---
sound/soc/Kconfig | 1 +
sound/soc/Makefile | 1 +
2 files changed, 2 insertions(+)
diff --git a/sound/
From: Kenneth Westfield
Add the native LPAIF driver for LPASS block in Qualcomm
Technologies SoCs.
Change-Id: I0f06f73a1267d7721209e58ce18e0d4897001141
Signed-off-by: Kenneth Westfield
Signed-off-by: Banajit Goswami
---
sound/soc/qcom/lpass-lpaif.c | 488 ++
From: Kenneth Westfield
Add the CPU DAI driver for the QCOM LPASS SOC.
Change-Id: I64ac4407dd32bb9a3066d4b7427292002eaf5d14
Signed-off-by: Kenneth Westfield
Signed-off-by: Banajit Goswami
---
sound/soc/qcom/lpass-cpu-dai.c | 307 +
1 file changed, 307 i
On Wed, Nov 19, 2014 at 4:48 AM, Dan Murphy wrote:
> Introduce the Texas Instruments lp8860
> 4 channel LED driver.
>
> This driver configures the device in display cluster mode
> as this seems to be the most used configuration at the
> time of the driver configuration.
>
> For more product inform
Hi Ian,
On Wed, 2014-11-19 at 13:09 +, Ian Campbell wrote:
> On Tue, 2014-11-18 at 22:11 +, Grant Likely wrote:
> > > > * It also helps with exposing the reserved map to userspace, but kexec
> > > > has done without that feature for years, and it is in the process of
> > > > being depr
On Wed, Nov 19, 2014 at 02:14:11PM +, Yingjoe Chen wrote:
> Add binding documentation for Mediatek SoC SYSIRQ.
>
> Signed-off-by: Yingjoe Chen
> ---
> .../bindings/arm/mediatek/mediatek,sysirq.txt | 26
> ++
> 1 file changed, 26 insertions(+)
> create mode 100644
On Wed, Nov 19, 2014 at 02:14:09PM +, Yingjoe Chen wrote:
> Mediatek SoCs have interrupt polarity support in sysirq which
> allows to invert polarity for given interrupt. Add this support
> using hierarchy irq domain.
>
> Signed-off-by: Yingjoe Chen
> ---
> drivers/irqchip/Makefile |
Hi Pavel,
Pavel Machek wrote:
> On Mon 2014-11-17 07:06:17, Tony Lindgren wrote:
>> * Pali Rohár [141117 07:03]:
>>> On Monday 17 November 2014 15:55:46 Tony Lindgren wrote:
There's nothing stopping us from initializing the camera code
from pdata-quirks.c for now to keep it working
Hi Jacek and Pavel,
Jacek Anaszewski wrote:
> Hi Pavel, Sakari,
>
> On 11/18/2014 05:51 PM, Pavel Machek wrote:
>> Hi!
>>
If the hardware LED changes with one that needs different current, the
block for the adp1653 stays the same, but white LED block should be
updated with differen
On Wed, Nov 19 2014 at 2:14:10 pm GMT, Yingjoe Chen
wrote:
> Add sysirq settings for mt6589/mt8135/mt8127
> This also correct timer interrupt flag. The old setting works
> because boot loader already set polarity for timer interrupt.
> Without intpol support, the setting was not changed so gic
>
On Fri, Nov 14 2014 at 08:56 -0700, Daniel Lezcano wrote:
On 10/25/2014 01:40 AM, Lina Iyer wrote:
+/**
+ * spm_set_low_power_mode() - Configure SPM start address for low power mode
+ * @mode: SPM LPM mode to enter
+ */
+int qcom_spm_set_low_power_mode(enum pm_sleep_mode mode)
+{
+ struc
On Wed, 19 Nov 2014 18:35:56 +0100
Nicolas Ferre wrote:
> On 19/11/2014 17:18, Boris Brezillon :
> > On Wed, 19 Nov 2014 17:15:47 +0100
> > Nicolas Ferre wrote:
> >
> >> On 19/11/2014 17:07, Boris Brezillon :
> >>> Hello,
> >>>
> >>> This series adds DT support for the TRNG (True Random Generat
On 19/11/2014 17:18, Boris Brezillon :
> On Wed, 19 Nov 2014 17:15:47 +0100
> Nicolas Ferre wrote:
>
>> On 19/11/2014 17:07, Boris Brezillon :
>>> Hello,
>>>
>>> This series adds DT support for the TRNG (True Random Generator) block and
>>> adds missing trng nodes to dtsi files.
>>
>> Nitpicking:
On 11/19/2014 10:49 PM, Mason wrote:
> On 19/11/2014 17:57, Victor Ascroft wrote:
>
>> This actually depends on the kernel you are using. Do you have relatively
>> new kernel or an old one? Depending on that, either you will get that
>> information in a board file or else in the device tree in ar
On 19/11/2014 17:57, Victor Ascroft wrote:
This actually depends on the kernel you are using. Do you have relatively
new kernel or an old one? Depending on that, either you will get that
information in a board file or else in the device tree in arch/arm/boot/dts.
I'll reply more thoroughly lat
Hi Yingjoe,
On Wed, Nov 19 2014 at 2:14:08 pm GMT, Yingjoe Chen
wrote:
> Add support to use gic as a parent for stacked irq domain.
>
> Signed-off-by: Yingjoe Chen
> ---
> drivers/irqchip/Kconfig | 1 +
> drivers/irqchip/irq-gic.c | 78
> ---
>
The removal path for selftest data has an off by one error that causes
the code to dereference beyond the end of the nodes[] array on the first
pass through. The old code only worked by chance on a lot of platforms,
but the bug was recently exposed on aarch64.
The fix is simple. Decrement the node
Hello Andreas,
On 11/19/2014 04:56 PM, Andreas Färber wrote:
> The HP Chromebook 11 uses an Atmel maXTouch as trackpad.
> The keymap was found by trial-and-error.
>
> Signed-off-by: Andreas Färber
Patch looks good to me.
Reviewed-by: Javier Martinez Canillas
Best regards,
Javier
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Hello Andreas,
On 11/19/2014 04:56 PM, Andreas Färber wrote:
> multi_v7_defconfig has it as Y already, so build it in here, too, for
> consistency, and therefore build in HWMON as well.
>
> Signed-off-by: Andreas Färber
Reviewed-by: Javier Martinez Canillas
Best regards,
Javier
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Hello Andreas,
On 11/19/2014 04:56 PM, Andreas Färber wrote:
> Spotted in the Chrome OS 3.8 based device tree.
> Needs CONFIG_SENSORS_LM90.
>
> Signed-off-by: Andreas Färber
Reviewed-by: Javier Martinez Canillas
Best regards,
Javier
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On Tue, 18 Nov 2014, Sascha Hauer wrote:
> On Tue, Nov 18, 2014 at 11:46:45AM +, Lee Jones wrote:
> > On Mon, 17 Nov 2014, Flora Fu wrote:
> >
> > > Add PMIC wrapper of MT8135 to access MFD MT6397.
> > > This is regmap of MT6397 MFD.
> > >
> > > Signed-off-by: Flora Fu
> > > ---
> > > driv
Hello Andreas,
On 11/19/2014 04:56 PM, Andreas Färber wrote:
> Reported-by: Doug Anderson
> Signed-off-by: Andreas Färber
Even though the patch is simple and is true that the subject explains
the change, I think that is always good to have a commit message anyways.
Patch looks good to me thoug
On 11/19/2014 06:20 PM, Mason wrote:
> Hello everyone,
>
> I've been using several Linux distributions, and writing user-space programs,
> for 15 years.
> I recently seized an opportunity to move into kernel development, mainly
> writing drivers
> for an ARM SoC, and I'm finding the transition h
On Wed, Nov 19, 2014 at 05:40:50PM +0100, Jean-Francois Moine wrote:
> On Wed, 19 Nov 2014 11:32:29 +
> Russell King wrote:
>
> > + lcd1: lcd-controller@81 {
> > + compatible = "marvell,dove-lcd";
> > + reg = <0x81
On 19/11/2014 12:07, Vinod Koul :
> On Wed, Nov 19, 2014 at 12:03:31PM +0100, Nicolas Ferre wrote:
>> On 06/11/2014 06:27, Vinod Koul :
>>> On Wed, Oct 22, 2014 at 05:22:17PM +0200, Ludovic Desroches wrote:
Hi,
This set of patches introduces support for the new Atmel DMA controller
Am 19.11.2014 um 17:28 schrieb Javier Martinez Canillas:
> On 11/19/2014 05:22 PM, Paolo Pisati wrote:
>> On Wed, Nov 19, 2014 at 12:20:53PM +0100, Javier Martinez Canillas wrote:
>>>
>>> If someone else is interested, I've pushed a branch [0] with 3.18-rc5 + all
>>> the needed patches.
>>>
>>> Aja
On Tue, 18 Nov 2014, Mike Turquette wrote:
> Quoting Chanwoo Choi (2014-11-18 00:59:41)
> > This patch adds the support for S2MPS13 PMIC clock which is same with
> > existing
> > S2MPS14 RTC IP. But, S2MPS13 uses all of clocks (32khz_{ap|bt|cp}).
> >
> > Cc: Mike Turquette
> > Signed-off-by: Ch
On Wed, 19 Nov 2014 11:32:29 +
Russell King wrote:
> + lcd1: lcd-controller@81 {
> + compatible = "marvell,dove-lcd";
> + reg = <0x81 0x1000>;
> + interrupts = <46>;
> +
On Wed, 19 Nov 2014, Beomho Seo wrote:
> This patch adds a new driver for Richtek RT5033 driver.
> RT5033 is a Multifunction device which includes battery charger, fuel gauge,
> flash LED current source, LDO and synchronous Buck converter. It is interfaced
> to host controller using I2C interface.
On Wed, Nov 19, 2014 at 3:39 PM, Rob Herring wrote:
> On Wed, Nov 19, 2014 at 8:49 AM, Arnd Bergmann wrote:
>> On Wednesday 19 November 2014 08:45:58 Rob Herring wrote:
>>> > static inline struct device_node *dev_of_node(struct device *of_node)
>>> > {
>>> > if (!IS_ENABLED(CONFIG_OF))
>>
Hello Paolo,
On 11/19/2014 05:22 PM, Paolo Pisati wrote:
> On Wed, Nov 19, 2014 at 12:20:53PM +0100, Javier Martinez Canillas wrote:
>>
>> If someone else is interested, I've pushed a branch [0] with 3.18-rc5 + all
>> the needed patches.
>>
>> Ajay, feel free to add to your series:
>>
>> Tested
On Wed, Nov 19, 2014 at 6:49 AM, Grant Likely wrote:
> On Wed, 12 Nov 2014 12:54:03 -0800
> , Kevin Cernekee
> wrote:
>> With a few tweaks, the PXA serial driver can handle other 16550A clones.
>> Add a fifo-size DT property to override the FIFO depth (BCM7xxx uses 32),
>> and {native,big}-endia
On Wed, Nov 19, 2014 at 12:20:53PM +0100, Javier Martinez Canillas wrote:
>
> If someone else is interested, I've pushed a branch [0] with 3.18-rc5 + all
> the needed patches.
>
> Ajay, feel free to add to your series:
>
> Tested-by: Javier Martinez Canillas
>
> Best regards,
> Javier
>
> [0]
On 19/11/2014 17:07, Boris Brezillon :
> Hello,
>
> This series adds DT support for the TRNG (True Random Generator) block and
> adds missing trng nodes to dtsi files.
Nitpicking: subject of this cover letter seems not good ;-)
Herbert, do you think you can take this series yourself or do I have
On Wed, 19 Nov 2014 17:15:47 +0100
Nicolas Ferre wrote:
> On 19/11/2014 17:07, Boris Brezillon :
> > Hello,
> >
> > This series adds DT support for the TRNG (True Random Generator) block and
> > adds missing trng nodes to dtsi files.
>
> Nitpicking: subject of this cover letter seems not good ;
Hello,
This series adds DT support for the TRNG (True Random Generator) block and
adds missing trng nodes to dtsi files.
Best Regards,
Boris
Boris Brezillon (4):
hwrng: atmel: use clk_prepapre_enable/_disable_unprepare
hwrng: atmel: add DT support
hwrng: atmel: Add TRNG DT binding doc
Add a DT node for the TRNG (True Random Number Generator) block.
Keep this block enabled as it does not depend on any external connection,
and thus should be available on all boards.
Signed-off-by: Boris Brezillon
Acked-by: Nicolas Ferre
---
arch/arm/boot/dts/at91sam9g45.dtsi | 7 +++
1 fi
Use clk_prepare_enable/_disable_unprepare instead of clk_enable/disable
to work properly with the CCF.
Signed-off-by: Boris Brezillon
Acked-by: Peter Korsgaard
Acked-by: Nicolas Ferre
---
drivers/char/hw_random/atmel-rng.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --g
Hello Andreas,
On 19/11/2014 16:02, Andreas Färber wrote:
Am 19.11.2014 um 13:50 schrieb Mason:
[...] I'm writing a driver for a temperature sensor, which is
supposed to work within the hwmon/lm-sensors framework.
The sensor's API consists of 3 memory-mapped registers, which are
accessible o
Add DT support.
Make the driver depend on CONFIG_OF as at91sam9g45 was the only SoC making
use of the TRNG block and this SoC is now fully migrated to DT.
Signed-off-by: Boris Brezillon
Acked-by: Nicolas Ferre
---
drivers/char/hw_random/Kconfig | 2 +-
drivers/char/hw_random/atmel-rng.c |
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