Hi Max
On 09/23/2015 09:37 PM, Maxime Coquelin wrote:
A borad might not expose the USB2.0 ports, so disable them by default in SoC
typo borad
Otherwise, for the series
Acked-by: Patrice Chotard
Patrice
file, and enable them in b2120 board.
Signed-off-by: Maxime Coquelin
---
arch/arm
On Thu, Sep 24, 2015 at 12:05:17AM +0800, Chen-Yu Tsai wrote:
> Reduced Serial Bus is a proprietary 2-line push-pull serial bus supporting
> multiple slave devices. It was developed by Allwinner, Inc. and used by
> Allwinner and X-Powers, Inc. for their line of PMICs and other peripheral
> ICs.
>
Hi,
On Mon, Sep 21, 2015 at 04:42:09PM -0700, Linus Walleij wrote:
> On Sun, Aug 30, 2015 at 12:44 AM, Markus Pargmann wrote:
>
> > This functions adds a way to initialize a GPIO without hogging it.
> >
> > Signed-off-by: Markus Pargmann
>
> (...)
>
> > -The GPIO chip may contain GPIO hog def
Hi,
On Mon, Sep 21, 2015 at 04:28:48PM -0700, Linus Walleij wrote:
> On Sun, Aug 30, 2015 at 12:44 AM, Markus Pargmann wrote:
>
> > The gpio name is now stored in the gpio descriptor, so we can simply use
> > that instead of an argument to the function.
> >
> > Signed-off-by: Markus Pargmann
>
On Wed, Sep 23, 2015 at 08:33:41AM -0700, Shawn Guo wrote:
> On Tue, Sep 15, 2015 at 06:01:01PM +0800, Shengjiu Wang wrote:
> > As spdif driver will register SPDIF clock to regmap, regmap will do
> > clk_prepare in init function, so SPDIF clock is prepared in probe, then its
> > root clock (pll clo
On 9/23/2015 2:55 PM, Ray Jui wrote:
>
>
> On 9/23/2015 2:29 PM, Arnd Bergmann wrote:
>> On Friday 18 September 2015 15:11:27 Ray Jui wrote:
>>> On 9/18/2015 2:34 PM, Arnd Bergmann wrote:
On Friday 18 September 2015 14:24:10 Ray Jui wrote:
> + soc {
> + compatib
DT binding documentation for this new ASoC driver.
Signed-off-by: Songjun Wu
---
Changes in v2:
- Delete the device node "Sound".
.../devicetree/bindings/sound/atmel-classd.txt | 52
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindin
The Audio Class D Amplifier driver includes two parts.
1) Driver code to implement the Audio Class D Amplifier function.
2) Device tree binding document, it describes how to add the Audio
Class D Amplifier in device tree.
Changes in v2:
- Change the "Mono", "Swap" and "Deemphasis" controls to
On 2015年09月17日 23:09, Heiko Stübner wrote:
Am Donnerstag, 17. September 2015, 18:32:49 schrieb Xing Zheng:
Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.
Signed-off-by: Xing Zheng
---
Changes in v2: None
.../bindings/clock/
From: Dinh Nguyen
Add the base DTS for Altera's SoCFPGA Stratix 10 platform.
Signed-off-by: Dinh Nguyen
---
v4: Add a non-zero ranges property for /soc node
v3: change #address-cells and #size-cells to <2>
change the GIC address to 0xfffc1000
update the GIC virtual CPU reg length to 0x2
Hi Dmitry,
在 2015年09月22日 01:08, Dmitry Torokhov 写道:
Hi Caesar,
On Mon, Sep 21, 2015 at 12:16:08PM +0800, Caesar Wang wrote:
The RK3368 SoCs support to 2 channel TS-ADC, the temperature criteria
of each channel can be configurable.
The system has two Temperature Sensors, channel 0 is for CPU,
On 2015年09月17日 17:25, Heiko Stübner wrote:
Am Donnerstag, 17. September 2015, 16:28:53 schrieb Xing Zheng:
Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.
Signed-off-by: Xing Zheng
---
Changes in v2: None
include/
On 2015年09月17日 17:18, Heiko Stübner wrote:
Am Donnerstag, 17. September 2015, 16:28:52 schrieb Xing Zheng:
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3036-sd
On 2015/9/21 22:52, Rob Herring wrote:
On 09/17/2015 01:51 AM, huangdaode wrote:
The Hisilicon Network Subsystem is a long term evolution IP which is
supposed to be used in Hisilicon ICT SoC. The IP, which is called hns
for short, is a TCP/IP acceleration engine, which can directly decode
TCP/IP
Add EDAC support for the SoC component.
Signed-off-by: Loc Ho
---
drivers/edac/xgene_edac.c | 498 +
1 files changed, 498 insertions(+), 0 deletions(-)
diff --git a/drivers/edac/xgene_edac.c b/drivers/edac/xgene_edac.c
index 37121e8..bfca5d2 100644
-
Add EDAC support for the L3 component.
Signed-off-by: Loc Ho
---
drivers/edac/xgene_edac.c | 669 -
1 files changed, 474 insertions(+), 195 deletions(-)
diff --git a/drivers/edac/xgene_edac.c b/drivers/edac/xgene_edac.c
index 5ff42d5..37121e8 100644
Add L3/SoC DT subnodes to the APM X-Gene SoC EDAC node.
Signed-off-by: Loc Ho
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index d831b
Update documentation for the APM X-Gene SoC EDAC DTS binding for L3/SoC
subnodes.
Signed-off-by: Loc Ho
---
.../devicetree/bindings/edac/apm-xgene-edac.txt| 23
1 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/edac/apm-x
v5:
* Drop the EDAC debugfs export and use the wrapper from maintainer
* Clean up debugfs node function to make use of function wrapper
* Clean up function xgene_edac_l3_v1_errata_chk
* Move SoC part into another patch
* Tested with
git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git#edac-debu
On Fri, Sep 11, 2015 at 12:53 AM, Yuan Yao wrote:
> Add Freescale Queue Direct Memory Access(qDMA) controller support.
> This module can be found on LS-1 and LS-2 SoCs.
>
> This add the legacy mode support for qDMA.
>
> Signed-off-by: Yuan Yao
> ---
> Documentation/devicetree/bindings/dma/fsl-qd
From: Russell King - ARM Linux
Date: Tue, 22 Sep 2015 17:17:10 +0100
> This is the second version of the series, with the comments David had
> on the first patch fixed up. Original series description with updated
> diffstat below.
This needs some build fixes:
drivers/net/ethernet/apm/xgene/xge
On Wed, Sep 23, 2015 at 12:10:13PM -0500, atull wrote:
> On Tue, 22 Sep 2015, Josh Cartwright wrote:
[..]
> > > +struct fpga_manager *of_fpga_mgr_get(struct device_node *node)
> > > +{
> > > + struct fpga_manager *mgr;
> > > + struct device *dev;
> > > +
> > > + if (!node)
> > > + return ER
On Wed, Sep 23, 2015 at 11:43:25PM +0100, Dinh Nguyen wrote:
> On Wed, Sep 23, 2015 at 12:54 AM, Mark Rutland wrote:
> >> +/ {
> >> + compatible = "altr,socfpga-stratix10";
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >
> > [...]
> >
> >> + soc {
> >> + #add
On Wed, Sep 23, 2015 at 12:54 AM, Mark Rutland wrote:
>> +/ {
>> + compatible = "altr,socfpga-stratix10";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>
> [...]
>
>> + soc {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible
From: Dinh Nguyen
On the Arria10 Devkit, the I2C bus has a serial EEPROM and an RTC
hanging off it. Also, enable the USB node.
Signed-off-by: Dinh Nguyen
---
arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/b
From: Dinh Nguyen
Add the required clock fields for all the I2C nodes. Also add missing clock
fields for UART0 and USB1.
Signed-off-by: Dinh Nguyen
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi
b/a
On 17 September 2015 at 17:20, Shawn Lin wrote:
> On 2015/9/17 19:44, Ulf Hansson wrote:
>>
>> On 14 September 2015 at 08:29, Shawn Lin wrote:
>>>
>>> This patch adds Generic PHY access for sdhci-of-arasan. Driver
>>> can get PHY handler from dt-binding, and power-on/init the PHY.
>>> Also we add
On 9/23/2015 2:29 PM, Arnd Bergmann wrote:
> On Friday 18 September 2015 15:11:27 Ray Jui wrote:
>> On 9/18/2015 2:34 PM, Arnd Bergmann wrote:
>>> On Friday 18 September 2015 14:24:10 Ray Jui wrote:
+ soc {
+ compatible = "simple-bus";
+ ranges;
>>
On 23/09/15 14:46, Ray Jui wrote:
>
>
> On 9/23/2015 2:31 PM, Arnd Bergmann wrote:
>> On Friday 18 September 2015 14:44:54 Ray Jui wrote:
>>> On 9/18/2015 2:27 PM, Arnd Bergmann wrote:
On Friday 18 September 2015 14:24:06 Ray Jui wrote:
The SoC has at least four uarts according to
On 9/23/2015 2:31 PM, Arnd Bergmann wrote:
> On Friday 18 September 2015 14:44:54 Ray Jui wrote:
>> On 9/18/2015 2:27 PM, Arnd Bergmann wrote:
>>> On Friday 18 September 2015 14:24:06 Ray Jui wrote:
>>>
>>> The SoC has at least four uarts according to this, so it seems unlikely that
>>> each boar
> +/ {
> + compatible = "altr,socfpga-stratix10";
> + #address-cells = <2>;
> + #size-cells = <2>;
[...]
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + device_type = "soc";
> +
On Friday 18 September 2015 14:44:54 Ray Jui wrote:
> On 9/18/2015 2:27 PM, Arnd Bergmann wrote:
> > On Friday 18 September 2015 14:24:06 Ray Jui wrote:
> >
> > The SoC has at least four uarts according to this, so it seems unlikely that
> > each board really only uses only the fourth one of them
On Friday 18 September 2015 15:11:27 Ray Jui wrote:
> On 9/18/2015 2:34 PM, Arnd Bergmann wrote:
> > On Friday 18 September 2015 14:24:10 Ray Jui wrote:
> >> + soc {
> >> + compatible = "simple-bus";
> >> + ranges;
> >> + #address-cells = <1>;
> >> +
On Wednesday 23 September 2015 21:39:27 Arnd Bergmann wrote:
> On Wednesday 23 September 2015 20:35:45 Will Deacon wrote:
> >
> > From what Lorenzo was saying, ACPI shares the interpretation that David is
> > implementing here and, given that the DT version seems to be subjective,
> > aligning thi
On Wed, Sep 23, 2015 at 02:34:27PM -0500, Andreas Dannenberg wrote:
> On Tue, Sep 22, 2015 at 09:37:20PM +0200, Sebastian Reichel wrote:
> >
> > I guess you can just handle this like an optional gpio
> >
> > if(bq->pg)
> > state->power_good = !gpiod_get_value_cansleep(bq->pg);
> > else
> >
On Wed, Sep 23, 2015 at 08:53:59PM +0200, Sebastian Reichel wrote:
> Hi,
>
> On Wed, Sep 23, 2015 at 01:32:58PM -0500, Andreas Dannenberg wrote:
> > On Wed, Sep 23, 2015 at 05:02:28PM +0200, Sebastian Reichel wrote:
> > > On Wed, Sep 23, 2015 at 09:11:46AM -0500, Andreas Dannenberg wrote:
> > > >
On Wed, Sep 23, 2015 at 08:39:27PM +0100, Arnd Bergmann wrote:
> On Wednesday 23 September 2015 20:35:45 Will Deacon wrote:
> > On Wed, Sep 23, 2015 at 08:27:41PM +0100, Arnd Bergmann wrote:
> > > On Wednesday 23 September 2015 11:21:56 David Daney wrote:
> > > > >>
> > > > >> /* Limit the bus
On Wednesday 23 September 2015 20:35:45 Will Deacon wrote:
> On Wed, Sep 23, 2015 at 08:27:41PM +0100, Arnd Bergmann wrote:
> > On Wednesday 23 September 2015 11:21:56 David Daney wrote:
> > > >>
> > > >> /* Limit the bus-range to fit within reg */
> > > >> -bus_max = pci->cfg.bus_range->s
The PWM may not be used on some boards, so enable them only the board file.
Signed-off-by: Maxime Coquelin
---
arch/arm/boot/dts/stih407-family.dtsi | 6 --
arch/arm/boot/dts/stihxxx-b2120.dtsi | 8
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/s
The display nodes are common to both STiH407 and STiH410, move them to the
family file.
Signed-off-by: Maxime Coquelin
---
arch/arm/boot/dts/stih407-family.dtsi | 13 +
arch/arm/boot/dts/stih407.dtsi| 13 -
arch/arm/boot/dts/stih410.dtsi| 13 -
A borad might not expose the USB2.0 ports, so disable them by default in SoC
file, and enable them in b2120 board.
Signed-off-by: Maxime Coquelin
---
arch/arm/boot/dts/stih410-b2120.dts | 24
arch/arm/boot/dts/stih410.dtsi | 12
2 files changed, 36 inse
This series cleans the STi407 family DTs, by factorizing common nodes between
STiH407 and STiH410, and also by only enabling PWM and USB nodes at board
level, as they could not be exposed on some boards.
Maxime Coquelin (3):
ARM: dts: stih407: Enable PWM nodes only board level
ARM: dts: stih40
On Wednesday 23 September 2015 08:50:45 David Daney wrote:
> On 09/23/2015 01:01 AM, Arnd Bergmann wrote:
> > On Tuesday 22 September 2015 16:49:15 David Daney wrote:
> >> From: David Daney
> >> diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt
> >> b/Documentation/devicetre
On Wed, Sep 23, 2015 at 08:27:41PM +0100, Arnd Bergmann wrote:
> On Wednesday 23 September 2015 11:21:56 David Daney wrote:
> > >>
> > >> /* Limit the bus-range to fit within reg */
> > >> -bus_max = pci->cfg.bus_range->start +
> > >> - (resource_size(&pci->cfg.res) >> pci->cf
On Tue, Sep 22, 2015 at 09:37:20PM +0200, Sebastian Reichel wrote:
> Hi,
>
> On Fri, Sep 18, 2015 at 04:39:53PM -0500, Andreas Dannenberg wrote:
> > - state->power_good = !gpiod_get_value_cansleep(bq->pg);
> > + if (bq->pg_gpio_disable)
> > + /*
> > +* If we have a chip w
On Wed, Sep 23, 2015 at 07:21:56PM +0100, David Daney wrote:
> On 09/23/2015 11:01 AM, Will Deacon wrote:
> > On Thu, Sep 17, 2015 at 11:02:11PM +0100, David Daney wrote:
> [...]
> >
> >> Properties of the /chosen node:
> >> diff --git a/drivers/pci/host/pci-host-generic.c
> >> b/drivers/pci/hos
On Tue, Sep 15, 2015 at 4:47 PM, wrote:
> From: Dinh Nguyen
>
> Add the base DTS for Altera's SoCFPGA Stratix 10 platform.
>
> Signed-off-by: Dinh Nguyen
> ---
> v3: change #address-cells and #size-cells to <2>
> change the GIC address to 0xfffc1000
> update the GIC virtual CPU reg leng
On Wednesday 23 September 2015 11:21:56 David Daney wrote:
> >>
> >> /* Limit the bus-range to fit within reg */
> >> -bus_max = pci->cfg.bus_range->start +
> >> - (resource_size(&pci->cfg.res) >> pci->cfg.ops.bus_shift) -
> >> 1;
> >> +bus_max = (resource_size(&pci->cfg.
On 23/09/15 19:18, Marc Zyngier wrote:
On Wed, 23 Sep 2015 18:52:59 +0100
Will Deacon wrote:
On Wed, Sep 23, 2015 at 06:08:39PM +0100, David Daney wrote:
On 09/23/2015 10:01 AM, Marc Zyngier wrote:
On Tue, 22 Sep 2015 17:00:06 -0700
David Daney wrote:
From: David Daney
Call of_msi_map_r
On 09/23/2015 01:05 PM, Murali Karicheri wrote:
> On 09/22/2015 12:08 PM, Nishanth Menon wrote:
[...]
>> diff --git
>> a/Documentation/devicetree/bindings/arm/keystone/keystone.txt
>> b/Documentation/devicetree/bindings/arm/keystone/keystone.txt
>> index 59d7a46f85eb..800d2d02e27b 100644
>> --- a/
Hi,
On Wed, Sep 23, 2015 at 01:32:58PM -0500, Andreas Dannenberg wrote:
> On Wed, Sep 23, 2015 at 05:02:28PM +0200, Sebastian Reichel wrote:
> > On Wed, Sep 23, 2015 at 09:11:46AM -0500, Andreas Dannenberg wrote:
> > > Ok. So how should we best go about extending the usage of the
> > > 'input_curr
On 09/23/2015 12:53 PM, Mark Brown wrote:
On Wed, Sep 23, 2015 at 11:07:39AM -0500, Andrew F. Davis wrote:
drivers/gpio/Kconfig | 6 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-tps65912.c | 138
drivers/mfd/Kconfig
From: Marcus Cooper
The A20-SOM-EVB is a reference design of a 2-layer board for the
A20-SOM.
It expands the features of A20-SOM by adding VGA connector, HDMI
connector, audio In/Out, LCD connector, 2 Mpix camera, gigabit
Ethernet, SATA, USB-OTG and 2 USB hosts.
Signed-off-by: Marcus Cooper
---
Hi Sascha,
On 23.09.2015 16:37, Sascha Hauer wrote:
> This adds support for the Mediatek thermal controller found on MT8173
> and likely other SoCs.
> The controller is a bit special. It does not have its own ADC, instead
> it controls the on-SoC AUXADC via AHB bus accesses. For this reason
> we n
On Wed, Sep 23, 2015 at 05:02:28PM +0200, Sebastian Reichel wrote:
> Hi,
>
> On Wed, Sep 23, 2015 at 09:11:46AM -0500, Andreas Dannenberg wrote:
> > Ok. So how should we best go about extending the usage of the
> > 'input_current_limit' sysfs node for this charger? You mentioned
> > writing 'auto'
On 09/23/2015 11:01 AM, Will Deacon wrote:
On Thu, Sep 17, 2015 at 11:02:11PM +0100, David Daney wrote:
[...]
Properties of the /chosen node:
diff --git a/drivers/pci/host/pci-host-generic.c
b/drivers/pci/host/pci-host-generic.c
index 77cf4bd..0a9c453 100644
--- a/drivers/pci/host/pci-host
Nishant,
On 9/22/2015 9:08 AM, Nishanth Menon wrote:
Keystone2 devices are used on more platforms than just Texas
Instruments reference evaluation platforms called EVMs. Providing a
generic compatible "ti,keystone" is not sufficient to differentiate
various SoC definitions possible on various pl
On Wed, 23 Sep 2015 18:52:59 +0100
Will Deacon wrote:
> On Wed, Sep 23, 2015 at 06:08:39PM +0100, David Daney wrote:
> > On 09/23/2015 10:01 AM, Marc Zyngier wrote:
> > > On Tue, 22 Sep 2015 17:00:06 -0700
> > > David Daney wrote:
> > >
> > >> From: David Daney
> > >>
> > >> Call of_msi_map_rid
On 09/22/2015 12:08 PM, Nishanth Menon wrote:
Keystone2 devices are used on more platforms than just Texas
Instruments reference evaluation platforms called EVMs. Providing a
generic compatible "ti,keystone" is not sufficient to differentiate
various SoC definitions possible on various platforms.
On Thu, Sep 17, 2015 at 11:02:11PM +0100, David Daney wrote:
> From: David Daney
>
> There are two problems with the bus_max calculation:
>
> 1) The u8 data type can overflow for large config space windows.
>
> 2) The calculation is incorrect for a bus range that doesn't start at
>zero.
>
On Thu, Sep 17, 2015 at 11:02:09PM +0100, David Daney wrote:
> From: David Daney
>
> If we create multiple buses with pci-host-generic, or there are buses
> created by other drivers, we don't want to call pci_fixup_irqs() which
> operates on all devices, not just the devices on the bus being adde
On Thu, Sep 24, 2015 at 12:05:18AM +0800, Chen-Yu Tsai wrote:
> +static int sunxi_rsb_device_probe(struct device *dev)
> +{
> + const struct sunxi_rsb_driver *drv = to_sunxi_rsb_driver(dev->driver);
> + struct sunxi_rsb_device *rdev = to_sunxi_rsb_device(dev);
> + int ret;
> +
> +
On Wed, Sep 23, 2015 at 11:07:39AM -0500, Andrew F. Davis wrote:
> drivers/gpio/Kconfig | 6 +
> drivers/gpio/Makefile | 1 +
> drivers/gpio/gpio-tps65912.c | 138
> drivers/mfd/Kconfig| 24 ++
> drivers/mfd/Makefi
* Suman Anna [150903 16:01]:
> On 07/23/2015 02:24 AM, Tony Lindgren wrote:
> > OK maybe check the syss/sysc registers involved here for each hardware
> > module here and which driver tinkers with which registers? This will
> > make things a lot easier in the long run for sure.
>
> The OMAP
On Wed, Sep 23, 2015 at 06:08:39PM +0100, David Daney wrote:
> On 09/23/2015 10:01 AM, Marc Zyngier wrote:
> > On Tue, 22 Sep 2015 17:00:06 -0700
> > David Daney wrote:
> >
> >> From: David Daney
> >>
> >> Call of_msi_map_rid() to handle mapping of the requester id.
> >>
> >> Signed-off-by: David
On 09/23/2015 10:01 AM, Marc Zyngier wrote:
On Tue, 22 Sep 2015 17:00:06 -0700
David Daney wrote:
From: David Daney
Call of_msi_map_rid() to handle mapping of the requester id.
Signed-off-by: David Daney
---
drivers/irqchip/irq-gic-v3-its-pci-msi.c | 3 ++-
1 file changed, 2 insertions(
Hi Josh,
Thanks for the review. This is all at the tail end of a long
(>2 years) discussion on this. I hope that the way this has
shaped out still meets the needs of the people who have been
in this discussion the most and have had the strongest feelings
(due to being current users of FPGAs unde
On 09/23/2015 10:07 AM, Rob Herring wrote:
On Tue, Sep 22, 2015 at 7:00 PM, David Daney wrote:
From: David Daney
The device tree property "msi-map" specifies how to create the PCI
requester id used in some MSI controllers. Add a new function
of_msi_map_rid() that finds the msi-map property a
On Tue, Sep 22, 2015 at 7:00 PM, David Daney wrote:
> From: David Daney
>
> The device tree property "msi-map" specifies how to create the PCI
> requester id used in some MSI controllers. Add a new function
> of_msi_map_rid() that finds the msi-map property and applies its
> translation to a giv
Hi,
Am 23.09.2015 um 18:56 schrieb Tony Lindgren :
> * H. Nikolaus Schaller [150923 05:53]:
>
> Missing description?
well, description is “ARM: dts: omap5-uevm: enable iio gpadc for Palmas"
and I didn’t catch that the commit is otherwise empty. Sorry.
> BTW, this I want to queue separately
>
On Tue, 22 Sep 2015 17:00:06 -0700
David Daney wrote:
> From: David Daney
>
> Call of_msi_map_rid() to handle mapping of the requester id.
>
> Signed-off-by: David Daney
> ---
> drivers/irqchip/irq-gic-v3-its-pci-msi.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git
On 09/23/2015 09:52 AM, Marc Zyngier wrote:
On Tue, 22 Sep 2015 17:00:05 -0700
David Daney wrote:
From: David Daney
The device tree property "msi-map" specifies how to create the PCI
requester id used in some MSI controllers. Add a new function
of_msi_map_rid() that finds the msi-map proper
* H. Nikolaus Schaller [150923 05:53]:
Missing description? BTW, this I want to queue separately
as I have patches in works to support omap5 variants with
omap5-board-common.dtsi to avoid duplicating things as
we get omap5 better supported for things like regulators.
Regards,
Tony
> Signed-off
On Tue, 22 Sep 2015 17:00:05 -0700
David Daney wrote:
> From: David Daney
>
> The device tree property "msi-map" specifies how to create the PCI
> requester id used in some MSI controllers. Add a new function
> of_msi_map_rid() that finds the msi-map property and applies its
> translation to a
On Tue, 22 Sep 2015 17:00:04 -0700
David Daney wrote:
> From: Mark Rutland
>
> Currently msi-parent is used by a few bindings to describe the
> relationship between a PCI root complex and a single MSI controller, but
> this property does not have a generic binding document.
>
> Additionally, m
On Wed, 23 Sep 2015, Dan Carpenter wrote:
> On Wed, Sep 23, 2015 at 03:23:54PM +0200, Pavel Machek wrote:
> > > > +int fpga_mgr_firmware_load(struct fpga_manager *mgr, u32 flags,
> > > > + const char *image_name)
> > > > +{
> > > > + struct device *dev = &mgr->dev;
>
On 09/22/2015 06:19 AM, Bjorn Helgaas wrote:
Hi David,
On Fri, Sep 18, 2015 at 06:00:28PM -0700, David Daney wrote:
On 09/18/2015 12:45 PM, Arnd Bergmann wrote:
On Friday 18 September 2015 10:00:32 David Daney wrote:
On 09/18/2015 12:19 AM, Arnd Bergmann wrote:
On Thursday 17 September 2015
Hi everyone,
This is my fourth attempt at adding support for Allwinner's Reduced
Serial Bus (RSB), which is used to communicate with PMICs and other
peripherals on their newer SoCs, such as the A23/A33/A80.
RSB is a simplified two wire interface using push-pull outputs,
supporting multiple slaves
Reduced Serial Bus is a proprietary 2-line push-pull serial bus supporting
multiple slave devices. It was developed by Allwinner, Inc. and used by
Allwinner and X-Powers, Inc. for their line of PMICs and other peripheral
ICs.
Recent Allwinner SoCs, starting with the A23, have an RSB controller. Th
On Thu, Sep 17, 2015 at 9:35 PM, Peter Chen wrote:
> On Wed, Sep 16, 2015 at 08:54:25AM -0500, Rob Herring wrote:
>> On 09/15/2015 08:49 PM, Peter Chen wrote:
>> > Some SoCs needs three clock to let controller work, but others only
>> > need one, add one property to differentiate this.
[...]
>>
The Reduced Serial Bus controller is used to talk to the onboard PMIC.
Signed-off-by: Chen-Yu Tsai
---
Changes since v3:
None
---
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
b/arch/arm/boot/dt
In an effort to cleanup this driver and add Device Tree support
the driver has been rewritten based on new driver styles and
modern kernel driver helpers. This has nearly halved the lines
of code while keeping all previous functionality.
Platform file based initialization has been dropped as there
This patch adds a device node for the Reduced Serial Bus (RSB)
controller and the defacto pinmux setting to the A23/A33 dtsi.
Since there is only one possible pinmux setting for RSB, just
set it in the dtsi.
Signed-off-by: Chen-Yu Tsai
---
Changes since v3:
- Changed #address-cells to 1
---
The old driver does not support DT. Rewrite the driver adding DT support
and use modern kernel features such as regmap and related helpers.
Signed-off-by: Andrew F. Davis
---
drivers/gpio/Kconfig | 6 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-tps6591
The TPS65912 PMIC contains several regulators and a GPIO controller.
Add bindings for the TPS65912 PMIC.
Signed-off-by: Andrew F. Davis
---
.../devicetree/bindings/gpio/gpio-tps65912.txt | 16 +
Documentation/devicetree/bindings/mfd/tps65912.txt | 42 ++
.../bindi
Reduced Serial Bus (RSB) is an Allwinner proprietery interface
used to communicate with PMICs and other peripheral ICs.
RSB is a two-wire push-pull serial bus that supports 1 master
device and up to 15 active slave devices.
Signed-off-by: Chen-Yu Tsai
---
Changes since v3:
- Merged common bu
The old tps65912 driver is being replaced, delete old driver.
Signed-off-by: Andrew F. Davis
---
drivers/gpio/Kconfig | 6 -
drivers/gpio/Makefile | 1 -
drivers/gpio/gpio-tps65912.c | 153 --
drivers/mfd/Kconfig| 26 -
The Reduced Serial Bus controller is used to talk to the onboard PMIC.
Signed-off-by: Chen-Yu Tsai
---
Changes since v3:
None
---
arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
b/arch/arm/b
On 09/23/2015 01:21 AM, Arnd Bergmann wrote:
On Tuesday 22 September 2015 16:49:14 David Daney wrote:
From: David Daney
The pci-host-generic driver keeps a global struct pci_ops which it
then patches with the .map_bus method appropriate for the bus device.
A problem arises when the driver is u
On 09/23/2015 01:01 AM, Arnd Bergmann wrote:
On Tuesday 22 September 2015 16:49:15 David Daney wrote:
From: David Daney
There are two problems with the bus_max calculation:
1) The u8 data type can overflow for large config space windows.
2) The calculation is incorrect for a bus range that d
Hi Vinod,
Thanks for reviewing the patch
> -Original Message-
> From: Vinod Koul [mailto:vinod.k...@intel.com]
> Sent: Monday, September 21, 2015 9:27 PM
> To: Anurag Kumar Vulisha
> Cc: Rob Herring; Pawel Moll; Mark Rutland; Ian Campbell; Kumar Gala; Michal
> Simek; Soren Brinkmann; Dan
On Wed, Sep 23, 2015 at 03:38:20PM +0800, Ming Lei wrote:
> Hi Leif,
>
>
> On Tue, Sep 8, 2015 at 8:43 PM, Leif Lindholm
> wrote:
> > Support for configuring bootconsole and console via the ACPI tables
> > DBG2 (Debug Port Table 2) [1] and SPCR (Serial Port Console Redirection
> > Table) [2], d
On Mon, Sep 21, 2015 at 9:17 AM, Felipe Tonello wrote:
> On Wed, Sep 16, 2015 at 6:40 PM, wrote:
>> From: "Felipe F. Tonello"
>>
>> This fixes a duplicated pin control causing this error:
>>
>> imx6q-pinctrl 20e.iomuxc: pin MX6Q_PAD_GPIO_1 already
>> requested by regulators:regulator@2; can
On Tue, Sep 15, 2015 at 06:01:01PM +0800, Shengjiu Wang wrote:
> As spdif driver will register SPDIF clock to regmap, regmap will do
> clk_prepare in init function, so SPDIF clock is prepared in probe, then its
> root clock (pll clock) is prepared also, which cause the arm can't enter
> low power m
On 09/23/2015 04:01 AM, Martin Sperl wrote:
On 22.09.2015 04:42, Stephen Warren wrote:
On 09/11/2015 05:20 AM, ker...@martin.sperl.org wrote:
From: Martin Sperl
Add the auxiliary uart1 device to the device tree of the bcm2835 SOC.
diff --git a/arch/arm/boot/dts/bcm2835.dtsi
b/arch/arm/boot
On Wed, 23 Sep 2015 17:33:09 +0800
Ley Foon Tan wrote:
> On Wed, Sep 23, 2015 at 2:33 AM, Marc Zyngier wrote:
> > On Mon, 21 Sep 2015 10:13:04 +0800
> > Ley Foon Tan wrote:
> >
> >> This patch adds the Altera PCIe host controller driver.
> >>
> >> Signed-off-by: Ley Foon Tan
> >> ---
> >> dri
Hi,
On Wed, Sep 23, 2015 at 09:11:46AM -0500, Andreas Dannenberg wrote:
> On Wed, Sep 23, 2015 at 02:29:06AM +0200, Sebastian Reichel wrote:
> > On Tue, Sep 22, 2015 at 05:10:45PM -0500, Andreas Dannenberg wrote:
> > > On Tue, Sep 22, 2015 at 09:16:49PM +0200, Sebastian Reichel wrote:
> > > > On F
Le 21/09/2015 20:25, Linus Walleij a écrit :
> On Wed, Sep 16, 2015 at 8:37 AM, Ludovic Desroches
> wrote:
>
>> SAMA5D2 chip family has a new PIO controller.
>>
>> Signed-off-by: Ludovic Desroches
>
> Acked-by: Linus Walleij
>
> Please merge this through Nicolas' AT91 tree.
Added in the at91
Le 21/09/2015 20:50, Linus Walleij a écrit :
> On Wed, Sep 16, 2015 at 8:36 AM, Ludovic Desroches
> wrote:
>
>> The Atmel PIO4 controller has been introduced with SAMA5D2 chip family. This
>> drivers manages both pinmux/pinconf and gpio stuff. It is inspired by
>> Mediatek
>> pinctrl driver.
>>
Hi Lee,
On 22/09/15 21:34, Lee Jones wrote:
On Mon, 21 Sep 2015, Emilio López wrote:
Some EC implementations include a small nvram space used to store
verified boot context data. This boolean property lets us indicate
whether this space is available or not on a specific EC implementation.
Sig
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