On 7 December 2015 at 18:37, Peter Chen wrote:
> Current USB HUB driver lacks of platform interfaces to configure
> external signal on HUB chip, eg, the PHY input clock and gpio reset
> pin for HUB, these kinds of HUBs are usually soldered at the board,
> and they are not hot-plug USB devices.
>
>
On 30 November 2015 at 08:29, Maxime Ripard
wrote:
> Some boards, in order to power devices that have a quite high power
> consumption, wire multiple regulators in parallel.
>
> In such a case, the regulators need to be kept in sync, all of them being
> enabled or disabled in parallel.
>
> This al
This patch adds support for coresight components. More specifically
it has definitions for the A53/57 tracers, the A53/57 cluster funnels,
the main funnel and the ETF configured in circular buffer mode.
Support for other coresight IP blocks have not been addressed yet.
Signed-off-by: Mathieu
On 8 May 2015 at 08:17, Ivan T. Ivanov wrote:
>
> On Fri, 2015-05-08 at 08:13 -0600, Mathieu Poirier wrote:
>> On 8 May 2015 at 07:47, Ivan T. Ivanov iva...@linaro.org> wrote:
>> > On Fri, 2015-05-08 at 07:38 -0600, Mathieu Poirier wrote:
>> > > On 7 M
On 30 April 2015 at 01:21, Ivan T. Ivanov wrote:
>
> On Wed, 2015-04-29 at 10:28 -0600, Mathieu Poirier wrote:
>> On 29 April 2015 at 06:19, Ivan T. Ivanov iva...@linaro.org> wrote:
>
>
>
>> > - "arm,coresight-etm4x", "arm,pr
On 30 April 2015 at 03:24, Ivan T. Ivanov wrote:
>
> On Wed, 2015-04-29 at 10:49 -0600, Mathieu Poirier wrote:
>> On 29 April 2015 at 06:20, Ivan T. Ivanov iva...@linaro.org> wrote:
>
>
>> > +
>> > + funnel@821000 {
>> > + com
On 23 April 2015 at 03:20, Mark Rutland wrote:
> Hi Matthieu,
>
>> + main_funnel@2004 {
>> + compatible = "arm,coresight-funnel", "arm,primecell";
>> + reg = <0 0x2004 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb
n the SPC sub-system have
not been addressed.
Signed-off-by: Mathieu Poirier
---
arch/arm64/boot/dts/arm/juno.dts | 222 +++
1 file changed, 222 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index 133ee59
Adding compatible string for new coresight ETMv4 tracer.
Signed-off-by: Mathieu Poirier
---
Documentation/devicetree/bindings/arm/coresight.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt
b/Documentation/devicetree/bindings/arm
On 3 April 2015 at 13:51, Olof Johansson wrote:
> On Wed, Mar 25, 2015 at 08:52:11PM +0800, Chunyan Zhang wrote:
>> Support only for ETF, FUNNEL, STM are included currently.
>> Support for ETM, TPIU and the replicator linked to it are not included in
>> this version patch.
>>
>> Signed-off-by: Chu
On 23 March 2015 at 23:48, Chunyan Zhang wrote:
> Support only for ETB, FUNNEL, STM are included currently.
> Support for ETM, TPIU and the replicator linked to it are not included in
> this version patch.
>
> Signed-off-by: Chunyan Zhang
> ---
> arch/arm64/boot/dts/sprd/sc9836.dtsi | 57
>
n for CoreSight components. The driver has been posted
here[1].
[1]. https://lkml.org/lkml/2015/2/25/743
Signed-off-by: Mathieu Poirier
---
.../devicetree/bindings/arm/coresight.txt | 25 ++
1 file changed, 25 insertions(+)
diff --git a/Documentation/devicetree/binding
From: Mathieu Poirier
The System Trace Macrocell (STM) is an IP block falling under the
CoreSight umbrella. It's main purpose it so expose stimulus channels
to any system component for the purpose of information logging.
Bindings for this IP block adds a couple of items to the cu
On 7 January 2015 at 03:54, Lorenzo Pieralisi wrote:
> On Tue, Jan 06, 2015 at 10:01:03PM +, Rob Herring wrote:
>> On Tue, Jan 6, 2015 at 12:36 PM, Mathieu Poirier
>> wrote:
>> > On 6 January 2015 at 10:02, Rob Herring wrote:
>> >> On Tue, Jan 6, 20
On 6 January 2015 at 10:02, Rob Herring wrote:
> On Tue, Jan 6, 2015 at 10:45 AM, wrote:
>> From: Mathieu Poirier
>>
>> Among other things, the serial power controller (SPC) controls power to
>> the A7 and A15 clusters. Theses clusters also happen to contains the
&g
From: Mathieu Poirier
Among other things, the serial power controller (SPC) controls power to
the A7 and A15 clusters. Theses clusters also happen to contains the
coresight tracers used for HW assisted tracing.
By modellling these to power domains in a way that is comprehensible to
the generic
From: Mathieu Poirier
Coresight IP blocks allow for the support of HW assisted tracing
on ARM SoCs. Bindings for the currently available blocks are
presented herein.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
Acked-by: Rob Herring
---
Change for v2:
- Added ack by Rob
ack from Rob
>> Herring.
>
> Ummm...
>
>>
>> Thanks,
>> Mathieu
>>
>> From 69cae46640b8cdc836bf7b86211d5f2adf3d0270 Mon Sep 17 00:00:00 2001
>> From: Mathieu Poirier
>> Date: Thu, 7 Aug 2014 12:34:06 -0600
>> Subject: [PATCH] coresight: bindi
Greg,
Please consider this as a supplement to the coresight patchset. It should have
been sent with the rest of the patches but I missed the original ack from Rob
Herring.
Thanks,
Mathieu
>From 69cae46640b8cdc836bf7b86211d5f2adf3d0270 Mon Sep 17 00:00:00 2001
From: Mathieu Poirier
Date:
ck and see where the problem is is...
>
> Rob
>
>
>>
>> Thanks,
>> Mathieu
>>
>> From 12ec0ef4753125e470a0899fabd94b46b3a93a9d Mon Sep 17 00:00:00 2001
>> From: Mathieu Poirier
>> Date: Thu, 7 Aug 2014 12:34:06 -0600
>> Subject: [PATCH v9] core
Can someone in the bindings' maintainer brigade pick this up? The code has been
added to linux-next:
a06ae86 coresight: add CoreSight core layer framework
Thanks,
Mathieu
>From 12ec0ef4753125e470a0899fabd94b46b3a93a9d Mon Sep 17 00:00:00 2001
From: Mathieu Poirier
Date: Th
On 3 November 2014 18:28, Kevin Hilman wrote:
> Mathieu Poirier writes:
>
>> On 3 November 2014 08:34, Geert Uytterhoeven wrote:
>>> Hi Rafael, Simon, Magnus,
>>>
>>> This patch series enables DT support for PM domains on Renesas R-Mobile
>&g
On 3 November 2014 08:34, Geert Uytterhoeven wrote:
> Add a device node for the System Controller, with subnodes that
> represent the hardware power area hierarchy.
> Hook up all devices to their respective PM domains.
>
> Add a minimal device node for the Coresight-ETM hardware block, and hook
>
On 3 November 2014 08:34, Geert Uytterhoeven wrote:
> Hi Rafael, Simon, Magnus,
>
> This patch series enables DT support for PM domains on Renesas R-Mobile SoCs.
>
> Currently it's limited to R-Mobile A1 (r8a7740), but given the similarity of
> the SYSC System-Controller on the various SH-
From: Mathieu Poirier
Coresight IP blocks allow for the support of HW assisted tracing
on ARM SoCs. Bindings for the currently available blocks are
presented herein.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../devicetree/bindings/arm/coresight.txt | 203
On 20 October 2014 11:20, Will Deacon wrote:
> On Mon, Oct 20, 2014 at 10:16:16AM +0100, Sudeep Holla wrote:
>> On 20/10/14 09:46, Neil Zhang wrote:
>> > Will, I prefer to check always-on field under PMU node to check
>> > whether we need Save/restore them.
>> >
>> But how do you handle it for dif
From: Mathieu Poirier
Coresight IP blocks allow for the support of HW assisted tracing
on ARM SoCs. Bindings for the currently available blocks are
presented herein.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../devicetree/bindings/arm/coresight.txt | 203
From: Mathieu Poirier
Coresight IP blocks allow for the support of HW assisted tracing
on ARM SoCs. Bindings for the currently available blocks are
presented herein.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../devicetree/bindings/arm/coresight.txt | 203
From: Mathieu Poirier
Coresight IP blocks allow for the support of HW assisted tracing
on ARM SoCs. Bindings for the currently available blocks are
presented herein.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../devicetree/bindings/arm/coresight.txt | 203
From: Mathieu Poirier
Coresight IP blocks allow for the support of HW assisted tracing
on ARM SoCs. Bindings for the currently available blocks are
presented herein.
Signed-off-by: Pratik Patel
Signed-off-by: Panchaxari Prasannamurthy
Signed-off-by: Mathieu Poirier
---
.../devicetree
From: Mathieu Poirier
Coresight IP blocks allow for the support of HW assisted tracing
on ARM SoCs. Bindings for the currently available blocks are
presented herein.
Signed-off-by: Pratik Patel
Signed-off-by: Panchaxari Prasannamurthy
Signed-off-by: Mathieu Poirier
---
Changes for V5
From: Pratik Patel
Coresight IP blocks allow for the support of HW assisted tracing
on ARM SoCs. Bindings for the currently available blocks are
presented herein.
Signed-off-by: Pratik Patel
Signed-off-by: Panchaxari Prasannamurthy
Signed-off-by: Mathieu Poirier
---
.../devicetree/bindings
From: Pratik Patel
Coresight IP blocks allow for the support of HW assisted tracing
on ARM SoCs. Bindings for the currently available blocks are
presented herein.
Signed-off-by: Pratik Patel
Signed-off-by: Panchaxari Prasannamurthy
Signed-off-by: Mathieu Poirier
---
.../devicetree/bindings
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