From: Srinivas Kandagatla
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP is common
across all the ST parts for settop box platforms.
ASC is embedded in ST COMMS IP block. It supports Rx & Tx functionality.
It sup
From: Srinivas Kandagatla
This patch adds phy reset callback support for stmmac driver via device
trees. It adds three new properties to gmac device tree bindings to
define the reset signal via gpio.
With this patch users can conveniently pass reset gpio number with pre,
pulse and post delay in
From: Srinivas Kandagatla
Hi Peppe/Dave,
Thankyou for the comments on v1 patches.
This patch series adds support to new gmac versions 3.6.10 and 3.710, these
versions of IP are integrated into ST STiH415/STiH416 SOCs.
This patchset also adds phy reset capablity to stmmac-mdio driver via DT
From: Srinivas Kandagatla
This patch adds dt support to dwmac version 3.610 and 3.710 these
versions are integrated in STiH415 and STiH416 ARM A9 SOCs.
To support these IP version, some of the device tree properties are
extended.
Signed-off-by: Srinivas Kandagatla
---
Documentation/devicetree
From: Srinivas Kandagatla
In some DT use-cases platform data might be already allocated and passed
via AUXDATA. These are the cases where machine level code populates few
callbacks in the platform data.
This patch adds check and reuses platform_data if its valid, before
allocating a new one
On 04/07/13 00:04, David Miller wrote:
> You are going to have to fix up the following build warnings and resubmit:
>
> CC [M] drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.o
> drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c: In function
> ‘stmmac_mdio_reset’:
> drivers/net/ethernet/stmic
From: Srinivas Kandagatla
This patch adds phy reset callback support for stmmac driver via device
trees. It adds three new properties to gmac device tree bindings to
define the reset signal via gpio.
With this patch users can conveniently pass reset gpio number with pre,
pulse and post delay in
From: Srinivas Kandagatla
In some DT use-cases platform data might be already allocated and passed
via AUXDATA. These are the cases where machine level code populates few
callbacks in the platform data.
This patch adds check and reuses platform_data if its valid, before
allocating a new one
From: Srinivas Kandagatla
This patch adds dt support to dwmac version 3.610 and 3.710 these
versions are integrated in STiH415 and STiH416 ARM A9 SOCs.
To support these IP version, some of the device tree properties are
extended.
Signed-off-by: Srinivas Kandagatla
---
Documentation/devicetree
From: Srinivas Kandagatla
Hi Peppe,
Thankyou for the comments on RFC patches.
This patch series adds support to new gmac versions 3.6.10 and 3.710, these
versions of IP are integrated into ST STiH415/STiH416 SOCs.
This patchset also adds phy reset capablity to stmmac-mdio driver via DT
Thanks Peppe for the comments,
On 01/07/13 18:20, Giuseppe CAVALLARO wrote:
> On 7/1/2013 1:43 PM, Srinivas KANDAGATLA wrote:
>> From: Srinivas Kandagatla
>>
>> +
>> +plat->bus_id = of_alias_get_id(np, "ethernet");
>> +if (
From: Srinivas Kandagatla
This patch adds phy reset callback support for stmmac driver via device
trees. It adds three new properties to gmac device tree bindings to
define the reset signal via gpio.
With this patch users can conveniently pass reset gpio number with pre,
pulse and post delay in
From: Srinivas Kandagatla
In some DT use-cases platform data might be already allocated and passed
via AUXDATA. These are the cases where machine level code populates few
callbacks in the platform data.
This patch adds check and reuses platform_data if its valid, before
allocating a new one
From: Srinivas Kandagatla
This patch adds dt support to dwmac version 3.610 and 3.710 these
versions are integrated in STiH415 and STiH416 ARM A9 SOCs.
To support these IP version, some of the device tree properties are
extended.
Signed-off-by: Srinivas Kandagatla
---
Documentation/devicetree
From: Srinivas Kandagatla
Hi Peppe,
This patch series adds support to new gmac versions 3.6.10 and 3.710, these
versions of IP are integrated into ST STiH415/STiH416 SOCs.
This patchset also adds phy reset capablity to stmmac-mdio driver via DT.
Thanks,
srini
Srinivas Kandagatla (3
info->pctl = pinctrl_register(pctl_desc, &pdev->dev, info);
> - if (IS_ERR(info->pctl)) {
> + if (!info->pctl) {
> dev_err(&pdev->dev, "Failed pinctrl registration\n");
> - return PTR_ERR(info->pctl);
> +
On 26/06/13 14:24, Daniel Lezcano wrote:
>> If its not too late can this patch be considered for 3.11 via clocksource
>> tree?
>> > This patch has no build dependencies.
> I took it in my tree but it is too late for a 3.11, sorry.
Thanks Daniel.
>
> Thanks
> -- Daniel
__
timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy
Signed-off-by: Srinivas Kandagatla
CC: Arnd Bergmann
CC: Rob Herring
CC: Linus Walleij
CC: Will Deacon
CC: Thomas Gleixner
---
Thankyou for reveiwing the v6 patch.
This patch is split out of the orignal 10 patches submitted for
Thanks for your comments,
On 25/06/13 22:14, Sören Brinkmann wrote:
>> +Example:
>> > +
>> > + timer@2c000600 {
>> > + compatible = "arm,cortex-a9-global-timer";
>> > + reg = <0x2c000600 0x20>;
>> > + interrupts = <1 13 0xf01>;
>> > + };
> Isn't a 'clocks' entry missing
Thanks for the comments.
On 25/06/13 14:17, Thomas Gleixner wrote:
> On Tue, 25 Jun 2013, Srinivas KANDAGATLA wrote:
>> If its not too late can this patch be considered for 3.11 via clocksource
>> tree?
>
> Sure. No worry, though I noticed a little detail when reading th
On 25/06/13 11:58, Linus Walleij wrote:
> On Mon, Jun 24, 2013 at 4:12 PM, Mark Brown wrote:
>> On Mon, Jun 24, 2013 at 01:57:56PM +0200, Linus Walleij wrote:
>>
>>> This seems fairly complete, but I cannot have such a basic dependency onto
>>> the regmap tree this late in the merge window, i.e. I
On 25/06/13 00:38, Greg Kroah-Hartman wrote:
> On Mon, Jun 24, 2013 at 08:21:43AM +0100, Srinivas KANDAGATLA wrote:
>> From: Srinivas Kandagatla
>>
>> This patch adds support to ASC (asynchronous serial controller)
>> driver, which is basically a standard seria
On 24/06/13 15:12, Mark Brown wrote:
> On Mon, Jun 24, 2013 at 01:57:56PM +0200, Linus Walleij wrote:
>
>> This seems fairly complete, but I cannot have such a basic dependency onto
>> the regmap tree this late in the merge window, i.e. I'm not ready to pull
>> all of regmap into the pinctrl tree.
timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Thomas Gleixner
CC: Arnd Bergmann
CC: Rob Herring
CC: Linus Walleij
CC: Will Deacon
---
Thankyou for reveiwing the v5 patch.
This patch is split out of the orignal 10 patches submitted
Thankyou for the comments,
On 24/06/13 23:00, Stephen Boyd wrote:
> On 06/24/13 14:08, Srinivas KANDAGATLA wrote:
>> On 24/06/13 21:06, Stephen Boyd wrote:
>>> On 06/24/13 08:53, Srinivas KANDAGATLA wrote:
>
>
> I think the problem is your clockevent has no rating. Ple
Thankyou for the comments.
On 24/06/13 23:08, Stephen Boyd wrote:
> On 06/24/13 08:53, Srinivas KANDAGATLA wrote:
>> +#include
>
> Why do you need this include?
>
>> +#include
>
> And this one?
Removed them.
>
>> +static u64 gt_counter_read(void)
>&
On 24/06/13 21:01, Thomas Gleixner wrote:
> On Mon, 24 Jun 2013, Srinivas KANDAGATLA wrote:
>
>> From: Stuart Menefy
>>
>> This is a simple driver for the global timer module found in the Cortex
>> A9-MP cores from revision r1p0 onwards. This should be able to p
On 24/06/13 21:06, Stephen Boyd wrote:
> On 06/24/13 08:53, Srinivas KANDAGATLA wrote:
>> +
>> +static void gt_clockevents_stop(struct clock_event_device *clk)
>> +{
>> +gt_clockevent_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
>> +disable_percpu_irq(clk
timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy
Signed-off-by: Srinivas Kandagatla
CC: Arnd Bergmann
CC: Rob Herring
CC: Linus Walleij
CC: Will Deacon
CC: Thomas Gleixner
---
Thankyou for reveiwing the v4 patch.
This patch is split out of the orignal 10 patches submitted for
On 24/06/13 12:57, Linus Walleij wrote:
> On Fri, Jun 21, 2013 at 3:41 PM, Srinivas KANDAGATLA
> wrote:
>
>> Hi Linus W,
>> If its not too late can this patch be considered for 3.11 via pinctrl tree?
>> There is a build dependecy with regmap_field apis pulled
Thankyou for the comments.
On 21/06/13 16:56, Thomas Gleixner wrote:
> On Fri, 21 Jun 2013, Srinivas KANDAGATLA wrote:
>> +static void gt_clockevent_set_mode(enum clock_event_mode mode,
>> + struct clock_event_device *clk)
>> +{
>&
From: Srinivas Kandagatla
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP is common
across all the ST parts for settop box platforms.
ASC is embedded in ST COMMS IP block. It supports Rx & Tx functionality.
It sup
From: Srinivas Kandagatla
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP is common
across all the ST parts for settop box platforms.
ASC is embedded in ST COMMS IP block. It supports Rx & Tx functionality.
It sup
orts Rx & Tx functionality.
>> It support all industry standard baud rates.
>>
>> Signed-off-by: Srinivas Kandagatla
>> CC: Stephen Gallimore
>> CC: Stuart Menefy
>> CC: Arnd Bergmann
>> CC: Greg Kroah-Hartman
>
>>From my point of view the se
p;id=67252287871113deba96adf7e4df1752f3f08688
Thanks,
srini
On 20/06/13 15:05, Srinivas KANDAGATLA wrote:
> This patch add pinctrl support to ST SoCs.
>
> About hardware:
> ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
> pin configurations.
>
> Each multi-function pin is cont
timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy
Signed-off-by: Srinivas Kandagatla
CC: Arnd Bergmann
CC: Rob Herring
CC: Linus Walleij
CC: Will Deacon
CC: Thomas Gleixner
---
This patch is split out of the orignal 10 patches submitted for Sti SOC
support to arm-kernel mailing
On 20/06/13 20:01, Arnd Bergmann wrote:
> On Thursday 20 June 2013, Srinivas KANDAGATLA wrote:
>> This patch adds support to ASC (asynchronous serial controller)
>> driver, which is basically a standard serial driver. This IP is common
>> across all the ST parts for settop box
On 20/06/13 20:02, Arnd Bergmann wrote:
> On Thursday 20 June 2013, Srinivas KANDAGATLA wrote:
>> +static u64 gt_counter_read(void)
>> +{
>> + u64 counter;
>> + u32 lower;
>> + u32 upper, old_upper;
>> +
>> + upper = __ra
On 20/06/13 19:55, Arnd Bergmann wrote:
> On Thursday 20 June 2013, Srinivas KANDAGATLA wrote:
>> --- a/arch/arm/mach-sti/board-dt.c
>> +++ b/arch/arm/mach-sti/board-dt.c
>> @@ -11,6 +11,7 @@
>> #include
>> #include
>> #include
>> +#in
This patch adds low level debug uart support to sti based SOCs.
Signed-off-by: Srinivas Kandagatla
CC: Arnd Bergmann
---
arch/arm/Kconfig.debug | 38 +++
arch/arm/include/debug/sti.S | 61 ++
arch/arm/mach-sti
B2000 board is reference board for STIH415/416 SOCs, it has
2 x UART, 4x USB, 2 x Ethernet, 1 x SATA, 1 x PCIe, and 1GB RAM.
This patch add initial support to b2000 with STiH415/416 with UART2 as
console and a heard beat LED.
Signed-off-by: Srinivas Kandagatla
CC: Stephen Gallimore
CC: Arnd
mode 100644
index 000..442b019
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2020.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under
new SOC addition to
multi_v7_defconfig.
I wanted this to be in a seperate patch, as these options are not
related any of the new SOC support.
Already some discussion at:https://patchwork.kernel.org/patch/2696481
Signed-off-by: Srinivas Kandagatla
---
arch/arm/configs/multi_v7_defconfig | 29
This patch adds stih415 and stih416 support to multi_v7_defconfig.
CONFIG_ARM_ERRATA_754322 is removed as it is selected by the sti
mach level kconfig.
Signed-off-by: Srinivas Kandagatla
---
arch/arm/configs/multi_v7_defconfig |4 +++-
1 files changed, 3 insertions(+), 1 deletions
The STiH416 is advanced HD AVC processor with 3D graphics acceleration
and 1.2-GHz ARM Cortex-A9 SMP CPU.
Signed-off-by: Srinivas Kandagatla
CC: Stephen Gallimore
CC: Stuart Menefy
CC: Arnd Bergmann
CC: Linus Walleij
---
Documentation/arm/sti/stih416-overview.txt | 12 +
arch/arm/boot
signal.
About driver:
This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
pinconf, pinmux, gpio subsystems. All the pinctrl related config
information can only come from device trees.
Signed-off-by: Srinivas Kandagatla
CC: Stephen Gallimore
CC: Stuart Menefy
CC: Arnd Bergmann
baud rates.
Signed-off-by: Srinivas Kandagatla
CC: Stephen Gallimore
CC: Stuart Menefy
CC: Arnd Bergmann
CC: Greg Kroah-Hartman
---
.../devicetree/bindings/tty/serial/st-asc.txt | 18 +
drivers/tty/serial/Kconfig | 16 +
drivers/tty/serial/Make
The STiH415 is the next generation of HD, AVC set-top box processors for
satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9
1.0 GHz, dual-core CPU.
Signed-off-by: Srinivas Kandagatla
CC: Stephen Gallimore
CC: Stuart Menefy
CC: Arnd Bergmann
CC: Linus Walleij
timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy
Signed-off-by: Srinivas Kandagatla
CC: Arnd Bergmann
CC: Rob Herring
CC: Linus Walleij
CC: Will Deacon
CC: Thomas Gleixner
---
.../devicetree/bindings/arm/global_timer.txt | 21 ++
drivers/clocksource/Kconfig
From: Srinivas Kandagatla
Thankyou all for reviewing the v2 patches.
Here is patch-set incorporating all the review comments from v2.
This patch-set adds basic support for STMicroelectronics STi SOCs
which includes STiH415 and STiH416 with B2000 and B2020 board support.
STiH415 and STiH416
Thankyou very much for the comments.
On 16/06/13 13:17, Linus Walleij wrote:
> On Mon, Jun 10, 2013 at 11:22 AM, Srinivas KANDAGATLA
> wrote:
>
>> About driver:
>> This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
>> pinconf, pinmux, gpio subsyste
On 10/06/13 17:38, Srinivas Kandagatla wrote:
>> +++ b/arch/arm/boot/dts/sti-pincfg.h
>> >> @@ -0,0 +1,94 @@
>> >> +#ifndef _STI_PINCFG_H_
>> >> +#define _STI_PINCFG_H_
>> >> +
>> >> +/* Alternate functions */
>&
On 10/06/13 14:52, Arnd Bergmann wrote:
> On Monday 10 June 2013 10:27:05 Srinivas KANDAGATLA wrote:
>
>> > + soc {
>> > + pin-controller-sbc {
>> > + #address-cells = <1>;
>> > + #size-cells = &l
On 13/06/13 12:56, Russell King - ARM Linux wrote:
> On Tue, Jun 11, 2013 at 07:50:31AM +0100, Srinivas KANDAGATLA wrote:
>> You are right, It does not make sense to use BIT() macro for field which
>> has more than 1 bit. I think using mix of both BIT() and the old style
>> wi
On 10/06/13 14:15, Mark Rutland wrote:
> CONFIG_EXPERIMENTAL's gone as of 3d374d09f1: "final removal of
> CONFIG_EXPERIMENTAL", so that's fine to go. CONFIG_GPIO_PL061 and
> CONFIG_MMC_WMT get selected elsewhere, so that's fine.
>
Am planning to send a patch to clean this up, so that any new plat
On 11/06/13 21:13, Linus Walleij wrote:
> On Tue, Jun 11, 2013 at 4:05 PM, Srinivas KANDAGATLA
> wrote:
>
>> Doing this is not adding any value to the driver, because
>> 1. Currently the driver only support DT boot paths, in my previous RFC
>> patches, Arnd suggested
On 10/06/13 14:41, Srinivas Kandagatla wrote:
> On 10/06/13 14:13, Linus Walleij wrote:
>> On Mon, Jun 10, 2013 at 11:21 AM, Srinivas KANDAGATLA
>> Isn't it better to pass a struct device_node *np around and have that as
>> NULL in the non-DT boot path?
> I will try it
On 11/06/13 11:48, Mark Brown wrote:
> On Mon, Jun 10, 2013 at 10:21:58AM +0100, Srinivas KANDAGATLA wrote:
>> It is common to access regmap registers at bit level, using
>> regmap_update_bits or regmap_read functions, however the end user has to
>> take care of a mask or s
On 10/06/13 15:02, Arnd Bergmann wrote:
> There are multiple ways of doing that, e.g. you could export a function
> from syscon.c that you call to register the device node and then import
> the regmap from syscon into your high-level driver again.
>
Hi Arnd/Linus,
Thankyou for your comments,
I d
On 11/06/13 00:19, Russell King - ARM Linux wrote:
> On Mon, Jun 10, 2013 at 12:46:59PM +0100, Srinivas KANDAGATLA wrote:
>>> > > + aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
>>> > > + (0
On 10/06/13 13:43, Linus Walleij wrote:
> On Mon, Jun 10, 2013 at 11:26 AM, Srinivas KANDAGATLA
> wrote:
>
>> The STiH415 is the next generation of HD, AVC set-top box processors for
>> satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9
>
Thankyou for your comments.
On 10/06/13 14:52, Arnd Bergmann wrote:
> On Monday 10 June 2013 10:27:05 Srinivas KANDAGATLA wrote:
>
>> +soc {
>> +pin-controller-sbc {
>> +#address-cells = <1>;
>> +
Thanks for the comments.
On 10/06/13 15:02, Arnd Bergmann wrote:
> On Monday 10 June 2013 14:52:38 Srinivas KANDAGATLA wrote:
>> On 10/06/13 14:16, Linus Walleij wrote:
>>> On Mon, Jun 10, 2013 at 11:22 AM, Srinivas KANDAGATLA
>>> wrote:
>>>
>>>> Th
On 10/06/13 14:16, Linus Walleij wrote:
> On Mon, Jun 10, 2013 at 11:22 AM, Srinivas KANDAGATLA
> wrote:
>
>> This mfd driver provides higher level inialization routines for various
>> IPs like Ethernet, USB, PCIE, SATA and so on. Also it provides way to
>> get to sy
On 10/06/13 14:13, Linus Walleij wrote:
> On Mon, Jun 10, 2013 at 11:21 AM, Srinivas KANDAGATLA
> wrote:
>>
>> Signed-off-by: Stuart Menefy
>> Signed-off-by: Srinivas Kandagatla
>> CC: Arnd Bergmann
>> CC: Rob Herring
>> CC: Linus Walleij
Thankyou for your comment and suggestion,
I will fix the POSIX compliant issue.
On 10/06/13 10:35, Russell King - ARM Linux wrote:
> On Mon, Jun 10, 2013 at 10:21:00AM +0100, Srinivas KANDAGATLA wrote:
>> This patch adds support to ASC (asynchronous serial controller)
>> d
On 10/06/13 12:15, Michal Simek wrote:
Thankyou for your comments,
> Hi,
>
> hmm - that's a nice bug that thunderbird is not able to send this email. :-(
> Let's comment it again via gmail.
> diff --git a/arch/arm/boot/dts/stih415.dtsi
> b/arch/arm/boot/dts/stih415.dtsi
> new file mod
Thanks for testing...
On 10/06/13 11:40, Mark Rutland wrote:
> On Mon, Jun 10, 2013 at 10:27:57AM +0100, Srinivas KANDAGATLA wrote:
>> > This patch adds stih415 and stih416 support to multi_v7_defconfig.
> This seems to drop a few options also:
>
> CONFIG_ARM_ARCH_TIMER
S
The STiH416 is advanced HD AVC processor with 3D graphics acceleration
and 1.2-GHz ARM Cortex-A9 SMP CPU.
Signed-off-by: Srinivas Kandagatla
CC: Stephen Gallimore
CC: Stuart Menefy
CC: Arnd Bergmann
CC: Linus Walleij
---
Documentation/arm/sti/stih416-overview.txt | 12 +
arch/arm/boot
B2000 board is reference board for STIH415/416 SOCs, it has
2 x UART, 4x USB, 2 x Ethernet, 1 x SATA, 1 x PCIe, and 1GB RAM.
This patch add initial support to b2000 with STiH415/416 with UART2 as
console and a heard beat LED.
Signed-off-by: Srinivas Kandagatla
CC: Stephen Gallimore
CC: Arnd
This patch adds stih415 and stih416 support to multi_v7_defconfig.
Signed-off-by: Srinivas Kandagatla
CC: Arnd Bergmann
---
arch/arm/configs/multi_v7_defconfig | 32 +++-
1 files changed, 15 insertions(+), 17 deletions(-)
diff --git a/arch/arm/configs
mode 100644
index 000..442b019
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2020.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under
This patch adds low level debug uart support to sti based SOCs.
Signed-off-by: Srinivas Kandagatla
CC: Arnd Bergmann
---
arch/arm/Kconfig.debug | 38 +++
arch/arm/include/debug/sti.S | 61 ++
arch/arm/mach-sti
based on regmaps,
like some clocks or pinctrls which can work on the regmap_fields
directly without having to worry about bit positions.
Signed-off-by: Srinivas Kandagatla
CC: Mark Brown
CC: Arnd Bergmann
CC: Alexander Shiyan
CC: Lars-Peter Clausen
---
drivers/base/regmap/internal.h |8
signal.
About driver:
This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
pinconf, pinmux, gpio subsystems. All the pinctrl related config
information can only come from device trees.
Signed-off-by: Srinivas Kandagatla
CC: Stephen Gallimore
CC: Stuart Menefy
CC: Arnd Bergmann
timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy
Signed-off-by: Srinivas Kandagatla
CC: Arnd Bergmann
CC: Rob Herring
CC: Linus Walleij
CC: Will Deacon
CC: Thomas Gleixner
---
.../devicetree/bindings/arm/global_timer.txt | 21 ++
drivers/clocksource/Kconfig
ch is usefull for
drivers like pinctrl.
This patch adds support to ST System Configuration registers, which can
be configured by the drivers.
Signed-off-by: Srinivas Kandagatla
CC: Stuart Menefy
CC: Stephen Gallimore
CC: Linus Walleij
CC: Mark Brown
---
.../devicetree/bindings/mfd/sti-sys
From: Srinivas Kandagatla
Here is new patch-set incorporating all the review comments.
This patch-set adds basic support for STMicroelectronics STi SOCs
which includes STiH415 and STiH416 with B2000 and B2020 board support.
STiH415 and STiH416 are dual-core ARM Cortex-A9 CPU, designed for
baud rates.
Signed-off-by: Srinivas Kandagatla
CC: Stephen Gallimore
CC: Stuart Menefy
CC: Arnd Bergmann
CC: Greg Kroah-Hartman
---
.../devicetree/bindings/tty/serial/st-asc.txt | 18 +
drivers/tty/serial/Kconfig | 16 +
drivers/tty/serial/Make
On 23/05/13 22:44, Arnd Bergmann wrote:
Thankyou Arnd for extending this discussion.
> On Monday 20 May 2013, Srinivas KANDAGATLA wrote:
>> On 17/05/13 15:36, Arnd Bergmann wrote:
>>
>> On the other hand using device trees to describe the HW
>> configuration(sysconfs)
Hi Arnd,
Thankyou for the comments.
On 17/05/13 15:36, Arnd Bergmann wrote:
> On Thursday 09 May 2013, Srinivas KANDAGATLA wrote:
>> On 08/05/13 20:48, Arnd Bergmann wrote:
>> I agree, my initial approach was having a dedicated driver specific to
>> ST syscon, however sysc
On 14/05/13 10:23, Linus Walleij wrote:
> On Tue, May 14, 2013 at 10:46 AM, Srinivas KANDAGATLA
> wrote:
>> On 13/05/13 20:05, Linus Walleij wrote:
>
>>> Why are you enabling the timer in unused and shutdown mode?
>>>
>>> This doesn't make sense.
&g
Thankyou for the comments.
On 13/05/13 20:05, Linus Walleij wrote:
> On Wed, May 8, 2013 at 4:11 PM, Srinivas KANDAGATLA
> wrote:
>
> Thomas Gleixner and John Stultz should always be included on timer code
> review.
>
> This is one reason I really like to move the clock
fic to ST.
This is how we did it initially in the out-of-tree kernel.
http://git.stlinux.com/?p=stm/linux-stm.git;a=blob;f=drivers/stm/sysconf.c
Any suggestions?
thanks,
srini
On 09/05/13 10:51, Mark Brown wrote:
> On Wed, May 08, 2013 at 06:42:04PM +0100, Srinivas KANDAGATLA wrote
On 09/05/13 15:51, Arnd Bergmann wrote:
> It won't.
>
>> > Looking at the code in clocksource_of_init it just goes through the
>> > of_device_id table, which is not used in case of non-DT.
> All new platforms are DT-only, and none of the old platforms use this
> driver, so it does not matter.
>
I
On 09/05/13 15:40, Mark Brown wrote:
> So what exactly is the driver doing then? If the register maps look
> nothing like each other then what's the common functionality the driver
> is providing?
What I meant here is that, sysconf registers are reassigned per SOC, so
the sysconf register definiti
On 08/05/13 15:38, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
>> From: Stuart Menefy
>>
>> This is a simple driver for the global timer module found in the Cortex
>> A9-MP cores from revision r1p0 onwards. This should be able to perf
On 09/05/13 14:26, Mark Brown wrote:
> On Thu, May 09, 2013 at 12:58:01PM +0100, Srinivas KANDAGATLA wrote:
>
>> Currently, we have two bits of information which come from device trees.
>> 1> The syscon bank/group definition itself.
>> 2> syscon register offse
On 09/05/13 10:51, Mark Brown wrote:
> On Wed, May 08, 2013 at 06:42:04PM +0100, Srinivas KANDAGATLA wrote:
>
> Fix your mailer to word wrap within paragraphs.
>
Sorry about that.
>> Ultimately the syscon_write use the regmap_update_bits, however we
>> really want is
Hi Arnd,
Thankyou for extending the discussion.
On 08/05/13 20:48, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
>> the pinctrl driver calls syconf_claim(np, "st,alt-control) to get a
>> field and then do a read/write on the field.
>>
>&g
On 08/05/13 15:39, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> +
>> >
>> > Please remove all forward declarations, by reordering the functions in
>> > the way they are called.
>> >
> and drop the dummy functions
We can not remove the dummy functions, as the serial-core does not check
it before us
Thankyou for the comments.
On 08/05/13 15:34, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
>> From: Srinivas Kandagatla
>> +*st-asc(Serial Port)
>> +
>> +Required properties:
>> +- compatible : Should be "st,asc".
> A
Thankyou for the comments.
On 08/05/13 16:01, Mark Brown wrote:
> On Wed, May 08, 2013 at 04:50:22PM +0200, Arnd Bergmann wrote:
>
>>> In many cases a single syconf register contains bits related to multiple
>>> devices, and therefore it need to be shared across multiple drivers at
>>> bit level. T
Thankyou for your comments.
On 08/05/13 15:50, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
>> From: Srinivas Kandagatla
>>
>> This patch introduces syscon_claim, syscon_read, syscon_write,
>> syscon_release APIs to help drivers to use sy
On 08/05/13 17:20, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
>> diff --git a/arch/arm/mach-stih41x/board-dt.c
>> b/arch/arm/mach-stih41x/board-dt.c
>> index 8005f71..1f23aca 100644
>> --- a/arch/arm/mach-stih41x/board-dt.c
>>
Thankyou for the comments.
On 08/05/13 17:18, Arnd Bergmann wrote:
> On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
>> From: Srinivas Kandagatla
>>
>> The STiH415 is the next generation of HD, AVC set-top box processors for
>> satellite, cable, terrestrial and I
Thankyou for the comments.
On 08/05/13 16:06, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 15:11 Wed 08 May , Srinivas KANDAGATLA wrote:
>> From: Srinivas Kandagatla
>>
>> This patch add pinctrl support to ST SoCs.
>>
>> About hardware:
>> ST Set-Top-B
From: Srinivas Kandagatla
This patch introduces syscon_claim, syscon_read, syscon_write,
syscon_release APIs to help drivers to use syscon registers in much more
flexible way.
With this patch, a driver can claim few/all bits in the syscon registers
and do read/write and then release them when
From: Srinivas Kandagatla
B2020 ADI board is reference board for STIH415/416 SOCs, it has 2 x
UART, 4x USB, 1 x Ethernet, 1 x SATA, 1 x PCIe, and 2GB RAM with
standard set-top box IPs.
This patch adds initial support to B2020 with STiH415/416 with SBC_UART1
as console and a heard beat LED
From: Srinivas Kandagatla
This patch add pinctrl support to ST SoCs.
About hardware:
ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
pin configurations.
Each multi-function pin is controlled, driven and routed through the PIO
multiplexing block. Each pin supports GPIO
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