Hi,
On Mon, Jan 13, 2014 at 02:15:01PM +0100, Zoltan HERPAI wrote:
> From b2cd1681fe988584028d280ca79249f4ebcb271c Mon Sep 17 00:00:00 2001
> From: Zoltan HERPAI
> Date: Mon, 13 Jan 2014 14:00:12 +0100
> Subject: [PATCH v2] ARM: sun4i: dt: Add basic board support for LinkSprite
> pcDuino
>
> Th
Quoting Haojian Zhuang (2014-01-14 21:59:40)
>
> On 01/15/2014 11:53 AM, Mike Turquette wrote:
> > Quoting zhangfei (2014-01-14 17:40:25)
> >> Dear Mike
> >>
> >> On 01/15/2014 04:17 AM, Mike Turquette wrote:
> >>> Quoting Zhangfei Gao (2014-01-13 01:14:28)
> Suggest by Arnd: abstract mmc tun
On Mon, Jan 13, 2014 at 02:15:01PM +0100, Zoltan HERPAI wrote:
> From b2cd1681fe988584028d280ca79249f4ebcb271c Mon Sep 17 00:00:00 2001
> From: Zoltan HERPAI
> Date: Mon, 13 Jan 2014 14:00:12 +0100
> Subject: [PATCH v2] ARM: sun4i: dt: Add basic board support for LinkSprite
> pcDuino
>
> This pa
Hi Simon,
On Wed, Jan 15, 2014 at 12:49 AM, Simon Horman wrote:
>> >> > [6/9][V3] ARM: shmobile: r7s72100 dtsi: Add RSPI nodes
>> >> > [7/9][V3] ARM: shmobile: genmai reference: Add RSPI nodes
>> >> > [8/9] ARM: shmobile: r8a7791 dtsi: Add QSPI node
>> >> > [9/9] ARM: shmobile: ko
On 01/15/2014 04:29 PM, Mike Turquette wrote:
Quoting Haojian Zhuang (2014-01-14 21:59:40)
On 01/15/2014 11:53 AM, Mike Turquette wrote:
Quoting zhangfei (2014-01-14 17:40:25)
Dear Mike
On 01/15/2014 04:17 AM, Mike Turquette wrote:
Quoting Zhangfei Gao (2014-01-13 01:14:28)
Suggest by Arnd
On Tue, Jan 14, 2014 at 8:00 PM, Sherman Yin wrote:
> Great! Is there anything else you would like to see changed before this
> patchset can be accepted?
I'd like some sign of life from the DT binding maintainers.
Yours,
Linus Walleij
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On Wednesday 15 January 2014, Tanmay Inamdar wrote:
> This patch adds the bindings for X-Gene PCIe driver. The driver resides
> under 'drivers/pci/host/pci-xgene.c' file.
>
> Signed-off-by: Tanmay Inamdar
> ---
> .../devicetree/bindings/pci/xgene-pcie.txt | 45
>
>
On Tue, Jan 14, 2014 at 3:52 PM, wrote:
> From: Srinivas Kandagatla
>
> Probe function had commas instead of semi-colons on some of the lines.
> This patch just fixes those lines. No functional chagnes done in this
> patch.
>
> Signed-off-by: Srinivas Kandagatla
Patch applied!
Yours,
Linus W
Hello,
On 01/14/2014 08:29 PM, Krzysztof Kozlowski wrote:
On 01/09/2014 05:49 PM, Vladimir Barinov wrote:
Hello.
This adds the folowing:
- Maxim ModelGauge ICs gauge driver for MAX17040/41/43/44/48/49/58/59
chips
- Document DT bindings
- Remove superseded Maxim MAX17040 gauge driver
Vladimi
Hello, Krzysztof,
Thank you for the review.
On 01/14/2014 08:31 PM, Krzysztof Kozlowski wrote:
On 01/09/2014 05:49 PM, Vladimir Barinov wrote:
Add Maxim ModelGauge ICs gauge driver for
MAX17040/41/43/44/48/49/58/59 chips
Signed-off-by: Vladimir Barinov
---
drivers/power/Kconfig
On Tue, Jan 14, 2014 at 09:30:32PM +, Stephen Boyd wrote:
> The Krait CPU/L1 error reporting device is made up a per-CPU
> interrupt. While we're here, document the next-level-cache
> property that's used by the Krait EDAC driver.
>
> Cc: Lorenzo Pieralisi
> Cc: Mark Rutland
> Cc: Kumar Gala
On 12/31/2013 03:16 PM, Mark Brown wrote:
On Fri, Dec 20, 2013 at 12:38:27PM +0200, Jyri Sarha wrote:
+static int evm_startup(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_card *soc_card = rtd->codec->card;
+
On Wed, Jan 15, 2014 at 07:11:48AM +, Loc Ho wrote:
> Signed-off-by: Loc Ho
> Signed-off-by: Tuan Phan
> Signed-off-by: Suman Tripathi
> ---
> .../devicetree/bindings/ata/apm-xgene.txt | 68
>
> 1 files changed, 68 insertions(+), 0 deletions(-)
> create mod
On 12/31/2013 03:25 PM, Mark Brown wrote:
On Fri, Dec 20, 2013 at 12:39:38PM +0200, Jyri Sarha wrote:
Add machine driver support for BeagleBone-Black and other boards with
tilcdc support and NXP TDA998X HDMI transmitter connected to McASP
port in I2S mode. The 44100 Hz sample-rate and it's mult
On Wed, Jan 15, 2014 at 07:10:38AM +, Loc Ho wrote:
> Signed-off-by: Loc Ho
> Signed-off-by: Tuan Phan
> Signed-off-by: Suman Tripathi
> ---
> .../devicetree/bindings/phy/apm-xgene-phy.txt | 94
>
> 1 files changed, 94 insertions(+), 0 deletions(-)
> create mod
On 11:25 Tue 14 Jan , Bo Shen wrote:
> Add the option to choose clock output on which pin connect to SSC.
> Default is on TK pin to SSC, add clk_from_rk_pin option, the clock
> is on RK pin to SSC.
>
> Signed-off-by: Bo Shen
> ---
>
> Documentation/devicetree/bindings/sound/atmel-wm8904.txt
On Wed, Jan 15, 2014 at 07:10:39AM +, Loc Ho wrote:
[...]
> + * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
> + * The first PLL clock macro is used for internal reference clock. The second
> + * PLL clock macro is used to generate the clock for the PHY. This driver
>
Hi Mike,
On 1/9/14 9:47 PM, Jaehoon Chung wrote:
> Acked-by: Jaehoon Chung
>
> On 01/10/2014 06:31 AM, dingu...@altera.com wrote:
>> From: Dinh Nguyen
>>
>> The clk-phase property is used to represent the 2 clock phase values that is
>> needed for the SD/MMC driver. Add a prepare function to the
On Wednesday 15 January 2014, Tanmay Inamdar wrote:
> This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
> X-Gene PCIe controller supports maxmum upto 8 lanes and GEN3 speed.
> X-Gene has maximum 5 PCIe ports supported.
>
> Signed-off-by: Tanmay Inamdar
This already looks much be
On Wednesday 15 January 2014, Marc Carino wrote:
> + gen-ctrl {
> + compatible = "brcm,brcmstb-gen-ctrl-v1";
> + reg = <0xf0404304 0x4
> + 0xf0404308 0x4
> + 0xf03e2578 0x4
> + 0xf03e2488 0x10
> +
ICP DAS LP-8x4x contains FPGA chip. The chip functions as an interrupt
source providing 16 additional interrupts among other things. The
interrupt lines are muxed to a GPIO pin of a 2nd level PXA-GPIO
interrupt controller. GPIO pins of the 2nd level controller are in turn
muxed to a CPU interrupt l
On Wed, 2014-01-15 at 08:39 +0100, Linus Walleij wrote:
> On Wed, Jan 8, 2014 at 8:01 PM, Sergei Ianovich wrote:
> Hm I don't know why I was deluded into thinking this had something to
> do with GPIO. I must have been soft in the head. Sorry about all those
> comments ...
It's not your fault for
On Friday 27 December 2013 09:59 PM, Balaji T K wrote:
Balaji T K (3):
ARM: dts: am335x-evm: add SD card hotplug support
ARM: dts: am335x-evmsk: add SD card hotplug support
ARM: dts: am43x-epos-evm: add SD card hotplug support
arch/arm/boot/dts/am335x-evm.dts |9 +
ar
On 01/15/2014 05:50 AM, Mike Turquette wrote:
Quoting Mike Turquette (2014-01-14 19:16:32)
Quoting Felipe Balbi (2014-01-14 18:04:21)
Hi,
On Tue, Jan 14, 2014 at 02:36:13PM -0600, Felipe Balbi wrote:
Felipe, care to run your randconfig magic for this?
This branch builds just fine so far, I
On Tue, Jan 14, 2014 at 2:46 AM, Zhang Rui wrote:
> Fix a problem that, the platform bus supports the OF style modalias
> in .uevent() call, but not in its device 'modalias' sysfs attribute.
>
> cc: devicetree@vger.kernel.org
> Signed-off-by: Zhang Rui
Acked-by: Rob Herring
As there doesn't ap
15.01.2014 13:27, Jyri Sarha kirjoitti:
> On 12/31/2013 03:25 PM, Mark Brown wrote:
>> On Fri, Dec 20, 2013 at 12:39:38PM +0200, Jyri Sarha wrote:
>>> support. The only supported sample format is SNDRV_PCM_FORMAT_S32_LE.
>>> The 8 least significant bits are ignored.
>>
>> Where does this constraint
On Tue, Jan 14, 2014 at 3:52 PM, wrote:
> ST Pincontroller GPIO bank can have one of the two possible types of
> interrupt-wirings.
Interesting :-)
> +Pin controller node:
> +Required properties:
> - compatible : should be "st,--pinctrl"
> like st,stih415-sbc-pinctrl, st,stih415-fro
On Tue, Jan 14, 2014 at 3:52 PM, wrote:
> From: Srinivas Kandagatla
>
> ST pin controller does not have hardware support for detecting edge
> triggered interrupts, It only has level triggering support.
> This patch attempts to fake up edge triggers from hw level trigger
> support in software. W
Thankyou for reviewing the patch.
On 15/01/14 14:27, Linus Walleij wrote:
> On Tue, Jan 14, 2014 at 3:52 PM, wrote:
>
>> From: Srinivas Kandagatla
>>
>> ST pin controller does not have hardware support for detecting edge
>> triggered interrupts, It only has level triggering support.
>> This pa
On Wednesday 15 January 2014 04:28 AM, Hans de Goede wrote:
> The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
> through a single set of registers. Besides this there are also some other
> phy related bits which need poking, which are per phy, but shared between the
> ohci a
Hi,
On 01/14/2014 08:08 PM, Alan Stern wrote:
On Mon, 13 Jan 2014, Hans de Goede wrote:
Add support for ohci-platform instantiation from devicetree, including
optionally getting clks and a phy from devicetree, and enabling / disabling
those on power_on / off.
This should allow using ohci-plat
On Monday 13 January 2014 09:06 PM, Balaji T K wrote:
Add pbias regulator node as a child of system control
module - syscon.
Signed-off-by: Balaji T K
Acked-by: Tony Lindgren
Hi Benoit,
Gentle Ping, Let me know if you have any comments.
---
arch/arm/boot/dts/dra7.dtsi | 17
Hello Jason,
On 09/01/2014 18:35, Jason Gunthorpe wrote:
On Thu, Jan 09, 2014 at 09:36:18AM +0100, boris brezillon wrote:
You might want to check if you can boil down the DT timings from the
huge list to just an ONFI mode number..
Sure, but the sunxi driver needs at least 19 of them...
So do
The head number of a given display controller is fixed in hardware and
required to program outputs appropriately. Relying on the driver probe
order to determine this number will not work, since that could yield a
situation where the second head was probed first and would be assigned
head number 0 i
Fixing DT list address...
On Wed, Jan 15, 2014 at 9:16 AM, Rob Herring wrote:
> On Wed, Jan 15, 2014 at 7:46 AM, Mark Rutland wrote:
>> On Wed, Jan 15, 2014 at 12:40:41PM +, Jean-Christophe PLAGNIOL-VILLARD
>> wrote:
>>> On 12:17 Wed 15 Jan , Mark Rutland wrote:
>>> > On Wed, Jan 15, 20
Hi,
On 01/15/2014 04:00 PM, Kishon Vijay Abraham I wrote:
On Wednesday 15 January 2014 04:28 AM, Hans de Goede wrote:
The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
through a single set of registers. Besides this there are also some other
phy related bits which need po
On Wed, 15 Jan 2014 13:27:21 +0200
Jyri Sarha wrote:
> From driver/gpu/drm/i2c/tda998x_drv.c. The driver configures CTS_N
> register statically to a value that works only with 4 byte samples.
> According to my tests it is possible to support 3 and 2 byte samples too
> by changing the CTS_N re
On 01/15/2014 07:41 AM, Tero Kristo wrote:
> On 01/15/2014 05:50 AM, Mike Turquette wrote:
>> Quoting Mike Turquette (2014-01-14 19:16:32)
>>> Quoting Felipe Balbi (2014-01-14 18:04:21)
Hi,
On Tue, Jan 14, 2014 at 02:36:13PM -0600, Felipe Balbi wrote:
>> Felipe, care to run your
Hi all,
And here is v6 of my ohci and ehci-platform clks, phy and dt support patch-set,
this version addresses the 2 small bugs Alan found.
Other then that there are no changes compared to v5.
Regards,
Hans
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of
Add support for ohci-platform instantiation from devicetree, including
optionally getting clks and a phy from devicetree, and enabling / disabling
those on power_on / off.
This should allow using ohci-platform from devicetree in various cases.
Specifically after this commit it can be used for the
Currently ehci-platform is only used in combination with devicetree when used
with some Via socs. By extending it to (optionally) get clks and a phy from
devicetree, and enabling / disabling those on power_on / off, it can be used
more generically. Specifically after this commit it can be used for
>
> Another, more invasive option would be extend the dts syntax and teach
> dtc to handle property appending. Then the soc dts could stay as it is,
> and the board dts could have something like:
>
> /append-property/ interrupts = <&intc1 6 1>;
> /append-property/ interrupt-names = "b
Mike Turquette writes:
> Quoting Haojian Zhuang (2014-01-14 21:59:40)
>>
>> On 01/15/2014 11:53 AM, Mike Turquette wrote:
>> > Quoting zhangfei (2014-01-14 17:40:25)
>> >> Dear Mike
>> >>
>> >> On 01/15/2014 04:17 AM, Mike Turquette wrote:
>> >>> Quoting Zhangfei Gao (2014-01-13 01:14:28)
>> >>>
This patch adds a new driver for keypad for Cirrus Logic CLPS711X CPUs
and devicetree binding documentation.
Target CPU contain keyboard interface which can scan 8 column lines,
so we can read row GPIOs to read status and determine asserted state.
Signed-off-by: Alexander Shiyan
---
.../devicetr
Thankyou for the detailed comments.
On 15/01/14 14:15, Linus Walleij wrote:
> On Tue, Jan 14, 2014 at 3:52 PM, wrote:
>
>> ST Pincontroller GPIO bank can have one of the two possible types of
>> interrupt-wirings.
>
> Interesting :-)
>
>> +Pin controller node:
>> +Required properties:
>> - c
On 01/15/2014 03:48 PM, Anssi Hannula wrote:
15.01.2014 13:27, Jyri Sarha kirjoitti:
On 12/31/2013 03:25 PM, Mark Brown wrote:
On Fri, Dec 20, 2013 at 12:39:38PM +0200, Jyri Sarha wrote:
support. The only supported sample format is SNDRV_PCM_FORMAT_S32_LE.
The 8 least significant bits are igno
The following devices/functionalities were added:
* Main and secondary UARTs.
* i2c and the pcf8563 device.
* Ethernet.
* NAND.
* The BP1 button.
* The LED.
* Watchdog
* SD.
Cc: Eric Bénard
Cc: Grant Likely
Cc: Rob Herring
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: devicetree@vger.kernel.org
On Wed, 15 Jan 2014, Hans de Goede wrote:
> +static int ohci_platform_power_on(struct platform_device *dev)
> +{
> + struct usb_hcd *hcd = platform_get_drvdata(dev);
> + struct ohci_platform_priv *priv = hcd_to_ohci_priv(hcd);
> + int clk, ret;
> +
> + for (clk = 0; clk < OHCI_MAX_
On Saturday 11 January 2014, Andrew Lunn wrote:
> The id of -1 causes platform_device_add() to set the device name to
> plain "gpio-keys".
>
> When using DT, the device name is created by the function
> of_device_make_bus_id(). It has the following comment:
>
> * This routine will first try usin
Hi Linus,
On Wed, Jan 15, 2014 at 09:40:53AM +, Linus Walleij wrote:
> On Tue, Jan 14, 2014 at 8:00 PM, Sherman Yin wrote:
>
> > Great! Is there anything else you would like to see changed before this
> > patchset can be accepted?
>
> I'd like some sign of life from the DT binding maintain
On Tue, Jan 14, 2014 at 04:13:45PM -0800, Courtney Cavin wrote:
> On Tue, Jan 14, 2014 at 07:41:39PM +0100, Josh Cartwright wrote:
> > Signed-off-by: Josh Cartwright
> > ---
> > .../bindings/spmi/qcom,spmi-pmic-arb.txt | 46
> > ++
> > 1 file changed, 46 insertions(
On 01/13, Bjorn Andersson wrote:
> +/*
> + * QUP driver for Qualcomm MSM platforms
> + *
> + */
This comment seems redundant, we know what file we're looking at.
> +
> +struct qup_i2c_dev {
> + struct device *dev;
> + void __iomem*base;
> + struct pinctrl
On 01/15, Lorenzo Pieralisi wrote:
> On Tue, Jan 14, 2014 at 09:30:32PM +, Stephen Boyd wrote:
> > The Krait CPU/L1 error reporting device is made up a per-CPU
> > interrupt. While we're here, document the next-level-cache
> > property that's used by the Krait EDAC driver.
> >
> > Cc: Lorenzo
On Tue, Jan 14, 2014 at 11:48:50PM +, Marc Carino wrote:
> Add the Broadcom Brahma B15 CPU to the DT CPU binding list.
>
> Signed-off-by: Marc Carino
> Acked-by: Florian Fainelli
> ---
> Documentation/devicetree/bindings/arm/cpus.txt |1 +
> 1 files changed, 1 insertions(+), 0 deletions
On 15/01/2014 16:09, boris brezillon wrote:
Hello Jason,
On 09/01/2014 18:35, Jason Gunthorpe wrote:
On Thu, Jan 09, 2014 at 09:36:18AM +0100, boris brezillon wrote:
You might want to check if you can boil down the DT timings from the
huge list to just an ONFI mode number..
Sure, but the sun
On Tue, Jan 14, 2014 at 11:48:51PM +, Marc Carino wrote:
> Document the bindings that the Broadcom STB platform needs
> for proper bootup.
>
> Signed-off-by: Marc Carino
> Acked-by: Florian Fainelli
> ---
> .../devicetree/bindings/arm/brcm-brcmstb.txt | 43
>
>
* Mike Turquette [140114 19:52]:
> >
> > These 40 patches apply very cleanly on top of clk-next with 2
> > exceptions:
> >
> > 1) I did not apply "[PATCH 30/42] ARM: dts: AM35xx: use DT clock data"
> > because I do not have arch/arm/boot/dts/am3517.dtsi in clk-next (based
> > on 3.13-rc1).
> >
On Wednesday 15 January 2014 17:11:55 Mark Rutland wrote:
> > +
> > +Further, a node with the following compatible string shall be defined:
> > +
> > +- compatible: "brcm,brcmstb-gen-ctrl-v1"
>
> It's probably better to say a brcmstb-gen-ctrl node (described below)
> should be present, or you'
Cc: Eric Bénard
Cc: Grant Likely
Cc: Rob Herring
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: devicetree@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Denis Carikli
---
ChangeLog v8->v9:
- Better Cc list.
ChangeLog v7->v8:
- Ajusted to match the driver changes.
---
.../boot/
On Tue, Jan 14, 2014 at 11:48:52PM +, Marc Carino wrote:
> Document the Broadcom Brahma B15 GIC implementation as compatible
> with the ARM GIC standard.
>
> Signed-off-by: Marc Carino
> Acked-by: Florian Fainelli
> ---
> Documentation/devicetree/bindings/arm/gic.txt |1 +
> 1 files cha
On Tue, Jan 14, 2014 at 11:48:49PM +, Marc Carino wrote:
> Perform any CPU-specific initialization required on the
> Broadcom Brahma-15 core.
>
> Signed-off-by: Marc Carino
> Acked-by: Florian Fainelli
> ---
> arch/arm/mm/proc-v7.S | 11 +++
> 1 files changed, 11 insertions(+), 0
On 14/01/2014 04:25, Bo Shen :
> Add the option to choose clock output on which pin connect to SSC.
> Default is on TK pin to SSC, add clk_from_rk_pin option, the clock
Please do not use "_" in DT properties. It is a common pattern to use
"-" instead.
> is on RK pin to SSC.
>
> Signed-off-by: Bo
Cc: Eric Bénard
Cc: Ian Campbell
Cc: Liam Girdwood
Cc: Mark Brown
Cc: Mark Rutland
Cc: Pawel Moll
Cc: Rob Herring
Cc: alsa-de...@alsa-project.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Denis Carikli
---
ChangeLog v9->v10:
- Better Cc list
- Some non-arm architecture that have CONFIG_
On Tue, Jan 14, 2014 at 8:07 AM, Matthew Garrett wrote:
> On Tue, Jan 07, 2014 at 02:50:35PM -0800, Feng Kan wrote:
>> Enable X-Gene platform driver for the X-Gene platform. Remove the
>> use of the mask attribute from the reboot dts node. Add support
>> for using the ACPI and DTS resource for the
On Tue, Jan 14, 2014 at 11:48:53PM +, Marc Carino wrote:
> Add a sample DTS which will allow bootup of a board populated
> with the BCM7445 chip.
>
> Signed-off-by: Marc Carino
> Acked-by: Florian Fainelli
> ---
> arch/arm/boot/dts/brcmstb-7445.dts | 104
>
> > But i'm also a little bit concerned by the "unique number" and this
> > ending up in /dev/input/by-path/platform-gpio_keys.3-event. Is this
> > path supposed to be stable? This unique number is not stable. An
> > unwitting change to the DT could cause its value to change. Do we need
> > to make
Document the Krait PMU compatible string.
Cc:
Signed-off-by: Stephen Boyd
---
Documentation/devicetree/bindings/arm/pmu.txt | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt
b/Documentation/devicetree/bindings/arm/pmu.txt
2014/1/15 Mark Rutland :
> On Tue, Jan 14, 2014 at 11:48:51PM +, Marc Carino wrote:
>> Document the bindings that the Broadcom STB platform needs
>> for proper bootup.
>>
>> Signed-off-by: Marc Carino
>> Acked-by: Florian Fainelli
>> ---
>> .../devicetree/bindings/arm/brcm-brcmstb.txt
On 16:12 Wed 15 Jan , Mark Rutland wrote:
> >
> > Another, more invasive option would be extend the dts syntax and teach
> > dtc to handle property appending. Then the soc dts could stay as it is,
> > and the board dts could have something like:
> >
> > /append-property/ interrupts = <&in
Hi Arnd,
Thank you for the suggestion - it's exactly what we were looking for!
Regards,
Marc
Sent from my phone
> On Jan 15, 2014, at 5:10 AM, Arnd Bergmann wrote:
>
>> On Wednesday 15 January 2014, Marc Carino wrote:
>> + gen-ctrl {
>> + compatible = "brcm,brcmstb-gen-ctr
On Wednesday 15 January 2014 18:45:19 Andrew Lunn wrote:
> > > But i'm also a little bit concerned by the "unique number" and this
> > > ending up in /dev/input/by-path/platform-gpio_keys.3-event. Is this
> > > path supposed to be stable? This unique number is not stable. An
> > > unwitting change
Hi
On 01/02/2014 02:01 AM, Sebastian Reichel wrote:
> Hi,
>
> On Thu, Jan 02, 2014 at 01:13:42AM +0100, Laurent Pinchart wrote:
>>> + .of_match_table = omap_iommu_of_match,
>>
>> If CONFIG_OF isn't defined (pretty unlikely I agree, but a possibility you
>> seem to be prepared for nonet
Hi Suman,
So back to this...
On 12/24/2013 12:35 AM, Anna, Suman wrote:
> Hi Florian,
>
[...]
>>
>> If omap_iommu_probe() fails, the init will have called bus_set_iommu()
>> anyways. Thus, when a driver request the iommu by calling
>> iommu_domain_alloc(), it will succeed (but iommu_attach_dev
Document the multimedia clock controller found on Qualcomm devices
Cc:
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,mmcc.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,mmcc.txt
diff
Document the global clock controller found on Qualcomm devices.
Cc:
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,gcc.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.txt
diff --g
The first breaks a reset-controller include ordering requirement. It got
an ack so I think we're ok for it to go through the clock tree.
The next patch adds support for setting the rate and the parent at the
same time based on patches from James Hogan's remuxing set_rate series.
After that we add
Hi,
On 01/15/2014 05:30 PM, Alan Stern wrote:
On Wed, 15 Jan 2014, Hans de Goede wrote:
+static int ohci_platform_power_on(struct platform_device *dev)
+{
+ struct usb_hcd *hcd = platform_get_drvdata(dev);
+ struct ohci_platform_priv *priv = hcd_to_ohci_priv(hcd);
+ int clk,
Hi,
On Wed, Dec 25, 2013 at 11:20 AM, Huang Shijie wrote:
> 1.) Why add a new framework for SPI NOR?
> The SPI-NOR controller such as Freescale's Quadspi controller is working
> in a different way from the SPI bus. It should knows the NOR commands to
> find the right LUT sequence. Unfortuna
Hi All,
This version of my ohci and ehci-platform clks, phy and dt support patch-set,
really fixes the 2 small bugs Alan found.
Regards,
Hans
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Add support for ohci-platform instantiation from devicetree, including
optionally getting clks and a phy from devicetree, and enabling / disabling
those on power_on / off.
This should allow using ohci-platform from devicetree in various cases.
Specifically after this commit it can be used for the
Currently ehci-platform is only used in combination with devicetree when used
with some Via socs. By extending it to (optionally) get clks and a phy from
devicetree, and enabling / disabling those on power_on / off, it can be used
more generically. Specifically after this commit it can be used for
* Mike Turquette [140115 11:25]:
> Quoting Tony Lindgren (2014-01-15 09:13:23)
> > * Mike Turquette [140114 19:52]:
> > > >
> > > > These 40 patches apply very cleanly on top of clk-next with 2
> > > > exceptions:
> > > >
> > > > 1) I did not apply "[PATCH 30/42] ARM: dts: AM35xx: use DT clock
Hi,
I finally found some time to update the proposed binding
documentation for omap3isp according to the comments on RFCv1.
Changes since v1:
* Use common DT clock bindings to provide isp-xclk
* Use common DT video-interface bindings to specify device connections
* Apply style updates suggeste
On Mon, Jan 13, 2014 at 22:27 -0800, Paul Walmsley wrote:
>
> On Thu, 19 Dec 2013, Stephen Warren wrote:
>
> >On 12/19/2013 05:49 AM, Paul Walmsley wrote:
> >>Add basic DT bindings for the DFLL IP block for the NVIDIA Tegra114 SoC.
> >
> >>diff --git
> >>a/Documentation/devicetree/bindings/clock
Hi,
>> +- clocks : Reference to the clock entry.
>> +- phys : PHY reference with parameter 0.
>
> The specific value of the phy-specifier shouldn't matter to this
> binding. What should matter is what it logically corresponds to.
I not quite following this. Are y
On 01/15/2014 11:50 AM, Gerhard Sittig wrote:
On Mon, Jan 13, 2014 at 22:27 -0800, Paul Walmsley wrote:
On Thu, 19 Dec 2013, Stephen Warren wrote:
On 12/19/2013 05:49 AM, Paul Walmsley wrote:
Add basic DT bindings for the DFLL IP block for the NVIDIA Tegra114 SoC.
diff --git a/Documentation/d
On Wednesday 15 January 2014 12:04:02 Loc Ho wrote:
>
> >> +- clocks : Reference to the clock entry.
> >> +- phys : PHY reference with parameter 0.
> >
> > The specific value of the phy-specifier shouldn't matter to this
> > binding. What should matter is what it
Hi,
> [...]
>
>> + * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
>> + * The first PLL clock macro is used for internal reference clock. The
>> second
>> + * PLL clock macro is used to generate the clock for the PHY. This driver
>> + * configures the first PLL CMU, the se
On Wed, 15 Jan 2014, Hans de Goede wrote:
> Hi All,
>
> This version of my ohci and ehci-platform clks, phy and dt support patch-set,
> really fixes the 2 small bugs Alan found.
All okay -- this time I can't find anything to complain about. :-)
Alan Stern
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Hi,
>>
>> >> +- clocks : Reference to the clock entry.
>> >> +- phys : PHY reference with parameter 0.
>> >
>> > The specific value of the phy-specifier shouldn't matter to this
>> > binding. What should matter is what it logically corresponds to.
>>
>> I not quit
On Wednesday 15 January 2014 13:08:47 Loc Ho wrote:
> >> >> +- clocks : Reference to the clock entry.
> >> >> +- phys : PHY reference with parameter 0.
> >> >
> >> > The specific value of the phy-specifier shouldn't matter to this
> >> > binding. What should matter
Some hardware may be broken in interesting and board-specific ways, such
that various bits of functionality don't work. This patch provides a
mechanism for overriding mii registers during init based on the contents of
the device tree data, allowing board-specific fixups without having to
pollute ge
This series enables the use of the additional cores on Rockchip
Cortex-A9 SoCs.
To achieve this, add the scu, the needed sram and power-management-unit.
Tested on both a BQ Curie2 (rk3066a / dual core) and
on a Radxa Rock (rk3188 / quad core).
changes since v5:
- Grant Likely liked it better to
Some SoCs need parts of their sram for special purposes. So while being part
of the peripheral, it should not be part of the genpool controlling the sram.
Therefore add an option mmio-sram-reserved to keep arbitrary portions of the
sram from general usage.
Suggested-by: Rob Herring
Signed-off-by
Add dt-nodes for the sram on rk3066 and rk3188 including the reserved section
needed for smp bringup.
Signed-off-by: Heiko Stuebner
Tested-by: Ulrich Prinz
---
.../devicetree/bindings/arm/rockchip/smp-sram.txt | 23
arch/arm/boot/dts/rk3066a.dtsi |
This adds the device-node and config select to enable the
scu in all Rockchip Cortex-A9 SoCs.
Signed-off-by: Heiko Stuebner
Tested-by: Ulrich Prinz
---
arch/arm/boot/dts/rk3xxx.dtsi |5 +
arch/arm/mach-rockchip/Kconfig |1 +
2 files changed, 6 insertions(+)
diff --git a/arch/arm/b
This implements support for the mmio-sram-reserved option to keep the
genpool from using these areas.
Suggested-by: Rob Herring
Signed-off-by: Heiko Stuebner
Tested-by: Ulrich Prinz
---
drivers/misc/sram.c | 118 +++
1 file changed, 110 insertio
The pmu is needed to bring up the cores during smp operations and later
also other system parts. Therefore add a node and documentation for it.
Signed-off-by: Heiko Stuebner
Tested-by: Ulrich Prinz
---
Documentation/devicetree/bindings/arm/rockchip/pmu.txt | 16
arch/arm/boot
This adds the necessary smp-operations and startup code to use
additional cores on Rockchip SoCs.
We currently hog the power management unit in the smp code, as it is
necessary to control the power to the cpu core and nothing else is
currently using it, so a generic implementation can be done late
Hi,
>> >> >> +- clocks : Reference to the clock entry.
>> >> >> +- phys : PHY reference with parameter 0.
>> >> >
>> >> > The specific value of the phy-specifier shouldn't matter to this
>> >> > binding. What should matter is what it logically corresponds to.
>> >
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