I actually get a very strange behavior now.
Every time I rerun my program , the output of the logic analyzer changes.
But the output that comes up the most often is the one I described before
where bit 1 toggles, and bit 5 is asserted (sometimes) .
What I am trying to do is to get some delay meas
On 11/17/06, Brian Padalino <[EMAIL PROTECTED]> wrote:
On 11/17/06, Oussama Sekkat <[EMAIL PROTECTED]> wrote:
>
> Ok.
> I fixed it now by making it a source instead. Thanks.
> My output reading from the logic analyzer is now the following constant
16
> bit value: 1100 0011
> This seems
On 11/17/06, Oussama Sekkat <[EMAIL PROTECTED]> wrote:
Ok.
I fixed it now by making it a source instead. Thanks.
My output reading from the logic analyzer is now the following constant 16
bit value: 1100 0011
This seems to me a too high of a value since I shouldn't be receiving any
sig
On 11/17/06, Eric Blossom <[EMAIL PROTECTED]> wrote:
On Fri, Nov 17, 2006 at 07:13:05PM -0800, Oussama Sekkat wrote:
> Hi,
>
> I am still trying to measure the digital output noise (from the LFRX_A
> daughterboard).
> In the verilog code I made sure to connect the rx_a_a input to the
debug1
> in
On Fri, Nov 17, 2006 at 07:13:05PM -0800, Oussama Sekkat wrote:
> Hi,
>
> I am still trying to measure the digital output noise (from the LFRX_A
> daughterboard).
> In the verilog code I made sure to connect the rx_a_a input to the debug1
> input of the master control module
> master_control mas
How many times did you get unhappy after being shy to take off your clothes in
a romantic moment? 0be~sity
does not only affect the way you look and feel about yourself. It is
also dangerous for your health, bringing plenty of health problems in a
variety of spheres. And of course feeling shy to t
Hi,
I am still trying to measure the digital output noise (from the LFRX_A
daughterboard).
In the verilog code I made sure to connect the rx_a_a input to the debug1
input of the master control module
master_control master_control
( .master_clk(clk64),.usbclk(usbclk) ...
...
On Fri, 17 Nov 2006, Jonathan Jacky wrote:
In fft_sink, fft_rate is the number of frames fft_sink
attempts to draw per second. Try adjusting it down. There is a similar
parameter frame_decim in scope_sink, again adjust this down until the display
updates and the program works.
Correction
On Fri, Nov 17, 2006 at 12:35:18PM -0400, Ryan Seal wrote:
> Eric Blossom wrote:
> >
> >The problem doesn't appear to be platform specific. In general our
> >current plotting code is dog slow. It's mostly implemented in Python
> >and could use a serious overhaul.
> >
> >There's an enhancement req
On Thu, Nov 16, 2006 at 10:10:23PM +, Newell Jensen wrote:
> As I am new to all this please correct me if I am wrong as I am trying to
> get a better understanding of everything. I am assuming that even though
> you are able run linux on the PS3 that you will not be able to use gnuradio
> a
Eric Blossom wrote:
On Fri, Nov 17, 2006 at 11:15:22AM -0500, Don Ward wrote:
I haven't been playing with the fft scope for a while until yesterday,
when I realized that it frequently hangs on my fc5 with two weeks ago
trunk gnuradio... The scope freezes (in all modes) and it needs to be
ki
On Fri, Nov 17, 2006 at 11:15:22AM -0500, Don Ward wrote:
> >I haven't been playing with the fft scope for a while until yesterday,
> >when I realized that it frequently hangs on my fc5 with two weeks ago
> >trunk gnuradio... The scope freezes (in all modes) and it needs to be
> >killed to get t
On Fri, 17 Nov 2006, Matteo Campanella wrote:
fft scope ... frequently hangs on my fc5
The scope freezes (in all modes) and it needs to be killed to get the
control back.
Has anyone experienced the same?
A GNU Radio flowgraph can generate samples much faster than wxPython can
display the
Don Ward wrote:
I haven't been playing with the fft scope for a while until
yesterday, when I realized that it frequently hangs on my fc5 with
two weeks ago trunk gnuradio... The scope freezes (in all modes) and
it needs to be killed to get the control back. No underruns or any
messgae that co
On Fri, Nov 17, 2006 at 01:02:31AM -0800, seph 004 wrote:
> Hi
>
> Thanks for responding. So WR & ~write_count[8] should be able to
> serve as a write enable for a ram block?
> Also, while testing with one of the unmodified FPGA builds, I found
> that the have_space control line would sometimes
I haven't been playing with the fft scope for a while until yesterday,
when I realized that it frequently hangs on my fc5 with two weeks ago
trunk gnuradio... The scope freezes (in all modes) and it needs to be
killed to get the control back. No underruns or any messgae that could
give a furthe
--
Message: 3
Date: Thu, 16 Nov 2006 12:44:48 -0800
From: Eric Blossom <[EMAIL PROTECTED]>
Subject: Re: [Discuss-gnuradio] Help with Verilog: write_count[8]
To: seph 004 <[EMAIL PROTECTED]>
Cc: discuss-gnuradio@gnu.org
Message-ID: <[EMAIL PROTECTED]>
Content-Type:
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