Hi Ketan,
I have also noticed the flipping , but not when transmitting only when
restarting, the signal flips 90 degree.
but this only happens when using the subdev, when using gr.sig_source_c this
doesn't happen.
I couldn't see why this only happens with subdev.
Anmar,
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get sin and cos,
but these are the I and Q singles.
did any one tried to doe this, and have it actually working?
please help thanks.
Anmar
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Roshan Baliga wrote:
The AD9862s (which are on the motherboard) both get the same clock from
AD9513 clock distribution IC. The only difference is that the clock
signal goes through separate (but identical) filters on its way to each
AD9862.
ok thanks a lot guys, I know enough now for trying
Eric Blossom wrote:
On Fri, Apr 20, 2007 at 08:26:25PM +0200, Anmar wrote:
explain why this is happening?
OK, here goes, one more time: there is state in the AD9862 -- its DUC
phase register -- that we can't control from software.
Do you understand what that means?
Yes
Have you looked
with the phase, probably not :).
Anmar
Eric
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it, and have got it working?
Thanks
Anmar
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Hi, I was looking at the UsrpTxModifications page in wiki, I want to
understand how the Tx goes.
my question is what is the spi_bus that goes into the data block and come out
of the command block, is it internal in the FPGA? looking at the
UsrpRfxDiagrams in the first digram I see the signal
hi Eric,
I'm not sure what you are looking for.
I just want to send a signal that is time shifted, or how to make my own
waveform?
thanks,
anmar
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other variables that have effect on the output frq.
can someone give us some advice?
thank you,
Wim anmar
def main():
interp = 32
waveform_type = gr.GR_SIN_WAVE
waveform_ampl = 32000
waveform_freq1 = 1e6
waveform_freq2 = 2e6
waveform_offset = 1
fg
interleave
what is going wrong this is not much different of the
fm_tx_2_daughterboard.py.
Thanks
anmar
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, i didn't noticed that, didn't even looked
there ops
Anmar
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hi,
when i load the fm_tx_2_daughterboards.py I see on the scoop that the
output of channel 2 is AM modulated, why is that?
and the output of the 1st channel is not modulated,
what i'm doing wrong?
Tuning side A to 10MHz
r.baseband_freq = 0
r.dxc_freq = 10M
r.residual_freq = 0
(gr.sizeof_gr_complex)'
thanks
anmar
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Eric Blossom wrote:
On Wed, Feb 21, 2007 at 11:11:17AM +0100, anmar wrote:
stream of complexes. (Yes, the interface is a bit strange and ought
fg.connect(interleaver, u)
That's right. If you're using a single Basic Tx daughterboard, and
you want independent real output out the I and Q
Eric Blossom wrote:
On Tue, Feb 20, 2007 at 03:41:31PM +0100, anmar wrote:
hi all,
we have been searching for a way to transmit two independent signals one
on TxA and the other on TxB.
Using two daughterboards, you can send different complex baseband
signals out the A side d'board
give
conflicts with the FPGA and the software.
is there some thing that we're missing or just not understanding.
thanks,
Wim anmar
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