Re: [Discuss-gnuradio] Block diagram of FPGA interface

2005-04-19 Thread Anastasopoulos Achilleas
Is this comment relevant for the Tx only or for both TX and Rx ? > Just one minor correction from what I said before. The way you show the > multipliers and the NCO is not quite correct. It is doing a full > complex > multiplication. The CORDIC does the NCO and the multiplication > together. >

Re: [Discuss-gnuradio] Block diagram of FPGA interface

2005-04-18 Thread Matt Ettus
Quoting Achilleas Anastasopoulos <[EMAIL PROTECTED]>: > Dear all, > > I am trying to understand exactly what kind of SP > is going on the Rx and Tx path of the FPGA and basic > Rx/Tx. > > I am attaching an eps file (and an xfig file) with a hypothesized block > diagram that is the result of all th

Re: [Discuss-gnuradio] Block diagram of FPGA interface

2005-04-18 Thread Matt Ettus
Quoting "Damien B." <[EMAIL PROTECTED]>: > Hi Matt, > I came up with the same diagram with a few difference. Could you confirm them > ? > > - the cordic stage in TX chain is disable (V0.8) > > - DA converter can work at 128MS/s but the txsync is muxing at 32MS/s > for each channel Sort of. The A

Re: [Discuss-gnuradio] Block diagram of FPGA interface

2005-04-18 Thread Damien B.
Hi Matt, I came up with the same diagram with a few difference. Could you confirm them ? - the cordic stage in TX chain is disable (V0.8) - DA converter can work at 128MS/s but the txsync is muxing at 32MS/s for each channel Thanks, cheers Damien On 4/19/05, Matt Ettus <[EMAIL PROTECTED]> wrote

Re: [Discuss-gnuradio] Block diagram of FPGA interface

2005-04-18 Thread Matt Ettus
Quoting Achilleas Anastasopoulos <[EMAIL PROTECTED]>: > Dear all, > > I am trying to understand exactly what kind of SP > is going on the Rx and Tx path of the FPGA and basic > Rx/Tx. > > I am attaching an eps file (and an xfig file) with a hypothesized block > diagram that is the result

[Discuss-gnuradio] Block diagram of FPGA interface

2005-04-18 Thread Achilleas Anastasopoulos
Dear all, I am trying to understand exactly what kind of SP is going on the Rx and Tx path of the FPGA and basic Rx/Tx. I am attaching an eps file (and an xfig file) with a hypothesized block diagram that is the result of all the information I have collected on the website and the discussions. Can