Hi Brennan,
This is great. I am curious, has this been released or you are still
working on it?
Thanks
Milos
On Thu, 31 Jan 2019 at 20:35, Brennan Ashton
wrote:
> In addition to what Ron mentioned there is an FPGA implementation of the
> LDPC portion of DVB-S2 that I will be releasing late
In addition to what Ron mentioned there is an FPGA implementation of the
LDPC portion of DVB-S2 that I will be releasing late February (I hoped to
be ready to relase it by FOSDEM, but work got in the way) which achieves
the full bitrate. The initial release will not be integrated with RFNoC,
but
The processing requirement for DVB-S2 are significant, especially the
receiver. Since you're using an X-series USRP, I'll guess you're
interested in satellite downlinks which can be 30 to 50 Msyms/s.
Basically, the requirement would be the most powerful system you can
afford. Something with
Hi there!
My name is Maria and I would like to make a question regarding the kind
of PC characteristics which would be required to be able to process the
signal in real-time (on the PC) when using the maximum bandwidth
available on the USRP X-series.
The scenario would be the following one:
